Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	903	1			T10	4		T27	4		T36	14
all_values[1]	903	1			T10	4		T27	4		T36	14
all_values[2]	903	1			T10	4		T27	4		T36	14
all_values[3]	903	1			T10	4		T27	4		T36	14
all_values[4]	903	1			T10	4		T27	4		T36	14
all_values[5]	903	1			T10	4		T27	4		T36	14
all_values[6]	903	1			T10	4		T27	4		T36	14
all_values[7]	903	1			T10	4		T27	4		T36	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3787

1

T10

10

T27

16

T36

58

auto[1]

3437

1

T10

22

T27

16

T36

54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2958

1

T10

13

T27

12

T36

47

auto[1]

4266

1

T10

19

T27

20

T36

65

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4174

1

T10

22

T27

16

T36

67

auto[1]

3050

1

T10

10

T27

16

T36

45

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	190	1			T36	3		T64	2		T65	8
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T27	1		T36	1		T64	2
all_values[0]	auto[0]	auto[1]	auto[0]	170	1			T10	1		T27	1		T36	3
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T10	1		T36	1		T64	2
all_values[0]	auto[1]	auto[0]	auto[1]	197	1			T27	1		T36	4		T64	6
all_values[0]	auto[1]	auto[1]	auto[1]	181	1			T10	2		T27	1		T36	2
all_values[1]	auto[0]	auto[0]	auto[0]	190	1			T36	1		T64	10		T65	2
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T10	1		T27	1		T138	3
all_values[1]	auto[0]	auto[1]	auto[0]	155	1			T36	3		T64	3		T65	3
all_values[1]	auto[0]	auto[1]	auto[1]	92	1			T10	2		T36	3		T65	1
all_values[1]	auto[1]	auto[0]	auto[1]	211	1			T10	1		T27	3		T36	4
all_values[1]	auto[1]	auto[1]	auto[1]	170	1			T36	3		T64	1		T65	5
all_values[2]	auto[0]	auto[0]	auto[0]	195	1			T10	2		T36	1		T64	7
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T36	4		T64	1		T65	3
all_values[2]	auto[0]	auto[1]	auto[0]	141	1			T27	2		T36	1		T64	3
all_values[2]	auto[0]	auto[1]	auto[1]	97	1			T10	1		T36	2		T65	1
all_values[2]	auto[1]	auto[0]	auto[1]	220	1			T36	3		T64	5		T65	3
all_values[2]	auto[1]	auto[1]	auto[1]	167	1			T10	1		T27	2		T36	3
all_values[3]	auto[0]	auto[0]	auto[0]	180	1			T36	6		T64	3		T65	2
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T64	2		T65	4		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	213	1			T10	1		T27	3		T36	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T10	1		T36	1		T64	2
all_values[3]	auto[1]	auto[0]	auto[1]	175	1			T10	1		T36	3		T64	1
all_values[3]	auto[1]	auto[1]	auto[1]	175	1			T10	1		T27	1		T36	3
all_values[4]	auto[0]	auto[0]	auto[0]	194	1			T10	1		T36	2		T64	5
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T10	2		T64	2		T21	1
all_values[4]	auto[0]	auto[1]	auto[0]	148	1			T27	2		T36	4		T64	2
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T36	2		T65	2		T138	1
all_values[4]	auto[1]	auto[0]	auto[1]	190	1			T36	2		T64	5		T65	2
all_values[4]	auto[1]	auto[1]	auto[1]	194	1			T10	1		T27	2		T36	4
all_values[5]	auto[0]	auto[0]	auto[0]	271	1			T10	1		T27	2		T36	3
all_values[5]	auto[0]	auto[1]	auto[0]	255	1			T10	3		T36	5		T64	4
all_values[5]	auto[1]	auto[0]	auto[1]	189	1			T27	2		T36	3		T64	2
all_values[5]	auto[1]	auto[1]	auto[1]	188	1			T36	3		T64	4		T65	6
all_values[6]	auto[0]	auto[0]	auto[0]	169	1			T27	2		T36	1		T64	5
all_values[6]	auto[0]	auto[0]	auto[1]	96	1			T36	3		T64	2		T65	1
all_values[6]	auto[0]	auto[1]	auto[0]	135	1			T36	2		T64	2		T65	6
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T10	1		T27	1		T36	1
all_values[6]	auto[1]	auto[0]	auto[1]	233	1			T10	1		T36	3		T64	5
all_values[6]	auto[1]	auto[1]	auto[1]	186	1			T10	2		T27	1		T36	4
all_values[7]	auto[0]	auto[0]	auto[0]	199	1			T36	10		T64	6		T65	3
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T27	1		T64	2		T21	1
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T10	4		T36	1		T64	3
all_values[7]	auto[0]	auto[1]	auto[1]	98	1			T36	2		T64	2		T21	3
all_values[7]	auto[1]	auto[0]	auto[1]	203	1			T27	3		T36	1		T64	2
all_values[7]	auto[1]	auto[1]	auto[1]	171	1			T64	2		T65	2		T21	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal