Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6776783	1			T2	1		T3	10126		T4	1805
all_values[1]	6776783	1			T2	1		T3	10126		T4	1805
all_values[2]	6776783	1			T2	1		T3	10126		T4	1805
all_values[3]	6776783	1			T2	1		T3	10126		T4	1805
all_values[4]	6776783	1			T2	1		T3	10126		T4	1805
all_values[5]	6776783	1			T2	1		T3	10126		T4	1805
all_values[6]	6776783	1			T2	1		T3	10126		T4	1805
all_values[7]	6776783	1			T2	1		T3	10126		T4	1805

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52840863

1

T2

8

T3

81008

T4

14440

auto[1]

1373401

1

T31

62

T20

196766

T57

69

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54134724

1

T2

8

T3

80996

T4

14370

auto[1]

79540

1

T3

12

T4

70

T11

538

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6622764	1			T2	1		T3	10126		T4	1758
all_values[0]	auto[0]	auto[1]	44435	1			T4	47		T11	274		T12	342
all_values[0]	auto[1]	auto[0]	108881	1			T31	4		T20	48665		T57	7
all_values[0]	auto[1]	auto[1]	703	1			T31	3		T20	515		T57	3
all_values[1]	auto[0]	auto[0]	6504809	1			T2	1		T3	10126		T4	1785
all_values[1]	auto[0]	auto[1]	22798	1			T4	20		T11	226		T12	342
all_values[1]	auto[1]	auto[0]	248576	1			T31	6		T20	48891		T57	3
all_values[1]	auto[1]	auto[1]	600	1			T31	4		T20	285		T57	3
all_values[2]	auto[0]	auto[0]	6693498	1			T2	1		T3	10126		T4	1802
all_values[2]	auto[0]	auto[1]	8368	1			T4	3		T11	38		T12	146
all_values[2]	auto[1]	auto[0]	74592	1			T31	8		T20	7		T57	4
all_values[2]	auto[1]	auto[1]	325	1			T31	3		T20	5		T57	3
all_values[3]	auto[0]	auto[0]	6553816	1			T2	1		T3	10126		T4	1805
all_values[3]	auto[0]	auto[1]	201	1			T31	2		T20	6		T57	3
all_values[3]	auto[1]	auto[0]	222581	1			T31	4		T20	49172		T57	10
all_values[3]	auto[1]	auto[1]	185	1			T31	4		T20	4		T144	2
all_values[4]	auto[0]	auto[0]	6742549	1			T2	1		T3	10126		T4	1805
all_values[4]	auto[0]	auto[1]	223	1			T31	6		T57	3		T144	2
all_values[4]	auto[1]	auto[0]	33775	1			T31	4		T20	13		T57	3
all_values[4]	auto[1]	auto[1]	236	1			T31	6		T20	4		T57	7
all_values[5]	auto[0]	auto[0]	6625879	1			T2	1		T3	10114		T4	1805
all_values[5]	auto[0]	auto[1]	456	1			T3	12		T31	4		T20	3
all_values[5]	auto[1]	auto[0]	150264	1			T31	1		T20	49177		T57	6
all_values[5]	auto[1]	auto[1]	184	1			T20	6		T57	3		T58	3
all_values[6]	auto[0]	auto[0]	6580160	1			T2	1		T3	10126		T4	1805
all_values[6]	auto[0]	auto[1]	218	1			T31	5		T20	8		T57	3
all_values[6]	auto[1]	auto[0]	196208	1			T31	4		T20	2		T57	5
all_values[6]	auto[1]	auto[1]	197	1			T31	2		T20	6		T57	2
all_values[7]	auto[0]	auto[0]	6440487	1			T2	1		T3	10126		T4	1805
all_values[7]	auto[0]	auto[1]	202	1			T31	5		T20	1		T57	5
all_values[7]	auto[1]	auto[0]	335885	1			T31	5		T20	9		T57	7
all_values[7]	auto[1]	auto[1]	209	1			T31	4		T20	5		T57	3