Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	41317	1			T2	12		T4	144		T5	8
auto[SpiFlashAddrCfg]	9377	1			T2	4		T4	23		T5	6
auto[SpiFlashAddr3b]	11269	1			T2	4		T4	25		T13	4
auto[SpiFlashAddr4b]	9373	1			T2	6		T4	13		T5	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41456

1

T4

85

T8

10

T9

30

auto[1]

29880

1

T2

26

T4

120

T5

18

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38000

1

T2

14

T4

119

T5

10

auto[1]

33336

1

T2

12

T4

86

T5

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	46974	1			T2	18		T4	151		T5	6
values[1]	1343	1			T4	6		T11	3		T12	2
values[2]	1831	1			T4	6		T5	2		T11	12
values[3]	1796	1			T4	1		T8	5		T11	12
values[4]	1798	1			T4	7		T11	5		T12	2
values[5]	1747	1			T4	7		T11	10		T12	3
values[6]	1797	1			T2	4		T11	12		T12	6
values[7]	1797	1			T4	2		T11	9		T12	8
values[8]	12253	1			T2	4		T4	25		T5	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34858

1

T2

26

T5

18

T9

30

auto[1]

36478

1

T4

205

T8

10

T11

354

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

68671

1

T2

22

T4

199

T5

18

write

2665

1

T2

4

T4

6

T11

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

24243

1

T2

10

T4

56

T5

4

valids[0x1]

47093

1

T2

16

T4

149

T5

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1843	1			T4	2		T11	12		T12	9
internal_process_ops[0x5a]	2030	1			T4	4		T11	25		T12	9
internal_process_ops[0x05]	24104	1			T4	107		T11	48		T12	38
internal_process_ops[0x35]	2014	1			T4	1		T11	15		T12	7
internal_process_ops[0x15]	2082	1			T2	8		T4	6		T5	4
internal_process_ops[0x03]	1257	1			T4	2		T13	2		T11	4
internal_process_ops[0x0b]	1424	1			T4	2		T12	8		T15	4
internal_process_ops[0x3b]	1327	1			T4	2		T5	2		T11	2
internal_process_ops[0x6b]	1314	1			T2	4		T4	1		T11	4
internal_process_ops[0xbb]	1299	1			T8	5		T11	7		T12	7
internal_process_ops[0xeb]	1366	1			T4	1		T8	5		T11	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70075

1

T2

22

T4

203

T5

18

auto[1]

1261

1

T2

4

T4

2

T11

10

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68836

1

T2

26

T4

199

T5

18

auto[1]

2500

1

T4

6

T11

10

T12

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12185

1

T9

30

T13

2

T12

50

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6454

1

T2

8

T5

8

T12

41

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2465

1

T13

2

T12

18

T25

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2187

1

T2

4

T5

6

T12

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3017

1

T13

4

T12

19

T14

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2548

1

T2

4

T12

17

T25

5

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2663

1

T13

4

T12

7

T25

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2161

1

T2

6

T5

4

T12

12

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

104

1

T26

1

T28

1

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

59

1

T12

1

T28

2

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

65

1

T26

1

T28

2

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T2

4

T12

1

T26

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

85

1

T12

2

T28

1

T30

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

58

1

T12

2

T31

1

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

53

1

T12

1

T30

1

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

85

1

T25

2

T30

1

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T30

1

T33

1

T145

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

61

1

T12

5

T25

2

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

63

1

T12

1

T28

3

T30

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

77

1

T30

1

T31

5

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

86

1

T28

1

T30

1

T31

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

62

1

T12

1

T26

2

T146

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

64

1

T26

2

T28

1

T30

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

74

1

T12

2

T26

3

T29

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12929

1

T4

52

T11

111

T18

150

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9051

1

T4

88

T11

55

T18

50

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2187

1

T4

13

T8

5

T11

24

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1884

1

T4

10

T11

36

T18

30

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2659

1

T4

10

T11

42

T15

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2389

1

T4

13

T11

30

T18

28

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1996

1

T4

9

T8

5

T11

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1896

1

T4

4

T11

34

T18

28

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T11

1

T18

2

T31

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T11

4

T31

2

T58

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T4

3

T18

1

T31

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

67

1

T4

1

T31

3

T118

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

89

1

T31

2

T20

1

T144

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T18

4

T57

1

T58

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T31

5

T142

1

T117

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

90

1

T31

2

T147

2

T148

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

93

1

T11

1

T18

1

T31

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T4

1

T11

2

T31

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

102

1

T4

1

T18

6

T20

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

76

1

T11

2

T31

3

T20

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T31

3

T57

2

T147

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T11

2

T18

3

T31

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T18

6

T31

5

T20

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

92

1

T27

1

T31

5

T115

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4843	1			T2	6		T9	30		T13	4
auto[0]	values[0]	valids[0x1]	16942	1			T2	12		T5	6		T13	2
auto[0]	values[1]	valids[0x1]	656	1			T12	2		T25	3		T28	17
auto[0]	values[2]	valids[0x0]	601	1			T5	2		T12	4		T26	6
auto[0]	values[2]	valids[0x1]	366	1			T14	4		T26	6		T28	5
auto[0]	values[3]	valids[0x0]	628	1			T12	3		T25	1		T92	6
auto[0]	values[3]	valids[0x1]	348	1			T12	4		T26	3		T28	10
auto[0]	values[4]	valids[0x0]	652	1			T12	2		T92	2		T26	4
auto[0]	values[4]	valids[0x1]	350	1			T26	8		T28	4		T30	1
auto[0]	values[5]	valids[0x0]	659	1			T12	3		T25	3		T75	2
auto[0]	values[5]	valids[0x1]	332	1			T26	1		T28	4		T30	4
auto[0]	values[6]	valids[0x0]	612	1			T12	2		T25	4		T26	2
auto[0]	values[6]	valids[0x1]	354	1			T2	4		T12	4		T26	4
auto[0]	values[7]	valids[0x0]	615	1			T12	1		T25	1		T92	4
auto[0]	values[7]	valids[0x1]	364	1			T12	7		T26	3		T28	7
auto[0]	values[8]	valids[0x0]	4032	1			T2	4		T5	2		T12	29
auto[0]	values[8]	valids[0x1]	2504	1			T5	8		T13	6		T12	22
auto[1]	values[0]	valids[0x0]	5313	1			T4	23		T11	76		T18	86
auto[1]	values[0]	valids[0x1]	19876	1			T4	128		T11	134		T18	182
auto[1]	values[1]	valids[0x1]	687	1			T4	6		T11	3		T18	10
auto[1]	values[2]	valids[0x0]	515	1			T4	4		T11	8		T15	5
auto[1]	values[2]	valids[0x1]	349	1			T4	2		T11	4		T18	9
auto[1]	values[3]	valids[0x0]	496	1			T8	5		T11	8		T18	7
auto[1]	values[3]	valids[0x1]	324	1			T4	1		T11	4		T18	7
auto[1]	values[4]	valids[0x0]	459	1			T4	6		T11	2		T18	4
auto[1]	values[4]	valids[0x1]	337	1			T4	1		T11	3		T18	5
auto[1]	values[5]	valids[0x0]	447	1			T4	5		T11	6		T18	5
auto[1]	values[5]	valids[0x1]	309	1			T4	2		T11	4		T18	8
auto[1]	values[6]	valids[0x0]	495	1			T11	3		T15	6		T18	8
auto[1]	values[6]	valids[0x1]	336	1			T11	9		T18	8		T27	7
auto[1]	values[7]	valids[0x0]	490	1			T11	7		T18	6		T31	8
auto[1]	values[7]	valids[0x1]	328	1			T4	2		T11	2		T18	3
auto[1]	values[8]	valids[0x0]	3386	1			T4	18		T8	5		T11	55
auto[1]	values[8]	valids[0x1]	2331	1			T4	7		T11	26		T15	4