Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19997

1

T2

1

T4

39

T5

1

auto[1]

24393

1

T4

110

T11

44

T12

39

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16650

1

T2

1

T4

35

T5

1

auto[1]

27740

1

T4

114

T11

72

T12

50

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7472	1			T2	1		T4	16		T5	1
auto[524288:1048575]	5411	1			T9	1		T11	25		T12	33
auto[1048576:1572863]	5269	1			T8	1		T11	16		T12	18
auto[1572864:2097151]	5520	1			T4	17		T8	2		T9	7
auto[2097152:2621439]	5355	1			T4	12		T9	5		T11	18
auto[2621440:3145727]	5812	1			T4	25		T9	6		T11	29
auto[3145728:3670015]	4720	1			T4	2		T8	4		T11	13
auto[3670016:4194303]	4831	1			T4	77		T9	2		T12	14

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43404

1

T2

1

T4

146

T5

1

auto[1]

986

1

T4

3

T11

2

T12

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35064

1

T2

1

T4

94

T5

1

auto[1]

9326

1

T4

55

T9

6

T11

63

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1948	1			T2	1		T4	2		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	812	1			T4	1		T11	2		T12	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1375	1			T11	9		T12	12		T14	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	551	1			T11	3		T12	5		T18	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1326	1			T8	1		T11	5		T12	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	562	1			T11	4		T12	2		T18	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1475	1			T4	4		T8	2		T9	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	533	1			T4	2		T11	8		T12	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1412	1			T4	8		T9	5		T11	8
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	575	1			T4	4		T11	3		T12	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1321	1			T4	1		T9	1		T11	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	510	1			T4	2		T11	1		T12	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1354	1			T4	2		T8	4		T11	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	518	1			T11	1		T12	2		T18	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1352	1			T4	7		T9	2		T12	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	486	1			T4	1		T12	1		T18	5
auto[0]	auto[1]	auto[0:524287]	auto[0]	321	1			T4	1		T11	4		T18	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	156	1			T11	3		T12	2		T26	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	313	1			T9	1		T11	5		T12	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	151	1			T11	6		T18	2		T27	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	322	1			T12	5		T18	3		T26	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	164	1			T12	1		T26	2		T28	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	344	1			T11	4		T12	2		T18	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	195	1			T11	3		T26	1		T27	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	331	1			T11	1		T18	2		T26	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	142	1			T11	1		T18	3		T26	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	320	1			T4	2		T9	5		T11	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	168	1			T11	2		T18	3		T28	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	311	1			T11	5		T12	1		T18	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	159	1			T11	1		T18	2		T26	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	325	1			T4	2		T12	1		T18	10
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	165	1			T18	2		T26	4		T28	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	350	1			T11	1		T12	2		T25	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3176	1			T11	3		T12	5		T25	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	230	1			T11	1		T12	2		T18	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2039	1			T11	1		T12	12		T18	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	233	1			T11	2		T12	1		T26	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2056	1			T11	5		T12	6		T26	9
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	244	1			T4	1		T18	1		T26	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2148	1			T4	10		T18	3		T26	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	256	1			T11	1		T25	3		T18	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2097	1			T11	4		T25	36		T18	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	242	1			T4	1		T11	1		T12	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2154	1			T4	9		T11	1		T12	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	211	1			T26	1		T28	2		T30	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1687	1			T26	2		T28	23		T30	61
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	212	1			T4	1		T12	1		T18	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1619	1			T4	38		T12	7		T18	8
auto[1]	auto[1]	auto[0:524287]	auto[0]	66	1			T4	1		T31	2		T20	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	643	1			T4	11		T31	39		T20	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	61	1			T27	1		T31	1		T20	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	691	1			T27	1		T31	9		T20	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	69	1			T18	1		T31	2		T57	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	537	1			T18	1		T31	33		T57	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	65	1			T11	2		T31	4		T20	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	516	1			T11	4		T31	56		T20	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	58	1			T18	1		T31	1		T57	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	484	1			T18	1		T31	55		T57	17
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	73	1			T4	1		T11	1		T28	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1024	1			T4	9		T11	13		T28	54
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	64	1			T11	1		T18	3		T31	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	416	1			T11	3		T18	7		T31	48
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	66	1			T4	1		T18	5		T26	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	606	1			T4	27		T18	8		T26	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	15738	1			T2	1		T4	34		T5	1
auto[0]	auto[0]	auto[1]	372	1			T25	2		T26	1		T28	3
auto[0]	auto[1]	auto[0]	3767	1			T4	3		T9	6		T11	38
auto[0]	auto[1]	auto[1]	120	1			T4	2		T11	1		T30	2
auto[1]	auto[0]	auto[0]	18569	1			T4	60		T11	20		T12	36
auto[1]	auto[0]	auto[1]	385	1			T12	3		T25	4		T18	1
auto[1]	auto[1]	auto[0]	5330	1			T4	49		T11	23		T18	27
auto[1]	auto[1]	auto[1]	109	1			T4	1		T11	1		T31	9