Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20937

1

T9

30

T13

12

T12

105

auto[1]

13921

1

T2

26

T5

18

T12

89

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4428	1			T12	26		T26	60		T28	40
values[1]	3871	1			T12	20		T25	37		T26	26
values[2]	4470	1			T12	20		T25	50		T75	6
values[3]	4065	1			T12	20		T26	27		T28	82
values[4]	4262	1			T9	30		T12	65		T14	8
values[5]	4534	1			T2	26		T13	12		T92	16
values[6]	4828	1			T26	28		T29	20		T28	71
values[7]	4400	1			T5	18		T12	43		T26	120

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4129	1			T12	43		T26	57		T29	20
values[1]	3914	1			T2	26		T25	20		T28	93
values[2]	4042	1			T75	6		T26	20		T28	66
values[3]	4189	1			T12	40		T25	50		T85	10
values[4]	5294	1			T9	30		T13	12		T12	25
values[5]	3768	1			T26	20		T28	81		T31	20
values[6]	5126	1			T5	18		T12	40		T26	138
values[7]	4396	1			T12	46		T14	8		T25	37

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	278	1			T30	76		T143	11		T116	22
auto[0]	values[0]	values[1]	294	1			T30	17		T180	24		T172	30
auto[0]	values[0]	values[2]	260	1			T102	8		T146	12		T143	14
auto[0]	values[0]	values[3]	505	1			T28	9		T30	12		T33	12
auto[0]	values[0]	values[4]	289	1			T28	11		T32	7		T33	10
auto[0]	values[0]	values[5]	307	1			T26	11		T34	13		T160	9
auto[0]	values[0]	values[6]	352	1			T26	9		T175	14		T215	16
auto[0]	values[0]	values[7]	292	1			T12	17		T26	10		T146	11
auto[0]	values[1]	values[0]	182	1			T28	11		T21	25		T213	16
auto[0]	values[1]	values[1]	302	1			T194	26		T216	28		T190	9
auto[0]	values[1]	values[2]	231	1			T31	9		T66	9		T184	16
auto[0]	values[1]	values[3]	252	1			T191	18		T170	36		T179	24
auto[0]	values[1]	values[4]	313	1			T31	12		T190	9		T21	15
auto[0]	values[1]	values[5]	282	1			T145	34		T146	23		T190	16
auto[0]	values[1]	values[6]	292	1			T12	7		T33	10		T195	26
auto[0]	values[1]	values[7]	400	1			T25	8		T26	18		T28	9
auto[0]	values[2]	values[0]	386	1			T31	14		T116	15		T160	94
auto[0]	values[2]	values[1]	319	1			T30	10		T66	11		T170	9
auto[0]	values[2]	values[2]	247	1			T75	6		T28	28		T160	15
auto[0]	values[2]	values[3]	453	1			T25	16		T31	9		T170	58
auto[0]	values[2]	values[4]	418	1			T32	9		T175	32		T169	34
auto[0]	values[2]	values[5]	258	1			T171	6		T217	71		T49	13
auto[0]	values[2]	values[6]	503	1			T12	11		T26	30		T31	27
auto[0]	values[2]	values[7]	231	1			T66	28		T160	26		T218	22
auto[0]	values[3]	values[0]	254	1			T219	4		T34	9		T220	22
auto[0]	values[3]	values[1]	253	1			T31	8		T33	16		T146	24
auto[0]	values[3]	values[2]	321	1			T31	10		T221	14		T159	6
auto[0]	values[3]	values[3]	283	1			T12	10		T30	22		T222	8
auto[0]	values[3]	values[4]	446	1			T28	18		T33	8		T116	9
auto[0]	values[3]	values[5]	176	1			T21	13		T192	10		T161	11
auto[0]	values[3]	values[6]	408	1			T189	12		T223	15		T170	10
auto[0]	values[3]	values[7]	374	1			T26	21		T28	11		T224	6
auto[0]	values[4]	values[0]	344	1			T26	25		T28	15		T31	15
auto[0]	values[4]	values[1]	358	1			T25	9		T28	38		T161	7
auto[0]	values[4]	values[2]	288	1			T141	20		T225	6		T66	18
auto[0]	values[4]	values[3]	331	1			T12	16		T32	18		T33	22
auto[0]	values[4]	values[4]	348	1			T9	30		T12	23		T146	13
auto[0]	values[4]	values[5]	179	1			T31	8		T160	11		T226	4
auto[0]	values[4]	values[6]	522	1			T30	9		T33	35		T227	14
auto[0]	values[4]	values[7]	252	1			T12	8		T14	8		T39	55
auto[0]	values[5]	values[0]	290	1			T30	15		T143	13		T116	20
auto[0]	values[5]	values[1]	166	1			T228	2		T191	18		T192	8
auto[0]	values[5]	values[2]	444	1			T26	8		T175	25		T73	10
auto[0]	values[5]	values[3]	229	1			T30	7		T160	35		T213	10
auto[0]	values[5]	values[4]	402	1			T13	12		T92	16		T26	11
auto[0]	values[5]	values[5]	402	1			T28	67		T159	9		T66	12
auto[0]	values[5]	values[6]	389	1			T31	13		T146	6		T176	10
auto[0]	values[5]	values[7]	319	1			T28	8		T229	22		T159	12
auto[0]	values[6]	values[0]	453	1			T28	10		T230	4		T66	16
auto[0]	values[6]	values[1]	234	1			T28	15		T143	10		T160	9
auto[0]	values[6]	values[2]	294	1			T28	11		T30	11		T31	8
auto[0]	values[6]	values[3]	237	1			T31	16		T231	12		T146	9
auto[0]	values[6]	values[4]	626	1			T26	10		T31	24		T146	11
auto[0]	values[6]	values[5]	347	1			T33	20		T175	8		T170	89
auto[0]	values[6]	values[6]	425	1			T140	22		T217	98		T188	10
auto[0]	values[6]	values[7]	361	1			T30	10		T33	11		T232	22
auto[0]	values[7]	values[0]	347	1			T12	13		T26	11		T30	9
auto[0]	values[7]	values[1]	267	1			T28	8		T175	9		T170	13
auto[0]	values[7]	values[2]	243	1			T173	30		T21	15		T135	37
auto[0]	values[7]	values[3]	292	1			T28	21		T30	11		T214	10
auto[0]	values[7]	values[4]	334	1			T26	8		T146	12		T233	6
auto[0]	values[7]	values[5]	364	1			T234	16		T21	16		T160	12
auto[0]	values[7]	values[6]	327	1			T26	8		T28	7		T159	12
auto[0]	values[7]	values[7]	362	1			T208	24		T235	26		T182	18
auto[1]	values[0]	values[0]	209	1			T30	5		T143	9		T116	6
auto[1]	values[0]	values[1]	250	1			T30	3		T159	32		T160	7
auto[1]	values[0]	values[2]	112	1			T146	8		T143	6		T159	7
auto[1]	values[0]	values[3]	253	1			T28	11		T30	8		T33	8
auto[1]	values[0]	values[4]	364	1			T28	9		T32	46		T33	10
auto[1]	values[0]	values[5]	256	1			T26	9		T34	10		T160	11
auto[1]	values[0]	values[6]	191	1			T26	11		T175	6		T67	18
auto[1]	values[0]	values[7]	216	1			T12	9		T26	10		T146	9
auto[1]	values[1]	values[0]	178	1			T28	25		T21	19		T213	7
auto[1]	values[1]	values[1]	145	1			T190	11		T116	8		T213	12
auto[1]	values[1]	values[2]	152	1			T31	14		T236	20		T66	11
auto[1]	values[1]	values[3]	181	1			T191	11		T170	14		T179	7
auto[1]	values[1]	values[4]	206	1			T31	8		T190	18		T21	11
auto[1]	values[1]	values[5]	202	1			T146	7		T190	7		T160	15
auto[1]	values[1]	values[6]	233	1			T12	13		T33	15		T184	4
auto[1]	values[1]	values[7]	320	1			T25	29		T26	8		T28	19
auto[1]	values[2]	values[0]	131	1			T31	6		T116	5		T160	9
auto[1]	values[2]	values[1]	388	1			T30	11		T237	12		T210	24
auto[1]	values[2]	values[2]	195	1			T28	11		T160	65		T161	11
auto[1]	values[2]	values[3]	236	1			T25	34		T31	37		T170	15
auto[1]	values[2]	values[4]	298	1			T32	11		T175	15		T213	6
auto[1]	values[2]	values[5]	110	1			T217	21		T49	7		T238	8
auto[1]	values[2]	values[6]	200	1			T12	9		T26	12		T31	8
auto[1]	values[2]	values[7]	97	1			T66	27		T160	14		T239	3
auto[1]	values[3]	values[0]	183	1			T34	30		T66	14		T120	6
auto[1]	values[3]	values[1]	147	1			T31	20		T33	4		T146	10
auto[1]	values[3]	values[2]	192	1			T31	16		T159	14		T160	10
auto[1]	values[3]	values[3]	182	1			T12	10		T30	21		T146	9
auto[1]	values[3]	values[4]	399	1			T28	44		T33	12		T116	11
auto[1]	values[3]	values[5]	136	1			T21	8		T192	10		T161	9
auto[1]	values[3]	values[6]	119	1			T223	5		T170	10		T217	8
auto[1]	values[3]	values[7]	192	1			T26	6		T28	9		T66	17
auto[1]	values[4]	values[0]	124	1			T26	10		T28	7		T31	7
auto[1]	values[4]	values[1]	198	1			T25	11		T28	15		T161	14
auto[1]	values[4]	values[2]	214	1			T240	18		T66	8		T241	9
auto[1]	values[4]	values[3]	261	1			T12	4		T85	10		T32	31
auto[1]	values[4]	values[4]	164	1			T12	2		T146	7		T161	11
auto[1]	values[4]	values[5]	183	1			T31	12		T160	9		T170	10
auto[1]	values[4]	values[6]	374	1			T30	57		T33	10		T191	10
auto[1]	values[4]	values[7]	122	1			T12	12		T159	13		T135	24
auto[1]	values[5]	values[0]	276	1			T30	5		T143	7		T116	11
auto[1]	values[5]	values[1]	167	1			T2	26		T191	7		T192	36
auto[1]	values[5]	values[2]	277	1			T26	12		T175	3		T223	11
auto[1]	values[5]	values[3]	130	1			T30	13		T160	12		T213	10
auto[1]	values[5]	values[4]	301	1			T26	9		T31	73		T34	8
auto[1]	values[5]	values[5]	226	1			T28	14		T159	21		T66	8
auto[1]	values[5]	values[6]	250	1			T31	7		T146	20		T66	10
auto[1]	values[5]	values[7]	266	1			T28	12		T159	8		T66	12
auto[1]	values[6]	values[0]	297	1			T29	20		T28	14		T66	4
auto[1]	values[6]	values[1]	158	1			T28	5		T143	11		T160	11
auto[1]	values[6]	values[2]	365	1			T28	16		T30	9		T31	39
auto[1]	values[6]	values[3]	235	1			T31	4		T146	11		T143	12
auto[1]	values[6]	values[4]	168	1			T26	18		T31	17		T146	9
auto[1]	values[6]	values[5]	133	1			T33	6		T175	12		T170	6
auto[1]	values[6]	values[6]	185	1			T217	16		T188	10		T49	7
auto[1]	values[6]	values[7]	310	1			T30	79		T33	16		T192	16
auto[1]	values[7]	values[0]	197	1			T12	30		T26	11		T30	11
auto[1]	values[7]	values[1]	268	1			T28	12		T175	15		T170	21
auto[1]	values[7]	values[2]	207	1			T21	9		T135	33		T242	16
auto[1]	values[7]	values[3]	129	1			T28	13		T30	9		T135	5
auto[1]	values[7]	values[4]	218	1			T26	14		T146	39		T170	1
auto[1]	values[7]	values[5]	207	1			T21	10		T160	8		T243	6
auto[1]	values[7]	values[6]	356	1			T5	18		T26	68		T28	13
auto[1]	values[7]	values[7]	282	1			T192	23		T161	9		T184	11