Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	515	1			T12	2		T92	8		T26	6
auto[ReadAddrCrossIntoMailbox]	355	1			T12	2		T26	7		T28	5
auto[ReadAddrCrossOutOfMailbox]	391	1			T26	3		T28	8		T30	3
auto[ReadAddrCrossAllMailbox]	229	1			T75	2		T26	2		T28	5
auto[ReadAddrOutsideMailbox]	4120	1			T2	4		T5	2		T12	27

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2809

1

T2

2

T5

1

T12

10

auto[1]

2801

1

T2

2

T5

1

T12

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	913	1			T12	2		T75	2		T26	5
read_ops[0x0b]	991	1			T12	8		T25	3		T75	2
read_ops[0x3b]	953	1			T5	2		T12	5		T25	3
read_ops[0x6b]	919	1			T2	4		T12	3		T25	2
read_ops[0xbb]	874	1			T12	7		T25	3		T26	7
read_ops[0xeb]	960	1			T12	6		T75	2		T92	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T28	1		T31	1		T32	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T26	1		T31	1		T190	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T32	1		T146	2		T116	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T33	1		T190	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T28	1		T225	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T28	1		T33	1		T225	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T143	1		T175	1		T192	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T116	1		T175	1		T66	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	334	1			T12	1		T75	1		T26	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T12	1		T75	1		T26	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T28	1		T31	1		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	57	1			T12	1		T30	1		T146	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T26	1		T30	1		T223	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T21	1		T66	3		T191	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T31	1		T146	1		T143	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T26	1		T28	2		T31	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T75	1		T33	1		T116	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T75	1		T119	1		T161	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	370	1			T12	1		T25	3		T26	7
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	351	1			T12	6		T26	2		T28	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T26	1		T28	1		T140	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T140	1		T143	1		T192	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T26	3		T28	1		T140	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T12	1		T28	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T28	1		T190	1		T175	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T26	1		T28	1		T30	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T28	2		T140	3		T102	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T28	1		T140	3		T102	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	357	1			T5	1		T12	1		T25	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	331	1			T5	1		T12	3		T25	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T92	1		T26	2		T28	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T92	1		T26	2		T28	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T28	1		T21	1		T160	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T26	1		T28	1		T146	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T26	1		T32	1		T160	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T30	1		T159	1		T21	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T26	1		T34	1		T175	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T31	1		T21	1		T66	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	345	1			T2	2		T25	1		T26	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T2	2		T12	3		T25	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T28	2		T140	1		T225	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T28	1		T31	1		T140	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T26	1		T30	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T30	1		T102	1		T192	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T140	2		T146	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T140	2		T146	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T26	1		T28	1		T140	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T140	1		T146	1		T66	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T12	4		T25	1		T26	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	349	1			T12	3		T25	2		T26	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T92	3		T28	1		T30	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T12	1		T92	3		T146	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T12	1		T26	1		T31	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T28	1		T30	2		T34	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T28	1		T31	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T28	1		T102	1		T146	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T28	1		T159	1		T175	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T120	1		T170	1		T179	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	349	1			T12	2		T75	1		T26	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	361	1			T12	2		T75	1		T26	2