Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6776783	1			T2	1		T3	10126		T4	1805
all_pins[1]	6776783	1			T2	1		T3	10126		T4	1805
all_pins[2]	6776783	1			T2	1		T3	10126		T4	1805
all_pins[3]	6776783	1			T2	1		T3	10126		T4	1805
all_pins[4]	6776783	1			T2	1		T3	10126		T4	1805
all_pins[5]	6776783	1			T2	1		T3	10126		T4	1805
all_pins[6]	6776783	1			T2	1		T3	10126		T4	1805
all_pins[7]	6776783	1			T2	1		T3	10126		T4	1805

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	54013088	1			T2	8		T3	81008		T4	14440
values[0x1]	201176	1			T31	26		T20	2194		T57	24
transitions[0x0=>0x1]	198903	1			T31	24		T20	1897		T57	19
transitions[0x1=>0x0]	198912	1			T31	24		T20	1897		T57	20

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6776064	1			T2	1		T3	10126		T4	1805
all_pins[0]	values[0x1]	719	1			T31	3		T20	530		T57	3
all_pins[0]	transitions[0x0=>0x1]	389	1			T31	3		T20	243		T57	2
all_pins[0]	transitions[0x1=>0x0]	283	1			T31	4		T20	6		T57	2
all_pins[1]	values[0x0]	6776170	1			T2	1		T3	10126		T4	1805
all_pins[1]	values[0x1]	613	1			T31	4		T20	293		T57	3
all_pins[1]	transitions[0x0=>0x1]	566	1			T31	4		T20	293		T57	1
all_pins[1]	transitions[0x1=>0x0]	282	1			T31	3		T20	5		T57	1
all_pins[2]	values[0x0]	6776454	1			T2	1		T3	10126		T4	1805
all_pins[2]	values[0x1]	329	1			T31	3		T20	5		T57	3
all_pins[2]	transitions[0x0=>0x1]	279	1			T31	2		T20	3		T57	3
all_pins[2]	transitions[0x1=>0x0]	135	1			T31	3		T20	2		T144	2
all_pins[3]	values[0x0]	6776598	1			T2	1		T3	10126		T4	1805
all_pins[3]	values[0x1]	185	1			T31	4		T20	4		T144	2
all_pins[3]	transitions[0x0=>0x1]	123	1			T31	3		T20	4		T144	1
all_pins[3]	transitions[0x1=>0x0]	174	1			T31	5		T20	4		T57	7
all_pins[4]	values[0x0]	6776547	1			T2	1		T3	10126		T4	1805
all_pins[4]	values[0x1]	236	1			T31	6		T20	4		T57	7
all_pins[4]	transitions[0x0=>0x1]	184	1			T31	6		T20	3		T57	6
all_pins[4]	transitions[0x1=>0x0]	3061	1			T20	1346		T57	2		T58	1
all_pins[5]	values[0x0]	6773670	1			T2	1		T3	10126		T4	1805
all_pins[5]	values[0x1]	3113	1			T20	1347		T57	3		T58	3
all_pins[5]	transitions[0x0=>0x1]	1483	1			T20	1346		T57	3		T58	2
all_pins[5]	transitions[0x1=>0x0]	194142	1			T31	2		T20	5		T57	2
all_pins[6]	values[0x0]	6581011	1			T2	1		T3	10126		T4	1805
all_pins[6]	values[0x1]	195772	1			T31	2		T20	6		T57	2
all_pins[6]	transitions[0x0=>0x1]	195717	1			T31	2		T20	3		T57	2
all_pins[6]	transitions[0x1=>0x0]	154	1			T31	4		T20	2		T57	3
all_pins[7]	values[0x0]	6776574	1			T2	1		T3	10126		T4	1805
all_pins[7]	values[0x1]	209	1			T31	4		T20	5		T57	3
all_pins[7]	transitions[0x0=>0x1]	162	1			T31	4		T20	2		T57	2
all_pins[7]	transitions[0x1=>0x0]	681	1			T31	3		T20	527		T57	3