Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4691	1			T25	37		T85	10		T29	20
values[1]	3453	1			T5	18		T12	20		T28	40
values[2]	4862	1			T12	40		T75	6		T26	138
values[3]	4364	1			T12	45		T14	8		T25	50
values[4]	4342	1			T2	26		T9	30		T12	43
values[5]	3831	1			T13	12		T12	46		T30	22
values[6]	4226	1			T25	20		T26	48		T28	66
values[7]	5089	1			T26	88		T28	82		T30	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4490	1			T9	30		T26	138		T28	40
values[1]	3957	1			T12	88		T14	8		T26	20
values[2]	3978	1			T12	46		T75	6		T92	16
values[3]	4738	1			T5	18		T25	37		T26	27
values[4]	4441	1			T2	26		T25	70		T85	10
values[5]	4293	1			T26	28		T29	20		T28	77
values[6]	5001	1			T13	12		T12	40		T26	40
values[7]	3960	1			T12	20		T26	105		T28	40

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34292

1

T2

22

T5

18

T9

30

auto[1]

566

1

T2

4

T12

12

T25

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	394	1			T31	20		T244	20		T66	20
auto[0]	values[0]	values[1]	591	1			T30	100		T31	20		T34	22
auto[0]	values[0]	values[2]	476	1			T33	20		T66	27		T223	20
auto[0]	values[0]	values[3]	640	1			T25	37		T28	20		T31	20
auto[0]	values[0]	values[4]	530	1			T85	10		T32	52		T219	4
auto[0]	values[0]	values[5]	783	1			T29	16		T175	24		T66	20
auto[0]	values[0]	values[6]	642	1			T102	8		T145	34		T143	20
auto[0]	values[0]	values[7]	567	1			T28	20		T66	20		T169	34
auto[0]	values[1]	values[0]	454	1			T33	24		T116	28		T170	19
auto[0]	values[1]	values[1]	411	1			T206	16		T240	18		T174	4
auto[0]	values[1]	values[2]	401	1			T28	20		T34	37		T227	14
auto[0]	values[1]	values[3]	672	1			T5	18		T28	20		T143	40
auto[0]	values[1]	values[4]	390	1			T159	20		T161	20		T213	22
auto[0]	values[1]	values[5]	484	1			T161	23		T213	28		T204	21
auto[0]	values[1]	values[6]	394	1			T189	12		T175	20		T215	16
auto[0]	values[1]	values[7]	178	1			T12	20		T163	28		T217	18
auto[0]	values[2]	values[0]	737	1			T26	74		T39	55		T33	20
auto[0]	values[2]	values[1]	588	1			T28	20		T143	20		T119	34
auto[0]	values[2]	values[2]	363	1			T75	6		T28	62		T33	20
auto[0]	values[2]	values[3]	619	1			T33	31		T190	20		T66	44
auto[0]	values[2]	values[4]	465	1			T26	20		T28	39		T173	30
auto[0]	values[2]	values[5]	668	1			T28	33		T31	20		T190	26
auto[0]	values[2]	values[6]	589	1			T12	39		T26	18		T160	20
auto[0]	values[2]	values[7]	764	1			T26	22		T32	20		T146	20
auto[0]	values[3]	values[0]	557	1			T26	42		T28	20		T229	22
auto[0]	values[3]	values[1]	419	1			T12	40		T14	8		T225	6
auto[0]	values[3]	values[2]	482	1			T92	16		T214	10		T33	26
auto[0]	values[3]	values[3]	662	1			T26	25		T31	76		T195	26
auto[0]	values[3]	values[4]	628	1			T25	48		T32	20		T180	24
auto[0]	values[3]	values[5]	449	1			T146	20		T171	6		T245	4
auto[0]	values[3]	values[6]	544	1			T141	20		T66	22		T246	4
auto[0]	values[3]	values[7]	552	1			T26	35		T30	89		T146	20
auto[0]	values[4]	values[0]	461	1			T9	30		T66	23		T191	23
auto[0]	values[4]	values[1]	449	1			T12	40		T28	41		T216	28
auto[0]	values[4]	values[2]	685	1			T28	27		T146	17		T116	20
auto[0]	values[4]	values[3]	701	1			T31	22		T33	45		T146	32
auto[0]	values[4]	values[4]	627	1			T2	22		T28	20		T30	20
auto[0]	values[4]	values[5]	347	1			T175	20		T247	2		T183	45
auto[0]	values[4]	values[6]	475	1			T28	36		T30	86		T31	33
auto[0]	values[4]	values[7]	524	1			T28	18		T194	26		T159	46
auto[0]	values[5]	values[0]	457	1			T31	96		T146	20		T248	12
auto[0]	values[5]	values[1]	439	1			T146	71		T161	20		T249	4
auto[0]	values[5]	values[2]	490	1			T12	43		T146	20		T181	10
auto[0]	values[5]	values[3]	621	1			T30	22		T31	20		T146	30
auto[0]	values[5]	values[4]	457	1			T69	12		T204	26		T135	39
auto[0]	values[5]	values[5]	412	1			T192	50		T161	20		T213	41
auto[0]	values[5]	values[6]	548	1			T13	12		T190	60		T143	20
auto[0]	values[5]	values[7]	330	1			T116	31		T208	24		T191	21
auto[0]	values[6]	values[0]	515	1			T28	20		T31	68		T32	20
auto[0]	values[6]	values[1]	436	1			T250	60		T183	19		T251	22
auto[0]	values[6]	values[2]	441	1			T28	21		T30	21		T252	4
auto[0]	values[6]	values[3]	273	1			T230	4		T253	32		T187	21
auto[0]	values[6]	values[4]	452	1			T25	18		T140	22		T222	8
auto[0]	values[6]	values[5]	484	1			T28	24		T30	39		T31	44
auto[0]	values[6]	values[6]	952	1			T30	19		T31	36		T231	12
auto[0]	values[6]	values[7]	608	1			T26	47		T30	19		T34	23
auto[0]	values[7]	values[0]	859	1			T26	20		T32	29		T33	44
auto[0]	values[7]	values[1]	546	1			T26	20		T234	16		T66	25
auto[0]	values[7]	values[2]	580	1			T30	20		T254	22		T170	166
auto[0]	values[7]	values[3]	463	1			T190	54		T21	22		T191	19
auto[0]	values[7]	values[4]	815	1			T31	20		T34	20		T220	22
auto[0]	values[7]	values[5]	596	1			T26	28		T28	20		T31	20
auto[0]	values[7]	values[6]	778	1			T26	20		T28	62		T31	26
auto[0]	values[7]	values[7]	378	1			T161	21		T135	26		T188	20
auto[1]	values[0]	values[0]	2	1			T135	1		T188	1		-	-
auto[1]	values[0]	values[1]	6	1			T30	1		T161	1		T170	1
auto[1]	values[0]	values[2]	6	1			T165	2		T255	1		T256	3
auto[1]	values[0]	values[3]	12	1			T67	4		T170	1		T257	3
auto[1]	values[0]	values[4]	7	1			T32	1		T258	1		T259	2
auto[1]	values[0]	values[5]	10	1			T29	4		T192	1		T260	4
auto[1]	values[0]	values[6]	9	1			T135	4		T261	1		T207	2
auto[1]	values[0]	values[7]	16	1			T192	3		T170	1		T243	1
auto[1]	values[1]	values[0]	12	1			T33	1		T170	1		T188	1
auto[1]	values[1]	values[1]	14	1			T183	1		T217	4		T262	1
auto[1]	values[1]	values[2]	4	1			T34	2		T40	2		-	-
auto[1]	values[1]	values[3]	8	1			T170	1		T263	1		T258	2
auto[1]	values[1]	values[4]	8	1			T217	3		T264	1		T238	1
auto[1]	values[1]	values[5]	12	1			T161	1		T204	1		T135	2
auto[1]	values[1]	values[6]	1	1			T191	1		-	-		-	-
auto[1]	values[1]	values[7]	10	1			T163	6		T217	2		T265	2
auto[1]	values[2]	values[0]	9	1			T26	2		T179	1		T217	1
auto[1]	values[2]	values[1]	9	1			T119	1		T213	1		T266	1
auto[1]	values[2]	values[2]	9	1			T210	2		T120	2		T267	4
auto[1]	values[2]	values[3]	6	1			T204	2		T268	3		T269	1
auto[1]	values[2]	values[4]	7	1			T21	2		T263	3		T242	1
auto[1]	values[2]	values[5]	7	1			T190	1		T257	1		T81	3
auto[1]	values[2]	values[6]	17	1			T12	1		T26	2		T217	2
auto[1]	values[2]	values[7]	5	1			T183	1		T187	1		T40	1
auto[1]	values[3]	values[0]	5	1			T159	1		T175	1		T217	1
auto[1]	values[3]	values[1]	18	1			T12	5		T175	2		T170	1
auto[1]	values[3]	values[2]	3	1			T116	1		T187	1		T42	1
auto[1]	values[3]	values[3]	15	1			T26	2		T31	1		T161	1
auto[1]	values[3]	values[4]	10	1			T25	2		T270	3		T271	2
auto[1]	values[3]	values[5]	11	1			T161	3		T272	1		T273	1
auto[1]	values[3]	values[6]	3	1			T161	1		T274	1		T275	1
auto[1]	values[3]	values[7]	6	1			T201	1		T188	2		T268	1
auto[1]	values[4]	values[0]	6	1			T201	2		T262	1		T276	1
auto[1]	values[4]	values[1]	9	1			T12	3		T277	2		T49	2
auto[1]	values[4]	values[2]	14	1			T146	3		T160	1		T242	2
auto[1]	values[4]	values[3]	11	1			T146	1		T192	2		T270	1
auto[1]	values[4]	values[4]	10	1			T2	4		T190	1		T179	2
auto[1]	values[4]	values[5]	10	1			T49	2		T165	2		T278	1
auto[1]	values[4]	values[6]	8	1			T31	2		T66	1		T183	1
auto[1]	values[4]	values[7]	5	1			T28	2		T191	2		T262	1
auto[1]	values[5]	values[0]	6	1			T31	2		T165	1		T279	2
auto[1]	values[5]	values[1]	9	1			T280	1		T238	3		T262	3
auto[1]	values[5]	values[2]	11	1			T12	3		T143	1		T281	4
auto[1]	values[5]	values[3]	17	1			T135	1		T165	1		T262	2
auto[1]	values[5]	values[4]	17	1			T204	3		T135	1		T187	1
auto[1]	values[5]	values[5]	2	1			T213	1		T282	1		-	-
auto[1]	values[5]	values[6]	14	1			T190	2		T143	1		T270	1
auto[1]	values[5]	values[7]	1	1			T277	1		-	-		-	-
auto[1]	values[6]	values[0]	6	1			T31	2		T238	1		T283	2
auto[1]	values[6]	values[1]	4	1			T183	1		T284	1		T278	2
auto[1]	values[6]	values[2]	5	1			T28	1		T159	1		T161	2
auto[1]	values[6]	values[3]	6	1			T258	3		T273	2		T285	1
auto[1]	values[6]	values[4]	5	1			T25	2		T66	1		T238	1
auto[1]	values[6]	values[5]	14	1			T30	2		T31	2		T159	2
auto[1]	values[6]	values[6]	16	1			T30	1		T159	1		T66	1
auto[1]	values[6]	values[7]	9	1			T26	1		T30	1		T66	2
auto[1]	values[7]	values[0]	10	1			T33	3		T257	2		T272	2
auto[1]	values[7]	values[1]	9	1			T66	1		T187	2		T40	2
auto[1]	values[7]	values[2]	8	1			T183	3		T188	1		T207	2
auto[1]	values[7]	values[3]	12	1			T21	4		T191	1		T135	3
auto[1]	values[7]	values[4]	13	1			T31	1		T160	5		T223	2
auto[1]	values[7]	values[5]	4	1			T192	1		T40	1		T276	2
auto[1]	values[7]	values[6]	11	1			T183	3		T135	1		T187	1
auto[1]	values[7]	values[7]	7	1			T271	2		T284	1		T283	1