Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2693

1

T7

7

T11

5

T17

5

auto[1]

2718

1

T7

12

T11

11

T17

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2890

1

T11

16

T12

15

T18

17

auto[1]

2521

1

T7

19

T17

14

T18

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4312

1

T7

19

T11

11

T17

14

auto[1]

1099

1

T11

5

T12

6

T18

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1055	1			T7	5		T11	3		T17	3
valid[1]	1074	1			T7	5		T11	4		T17	4
valid[2]	1083	1			T7	2		T11	2		T17	2
valid[3]	1114	1			T7	4		T11	5		T17	1
valid[4]	1085	1			T7	3		T11	2		T17	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	177	1			T11	1		T12	1		T30	1
auto[0]	auto[0]	valid[0]	auto[1]	225	1			T7	1		T17	1		T18	1
auto[0]	auto[0]	valid[1]	auto[0]	181	1			T11	1		T18	1		T30	1
auto[0]	auto[0]	valid[1]	auto[1]	248	1			T7	1		T17	2		T19	3
auto[0]	auto[0]	valid[2]	auto[0]	180	1			T26	1		T28	2		T31	1
auto[0]	auto[0]	valid[2]	auto[1]	252	1			T19	12		T37	6		T83	5
auto[0]	auto[0]	valid[3]	auto[0]	186	1			T11	1		T12	1		T18	1
auto[0]	auto[0]	valid[3]	auto[1]	269	1			T7	3		T17	1		T18	1
auto[0]	auto[0]	valid[4]	auto[0]	161	1			T12	4		T18	2		T27	3
auto[0]	auto[0]	valid[4]	auto[1]	251	1			T7	2		T17	1		T18	1
auto[0]	auto[1]	valid[0]	auto[0]	169	1			T11	1		T12	2		T18	2
auto[0]	auto[1]	valid[0]	auto[1]	271	1			T7	4		T17	2		T18	1
auto[0]	auto[1]	valid[1]	auto[0]	178	1			T11	3		T27	1		T28	1
auto[0]	auto[1]	valid[1]	auto[1]	252	1			T7	4		T17	2		T19	2
auto[0]	auto[1]	valid[2]	auto[0]	182	1			T11	1		T18	2		T27	1
auto[0]	auto[1]	valid[2]	auto[1]	263	1			T7	2		T17	2		T19	4
auto[0]	auto[1]	valid[3]	auto[0]	184	1			T11	3		T12	1		T26	1
auto[0]	auto[1]	valid[3]	auto[1]	250	1			T7	1		T19	5		T83	5
auto[0]	auto[1]	valid[4]	auto[0]	193	1			T18	1		T26	1		T27	3
auto[0]	auto[1]	valid[4]	auto[1]	240	1			T7	1		T17	3		T19	2
auto[1]	auto[0]	valid[0]	auto[0]	115	1			T26	1		T28	1		T31	1
auto[1]	auto[0]	valid[1]	auto[0]	111	1			T12	1		T26	1		T30	1
auto[1]	auto[0]	valid[2]	auto[0]	102	1			T12	1		T27	1		T115	1
auto[1]	auto[0]	valid[3]	auto[0]	111	1			T12	1		T18	3		T26	1
auto[1]	auto[0]	valid[4]	auto[0]	124	1			T11	2		T28	2		T30	1
auto[1]	auto[1]	valid[0]	auto[0]	98	1			T11	1		T12	1		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	104	1			T26	1		T27	1		T20	2
auto[1]	auto[1]	valid[2]	auto[0]	104	1			T11	1		T27	1		T28	1
auto[1]	auto[1]	valid[3]	auto[0]	114	1			T11	1		T12	2		T18	3
auto[1]	auto[1]	valid[4]	auto[0]	116	1			T18	1		T26	1		T31	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal