Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72346

1

T3

15

T11

328

T12

362

auto[1]

25130

1

T7

19

T17

196

T18

48

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71182

1

T3

8

T7

19

T11

212

auto[1]

26294

1

T3

7

T11

116

T12

136

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	50304	1			T3	5		T7	19		T11	177
others[1]	8069	1			T11	23		T17	21		T12	28
others[2]	8274	1			T3	3		T11	21		T17	16
others[3]	9386	1			T3	1		T11	35		T17	22
interest[1]	5420	1			T3	1		T11	22		T17	10
interest[4]	33019	1			T3	2		T7	19		T11	114
interest[64]	16023	1			T3	5		T11	50		T17	23

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	23632	1			T3	3		T11	130		T12	119
auto[0]	auto[0]	others[1]	3848	1			T11	11		T12	21		T18	24
auto[0]	auto[0]	others[2]	3890	1			T11	12		T12	12		T18	21
auto[0]	auto[0]	others[3]	4491	1			T3	1		T11	18		T12	15
auto[0]	auto[0]	interest[1]	2557	1			T3	1		T11	11		T12	12
auto[0]	auto[0]	interest[4]	15405	1			T3	1		T11	85		T12	75
auto[0]	auto[0]	interest[64]	7634	1			T3	3		T11	30		T12	47
auto[0]	auto[1]	others[0]	13174	1			T7	19		T17	104		T18	18
auto[0]	auto[1]	others[1]	2044	1			T17	21		T18	4		T19	38
auto[0]	auto[1]	others[2]	2163	1			T17	16		T18	6		T19	41
auto[0]	auto[1]	others[3]	2359	1			T17	22		T18	8		T19	55
auto[0]	auto[1]	interest[1]	1336	1			T17	10		T18	4		T19	26
auto[0]	auto[1]	interest[4]	8775	1			T7	19		T17	65		T18	11
auto[0]	auto[1]	interest[64]	4054	1			T17	23		T18	8		T19	82
auto[1]	auto[0]	others[0]	13498	1			T3	2		T11	47		T12	58
auto[1]	auto[0]	others[1]	2177	1			T11	12		T12	7		T18	12
auto[1]	auto[0]	others[2]	2221	1			T3	3		T11	9		T12	8
auto[1]	auto[0]	others[3]	2536	1			T11	17		T12	20		T18	17
auto[1]	auto[0]	interest[1]	1527	1			T11	11		T12	11		T18	12
auto[1]	auto[0]	interest[4]	8839	1			T3	1		T11	29		T12	41
auto[1]	auto[0]	interest[64]	4335	1			T3	2		T11	20		T12	32

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal