Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	902	1			T31	14		T20	22		T57	17
all_values[1]	902	1			T31	14		T20	22		T57	17
all_values[2]	902	1			T31	14		T20	22		T57	17
all_values[3]	902	1			T31	14		T20	22		T57	17
all_values[4]	902	1			T31	14		T20	22		T57	17
all_values[5]	902	1			T31	14		T20	22		T57	17
all_values[6]	902	1			T31	14		T20	22		T57	17
all_values[7]	902	1			T31	14		T20	22		T57	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3890

1

T31

64

T20

100

T57

72

auto[1]

3326

1

T31

48

T20

76

T57

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3013

1

T31

49

T20

91

T57

56

auto[1]

4203

1

T31

63

T20

85

T57

80

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4233

1

T31

71

T20

114

T57

75

auto[1]

2983

1

T31

41

T20

62

T57

61

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	202	1			T31	4		T20	5		T57	3
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T31	2		T20	4		T57	3
all_values[0]	auto[0]	auto[1]	auto[0]	169	1			T31	3		T20	5		T57	2
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T31	1		T20	1		T57	1
all_values[0]	auto[1]	auto[0]	auto[1]	200	1			T31	2		T20	5		T57	1
all_values[0]	auto[1]	auto[1]	auto[1]	159	1			T31	2		T20	2		T57	7
all_values[1]	auto[0]	auto[0]	auto[0]	206	1			T31	3		T20	5		T57	5
all_values[1]	auto[0]	auto[0]	auto[1]	109	1			T31	1		T20	2		T57	2
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T31	3		T20	1		T57	1
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T31	1		T20	3		T58	1
all_values[1]	auto[1]	auto[0]	auto[1]	208	1			T31	3		T20	6		T57	5
all_values[1]	auto[1]	auto[1]	auto[1]	167	1			T31	3		T20	5		T57	4
all_values[2]	auto[0]	auto[0]	auto[0]	191	1			T31	3		T20	6		T57	6
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T20	1		T57	1		T143	1
all_values[2]	auto[0]	auto[1]	auto[0]	173	1			T31	6		T20	5		T57	2
all_values[2]	auto[0]	auto[1]	auto[1]	99	1			T31	1		T20	2		T57	2
all_values[2]	auto[1]	auto[0]	auto[1]	179	1			T31	2		T20	4		T57	2
all_values[2]	auto[1]	auto[1]	auto[1]	184	1			T31	2		T20	4		T57	4
all_values[3]	auto[0]	auto[0]	auto[0]	223	1			T31	6		T20	8		T57	4
all_values[3]	auto[0]	auto[0]	auto[1]	95	1			T20	2		T57	2		T58	4
all_values[3]	auto[0]	auto[1]	auto[0]	177	1			T31	2		T20	3		T57	7
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T31	2		T20	1		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	183	1			T31	2		T20	5		T57	1
all_values[3]	auto[1]	auto[1]	auto[1]	149	1			T31	2		T20	3		T57	3
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T20	11		T57	3		T58	1
all_values[4]	auto[0]	auto[0]	auto[1]	98	1			T31	2		T144	1		T143	2
all_values[4]	auto[0]	auto[1]	auto[0]	145	1			T20	6		T144	1		T58	1
all_values[4]	auto[0]	auto[1]	auto[1]	101	1			T31	4		T20	1		T57	3
all_values[4]	auto[1]	auto[0]	auto[1]	206	1			T31	4		T57	7		T144	2
all_values[4]	auto[1]	auto[1]	auto[1]	179	1			T31	4		T20	4		T57	4
all_values[5]	auto[0]	auto[0]	auto[0]	278	1			T31	10		T20	6		T57	1
all_values[5]	auto[0]	auto[1]	auto[0]	233	1			T20	7		T57	8		T58	3
all_values[5]	auto[1]	auto[0]	auto[1]	212	1			T31	4		T20	5		T57	6
all_values[5]	auto[1]	auto[1]	auto[1]	179	1			T20	4		T57	2		T58	3
all_values[6]	auto[0]	auto[0]	auto[0]	202	1			T31	2		T20	7		T57	6
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T31	1		T20	2		T57	1
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T31	3		T57	3		T58	1
all_values[6]	auto[0]	auto[1]	auto[1]	78	1			T31	2		T20	2		T57	1
all_values[6]	auto[1]	auto[0]	auto[1]	213	1			T31	5		T20	7		T57	4
all_values[6]	auto[1]	auto[1]	auto[1]	170	1			T31	1		T20	4		T57	2
all_values[7]	auto[0]	auto[0]	auto[0]	186	1			T31	3		T20	8		T57	2
all_values[7]	auto[0]	auto[0]	auto[1]	63	1			T31	2		T57	1		T144	1
all_values[7]	auto[0]	auto[1]	auto[0]	169	1			T31	1		T20	8		T57	3
all_values[7]	auto[0]	auto[1]	auto[1]	89	1			T31	3		T20	2		T57	2
all_values[7]	auto[1]	auto[0]	auto[1]	206	1			T31	3		T20	1		T57	6
all_values[7]	auto[1]	auto[1]	auto[1]	189	1			T31	2		T20	3		T57	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal