Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17074897	1			T1	25133		T2	325		T3	1
all_values[1]	17074897	1			T1	25133		T2	325		T3	1
all_values[2]	17074897	1			T1	25133		T2	325		T3	1
all_values[3]	17074897	1			T1	25133		T2	325		T3	1
all_values[4]	17074897	1			T1	25133		T2	325		T3	1
all_values[5]	17074897	1			T1	25133		T2	325		T3	1
all_values[6]	17074897	1			T1	25133		T2	325		T3	1
all_values[7]	17074897	1			T1	25133		T2	325		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132301018

1

T1

201064

T2

2600

T3

8

auto[1]

4298158

1

T8

70

T16

27

T17

18415

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136433915

1

T1

200806

T2

2600

T3

8

auto[1]

165261

1

T1

258

T4

5

T5

190

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	16479297	1			T1	24946		T2	325		T3	1
all_values[0]	auto[0]	auto[1]	92761	1			T1	187		T5	129		T8	327
all_values[0]	auto[1]	auto[0]	499338	1			T8	5		T16	1		T17	4585
all_values[0]	auto[1]	auto[1]	3501	1			T8	7		T17	8		T20	6
all_values[1]	auto[0]	auto[0]	16880405	1			T1	25089		T2	325		T3	1
all_values[1]	auto[0]	auto[1]	46042	1			T1	44		T5	51		T8	148
all_values[1]	auto[1]	auto[0]	147402	1			T8	4		T16	1		T17	4
all_values[1]	auto[1]	auto[1]	1048	1			T8	3		T16	1		T17	4
all_values[2]	auto[0]	auto[0]	16581189	1			T1	25106		T2	325		T3	1
all_values[2]	auto[0]	auto[1]	16986	1			T1	27		T5	10		T8	5
all_values[2]	auto[1]	auto[0]	475979	1			T8	11		T16	5		T17	4588
all_values[2]	auto[1]	auto[1]	743	1			T8	6		T16	2		T17	6
all_values[3]	auto[0]	auto[0]	16538250	1			T1	25133		T2	325		T3	1
all_values[3]	auto[0]	auto[1]	366	1			T17	3		T18	2		T20	6
all_values[3]	auto[1]	auto[0]	535874	1			T8	8		T16	4		T17	4587
all_values[3]	auto[1]	auto[1]	407	1			T16	2		T17	9		T20	7
all_values[4]	auto[0]	auto[0]	16301871	1			T1	25133		T2	325		T3	1
all_values[4]	auto[0]	auto[1]	398	1			T8	6		T37	1		T16	4
all_values[4]	auto[1]	auto[0]	772259	1			T8	6		T17	4584		T20	4
all_values[4]	auto[1]	auto[1]	369	1			T8	1		T16	1		T17	12
all_values[5]	auto[0]	auto[0]	16389300	1			T1	25133		T2	325		T3	1
all_values[5]	auto[0]	auto[1]	755	1			T4	5		T8	4		T16	3
all_values[5]	auto[1]	auto[0]	684496	1			T8	6		T16	1		T17	6
all_values[5]	auto[1]	auto[1]	346	1			T8	1		T16	1		T17	3
all_values[6]	auto[0]	auto[0]	16538363	1			T1	25133		T2	325		T3	1
all_values[6]	auto[0]	auto[1]	355	1			T8	5		T16	3		T17	4
all_values[6]	auto[1]	auto[0]	535795	1			T8	1		T16	2		T17	8
all_values[6]	auto[1]	auto[1]	384	1			T8	3		T16	1		T17	1
all_values[7]	auto[0]	auto[0]	16434302	1			T1	25133		T2	325		T3	1
all_values[7]	auto[0]	auto[1]	378	1			T8	7		T16	1		T17	2
all_values[7]	auto[1]	auto[0]	639795	1			T8	5		T16	5		T17	3
all_values[7]	auto[1]	auto[1]	422	1			T8	3		T17	7		T18	1