Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	87203	1			T1	96		T3	12		T5	215
auto[SpiFlashAddrCfg]	18981	1			T1	34		T2	3		T3	6
auto[SpiFlashAddr3b]	23292	1			T1	30		T3	4		T5	61
auto[SpiFlashAddr4b]	19462	1			T1	43		T2	3		T3	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85522

1

T1

123

T2

6

T3

26

auto[1]

63416

1

T1

80

T5

204

T8

244

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81367

1

T1

111

T3

10

T5

176

auto[1]

67571

1

T1

92

T2

6

T3

16

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	98877	1			T1	114		T3	16		T5	230
values[1]	2694	1			T1	9		T2	3		T5	9
values[2]	3679	1			T1	9		T5	8		T8	19
values[3]	3714	1			T1	8		T3	2		T5	13
values[4]	3725	1			T1	14		T3	2		T5	6
values[5]	3747	1			T1	4		T2	3		T5	13
values[6]	3707	1			T1	3		T3	4		T5	10
values[7]	3532	1			T1	5		T5	8		T8	15
values[8]	25263	1			T1	37		T3	2		T5	84

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67721

1

T3

26

T5

381

T10

30

auto[1]

81217

1

T1

203

T2

6

T8

512

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

143518

1

T1

186

T2

6

T3

26

write

5420

1

T1

17

T5

9

T8

19

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

50135

1

T1

75

T2

3

T3

6

valids[0x1]

98803

1

T1

128

T2

3

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	4014	1			T1	5		T3	6		T5	13
internal_process_ops[0x5a]	4117	1			T1	7		T3	2		T5	7
internal_process_ops[0x05]	51683	1			T1	27		T5	111		T8	128
internal_process_ops[0x35]	4061	1			T1	6		T3	6		T5	14
internal_process_ops[0x15]	3956	1			T1	11		T5	13		T8	18
internal_process_ops[0x03]	2712	1			T1	3		T3	2		T5	5
internal_process_ops[0x0b]	2618	1			T1	1		T2	3		T5	11
internal_process_ops[0x3b]	2675	1			T1	1		T3	2		T5	13
internal_process_ops[0x6b]	2715	1			T1	2		T5	8		T8	7
internal_process_ops[0xbb]	2572	1			T1	1		T2	3		T5	10
internal_process_ops[0xeb]	2654	1			T1	1		T3	2		T5	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146351

1

T1

198

T2

6

T3

26

auto[1]

2587

1

T1

5

T5

3

T8

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143657

1

T1

196

T2

6

T3

26

auto[1]

5281

1

T1

7

T5

7

T8

18

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

23044

1

T3

12

T5

88

T10

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

13465

1

T5

122

T27

16

T18

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

4842

1

T3

6

T5

14

T10

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

4099

1

T5

24

T18

12

T20

33

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

5798

1

T3

4

T5

32

T10

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

4900

1

T5

28

T27

6

T18

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

5001

1

T3

4

T5

36

T10

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

4135

1

T5

28

T27

4

T18

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

189

1

T5

2

T28

1

T165

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

117

1

T5

1

T156

1

T166

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

130

1

T5

2

T28

4

T29

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

153

1

T28

1

T31

2

T164

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

171

1

T26

2

T28

2

T140

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

114

1

T5

1

T20

1

T34

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

142

1

T28

1

T29

1

T30

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

142

1

T20

1

T156

1

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

210

1

T5

1

T20

3

T166

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

126

1

T20

1

T31

4

T34

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

126

1

T20

3

T166

1

T29

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

189

1

T29

1

T34

6

T167

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

170

1

T5

1

T20

3

T156

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

139

1

T5

1

T20

2

T28

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

140

1

T28

3

T166

2

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

179

1

T20

3

T166

1

T31

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

29130

1

T1

59

T8

160

T9

180

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

20183

1

T1

33

T8

117

T9

99

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

4371

1

T1

13

T2

3

T8

40

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

4305

1

T1

15

T8

42

T9

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

5870

1

T1

16

T8

42

T9

25

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

5387

1

T1

9

T8

33

T9

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

4710

1

T1

26

T2

3

T8

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

4278

1

T1

15

T8

41

T9

22

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

196

1

T1

1

T8

1

T43

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

226

1

T1

1

T8

3

T9

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

178

1

T1

1

T8

3

T25

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

192

1

T1

1

T8

1

T9

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

224

1

T1

3

T43

3

T59

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

196

1

T9

1

T25

4

T43

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

201

1

T1

3

T9

5

T43

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

174

1

T9

1

T100

2

T92

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

175

1

T1

2

T8

1

T9

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

135

1

T9

1

T43

2

T92

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

210

1

T8

1

T9

4

T43

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

166

1

T1

3

T59

2

T100

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

187

1

T1

2

T8

1

T9

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

181

1

T8

2

T87

3

T168

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

184

1

T8

4

T43

1

T59

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

158

1

T8

2

T59

1

T92

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	9095	1			T5	48		T10	6		T11	14
auto[0]	values[0]	valids[0x1]	33612	1			T3	16		T5	182		T10	4
auto[0]	values[1]	valids[0x1]	1146	1			T5	9		T13	4		T18	4
auto[0]	values[2]	valids[0x0]	1156	1			T5	4		T18	4		T26	4
auto[0]	values[2]	valids[0x1]	709	1			T5	4		T27	8		T20	3
auto[0]	values[3]	valids[0x0]	1221	1			T3	2		T5	11		T10	8
auto[0]	values[3]	valids[0x1]	696	1			T5	2		T20	12		T28	5
auto[0]	values[4]	valids[0x0]	1217	1			T3	2		T5	6		T18	3
auto[0]	values[4]	valids[0x1]	638	1			T18	2		T26	4		T20	1
auto[0]	values[5]	valids[0x0]	1243	1			T5	9		T18	2		T26	2
auto[0]	values[5]	valids[0x1]	756	1			T5	4		T10	6		T18	1
auto[0]	values[6]	valids[0x0]	1154	1			T3	2		T5	6		T27	6
auto[0]	values[6]	valids[0x1]	688	1			T3	2		T5	4		T10	2
auto[0]	values[7]	valids[0x0]	1128	1			T5	4		T18	1		T20	9
auto[0]	values[7]	valids[0x1]	650	1			T5	4		T18	2		T169	4
auto[0]	values[8]	valids[0x0]	8009	1			T5	47		T10	4		T170	2
auto[0]	values[8]	valids[0x1]	4603	1			T3	2		T5	37		T18	10
auto[1]	values[0]	valids[0x0]	11924	1			T1	34		T8	89		T9	53
auto[1]	values[0]	valids[0x1]	44246	1			T1	80		T8	234		T9	264
auto[1]	values[1]	valids[0x1]	1548	1			T1	9		T2	3		T8	8
auto[1]	values[2]	valids[0x0]	1071	1			T1	7		T8	8		T9	3
auto[1]	values[2]	valids[0x1]	743	1			T1	2		T8	11		T25	3
auto[1]	values[3]	valids[0x0]	1044	1			T1	5		T8	11		T9	11
auto[1]	values[3]	valids[0x1]	753	1			T1	3		T8	3		T9	3
auto[1]	values[4]	valids[0x0]	1122	1			T1	7		T8	6		T9	2
auto[1]	values[4]	valids[0x1]	748	1			T1	7		T8	3		T9	1
auto[1]	values[5]	valids[0x0]	1116	1			T1	1		T2	3		T8	7
auto[1]	values[5]	valids[0x1]	632	1			T1	3		T8	8		T9	3
auto[1]	values[6]	valids[0x0]	1136	1			T1	1		T8	9		T9	3
auto[1]	values[6]	valids[0x1]	729	1			T1	2		T8	7		T9	2
auto[1]	values[7]	valids[0x0]	1051	1			T1	2		T8	6		T9	7
auto[1]	values[7]	valids[0x1]	703	1			T1	3		T8	9		T9	7
auto[1]	values[8]	valids[0x0]	7448	1			T1	18		T8	57		T9	15
auto[1]	values[8]	valids[0x1]	5203	1			T1	19		T8	36		T9	26