Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40967

1

T1

67

T2

13

T3

1

auto[1]

52353

1

T1

30

T5

104

T8

126

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34322

1

T1

53

T2

13

T3

1

auto[1]

58998

1

T1

44

T5

138

T8

167

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	15166	1			T1	9		T2	2		T3	1
auto[524288:1048575]	11046	1			T1	4		T2	2		T5	92
auto[1048576:1572863]	9981	1			T1	1		T5	13		T8	80
auto[1572864:2097151]	12062	1			T1	14		T5	27		T8	46
auto[2097152:2621439]	10557	1			T1	21		T2	9		T5	8
auto[2621440:3145727]	11413	1			T1	12		T5	30		T8	8
auto[3145728:3670015]	11824	1			T1	20		T5	7		T8	22
auto[3670016:4194303]	11271	1			T1	16		T5	24		T8	32

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91285

1

T1

97

T2

13

T3

1

auto[1]

2035

1

T5

7

T8

11

T9

17

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74658

1

T1

84

T2

13

T3

1

auto[1]

18662

1

T1

13

T5

46

T8

18

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	3878	1			T1	7		T2	2		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	1582	1			T1	1		T5	3		T8	8
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	2856	1			T1	2		T2	2		T5	21
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	1121	1			T1	2		T5	12		T8	9
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	2684	1			T5	4		T8	20		T9	20
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	1083	1			T5	7		T8	13		T9	8
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	2909	1			T1	7		T5	2		T8	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	1164	1			T1	3		T5	4		T8	8
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	2828	1			T1	8		T2	9		T5	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	1139	1			T1	1		T5	3		T8	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	2651	1			T1	4		T5	8		T8	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	1049	1			T1	2		T5	5		T8	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	2869	1			T1	6		T5	4		T8	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	1080	1			T1	3		T5	2		T8	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	2766	1			T1	5		T5	5		T8	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	1061	1			T1	3		T5	2		T8	5
auto[0]	auto[1]	auto[0:524287]	auto[0]	765	1			T8	1		T9	4		T11	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	389	1			T1	1		T9	1		T43	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	745	1			T5	2		T8	2		T125	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	341	1			T5	1		T8	2		T25	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	663	1			T1	1		T5	2		T8	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	307	1			T8	2		T9	3		T25	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	671	1			T1	1		T5	4		T8	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	343	1			T5	1		T8	2		T20	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	653	1			T5	2		T224	1		T43	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	282	1			T43	2		T59	3		T92	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	728	1			T9	1		T25	3		T125	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	333	1			T9	2		T25	1		T20	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	656	1			T1	2		T8	3		T25	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	337	1			T1	2		T5	1		T25	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	712	1			T1	3		T5	2		T9	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	322	1			T1	3		T9	10		T43	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	640	1			T9	1		T25	1		T26	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	6240	1			T9	23		T25	15		T26	19
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	514	1			T5	4		T8	2		T9	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4486	1			T5	52		T8	2		T9	9
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	483	1			T8	5		T9	3		T25	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3690	1			T8	35		T9	11		T25	131
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	563	1			T1	1		T8	4		T9	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	5088	1			T1	2		T8	21		T9	74
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	502	1			T1	2		T8	2		T43	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3960	1			T1	10		T8	26		T43	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	484	1			T1	2		T5	1		T20	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4819	1			T1	4		T5	16		T20	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	522	1			T1	1		T8	1		T9	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	5080	1			T1	6		T8	11		T9	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	501	1			T1	1		T8	4		T20	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4366	1			T1	1		T8	13		T20	93
auto[1]	auto[1]	auto[0:524287]	auto[0]	154	1			T9	1		T140	1		T29	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	1518	1			T9	1		T140	1		T29	39
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	133	1			T43	2		T59	7		T92	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	850	1			T43	3		T59	22		T92	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	127	1			T9	2		T25	1		T28	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	944	1			T9	18		T25	4		T28	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	122	1			T5	1		T59	1		T92	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1202	1			T5	15		T59	3		T92	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	131	1			T43	4		T59	1		T92	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1062	1			T43	6		T59	1		T92	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	139	1			T25	1		T20	1		T59	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1210	1			T25	23		T20	3		T59	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	127	1			T25	1		T43	2		T28	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1153	1			T25	26		T43	4		T28	11
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	146	1			T5	1		T9	4		T100	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1397	1			T5	14		T9	36		T100	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	31940	1			T1	54		T2	13		T3	1
auto[0]	auto[0]	auto[1]	780	1			T5	1		T8	4		T9	2
auto[0]	auto[1]	auto[0]	8039	1			T1	13		T5	14		T8	18
auto[0]	auto[1]	auto[1]	208	1			T5	1		T25	3		T36	1
auto[1]	auto[0]	auto[0]	41086	1			T1	30		T5	69		T8	119
auto[1]	auto[0]	auto[1]	852	1			T5	4		T8	7		T9	9
auto[1]	auto[1]	auto[0]	10220	1			T5	30		T9	56		T25	56
auto[1]	auto[1]	auto[1]	195	1			T5	1		T9	6		T43	1