Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39921

1

T3

26

T5

177

T10

30

auto[1]

27800

1

T5

204

T27

26

T18

32

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	7998	1			T5	70		T18	20		T20	40
values[1]	8375	1			T5	40		T10	30		T125	30
values[2]	8700	1			T5	20		T13	8		T27	26
values[3]	8637	1			T11	14		T170	2		T18	20
values[4]	9055	1			T3	26		T5	60		T20	60
values[5]	8574	1			T5	118		T18	20		T101	26
values[6]	8611	1			T5	20		T20	49		T28	130
values[7]	7771	1			T5	53		T20	75		T190	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	8102	1			T5	20		T18	20		T20	20
values[1]	9797	1			T3	26		T5	76		T10	30
values[2]	8945	1			T5	87		T169	14		T20	20
values[3]	7905	1			T5	20		T170	2		T20	115
values[4]	8572	1			T5	36		T18	20		T101	26
values[5]	8134	1			T5	40		T13	8		T20	88
values[6]	8065	1			T5	82		T27	26		T125	30
values[7]	8201	1			T5	20		T11	14		T26	52

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	507	1			T216	2		T204	11		T79	15
auto[0]	values[0]	values[1]	642	1			T28	13		T193	13		T203	10
auto[0]	values[0]	values[2]	540	1			T5	13		T156	13		T140	15
auto[0]	values[0]	values[3]	561	1			T20	17		T225	20		T140	13
auto[0]	values[0]	values[4]	663	1			T5	31		T18	12		T31	12
auto[0]	values[0]	values[5]	668	1			T30	16		T226	8		T193	11
auto[0]	values[0]	values[6]	505	1			T127	14		T34	15		T204	14
auto[0]	values[0]	values[7]	439	1			T20	14		T35	11		T227	6
auto[0]	values[1]	values[0]	542	1			T5	10		T18	10		T228	2
auto[0]	values[1]	values[1]	849	1			T5	9		T10	30		T28	13
auto[0]	values[1]	values[2]	549	1			T229	18		T31	9		T34	23
auto[0]	values[1]	values[3]	631	1			T20	13		T156	16		T230	14
auto[0]	values[1]	values[4]	614	1			T29	10		T141	14		T159	15
auto[0]	values[1]	values[5]	596	1			T199	14		T28	8		T195	11
auto[0]	values[1]	values[6]	618	1			T125	30		T85	20		T30	13
auto[0]	values[1]	values[7]	601	1			T31	12		T231	14		T193	16
auto[0]	values[2]	values[0]	564	1			T20	7		T28	7		T188	10
auto[0]	values[2]	values[1]	857	1			T20	17		T224	14		T28	12
auto[0]	values[2]	values[2]	508	1			T29	9		T30	13		T210	10
auto[0]	values[2]	values[3]	605	1			T5	15		T28	41		T33	25
auto[0]	values[2]	values[4]	490	1			T34	10		T232	14		T195	10
auto[0]	values[2]	values[5]	697	1			T13	8		T156	16		T233	8
auto[0]	values[2]	values[6]	542	1			T165	26		T31	8		T33	13
auto[0]	values[2]	values[7]	731	1			T28	29		T234	14		T235	2
auto[0]	values[3]	values[0]	419	1			T156	12		T29	13		T193	14
auto[0]	values[3]	values[1]	701	1			T18	14		T200	22		T140	14
auto[0]	values[3]	values[2]	766	1			T169	14		T31	7		T33	10
auto[0]	values[3]	values[3]	517	1			T170	2		T20	13		T30	6
auto[0]	values[3]	values[4]	639	1			T29	9		T35	35		T187	40
auto[0]	values[3]	values[5]	801	1			T20	24		T166	9		T30	17
auto[0]	values[3]	values[6]	634	1			T33	7		T210	13		T158	20
auto[0]	values[3]	values[7]	586	1			T11	14		T164	16		T217	6
auto[0]	values[4]	values[0]	752	1			T166	10		T34	8		T219	16
auto[0]	values[4]	values[1]	577	1			T3	26		T34	25		T193	17
auto[0]	values[4]	values[2]	731	1			T20	8		T30	12		T35	11
auto[0]	values[4]	values[3]	606	1			T34	13		T195	24		T215	26
auto[0]	values[4]	values[4]	602	1			T31	20		T34	9		T203	18
auto[0]	values[4]	values[5]	664	1			T5	15		T20	12		T41	44
auto[0]	values[4]	values[6]	562	1			T5	10		T28	10		T195	8
auto[0]	values[4]	values[7]	1041	1			T5	10		T20	12		T28	25
auto[0]	values[5]	values[0]	401	1			T34	19		T236	10		T196	21
auto[0]	values[5]	values[1]	501	1			T5	14		T195	9		T237	2
auto[0]	values[5]	values[2]	605	1			T238	4		T210	10		T204	10
auto[0]	values[5]	values[3]	344	1			T239	12		T34	12		T210	7
auto[0]	values[5]	values[4]	800	1			T101	26		T29	105		T30	14
auto[0]	values[5]	values[5]	741	1			T5	9		T20	13		T29	9
auto[0]	values[5]	values[6]	601	1			T5	17		T18	12		T20	17
auto[0]	values[5]	values[7]	806	1			T26	52		T20	8		T111	10
auto[0]	values[6]	values[0]	725	1			T166	8		T140	17		T29	7
auto[0]	values[6]	values[1]	908	1			T5	13		T240	22		T29	13
auto[0]	values[6]	values[2]	660	1			T28	12		T241	14		T242	16
auto[0]	values[6]	values[3]	665	1			T28	38		T184	10		T34	89
auto[0]	values[6]	values[4]	845	1			T28	28		T166	12		T34	70
auto[0]	values[6]	values[5]	413	1			T166	8		T29	48		T212	11
auto[0]	values[6]	values[6]	636	1			T28	11		T166	18		T34	10
auto[0]	values[6]	values[7]	445	1			T20	8		T223	28		T195	49
auto[0]	values[7]	values[0]	784	1			T28	91		T243	6		T34	41
auto[0]	values[7]	values[1]	625	1			T29	10		T34	33		T141	3
auto[0]	values[7]	values[2]	680	1			T5	11		T244	10		T34	35
auto[0]	values[7]	values[3]	649	1			T20	51		T190	26		T29	11
auto[0]	values[7]	values[4]	531	1			T30	10		T245	18		T202	11
auto[0]	values[7]	values[5]	561	1			T20	11		T140	12		T34	9
auto[0]	values[7]	values[6]	358	1			T29	18		T246	9		T202	10
auto[0]	values[7]	values[7]	520	1			T31	10		T184	10		T34	20
auto[1]	values[0]	values[0]	330	1			T204	55		T79	7		T202	12
auto[1]	values[0]	values[1]	700	1			T28	13		T193	10		T203	30
auto[1]	values[0]	values[2]	506	1			T5	21		T156	23		T140	8
auto[1]	values[0]	values[3]	316	1			T20	3		T140	8		T184	12
auto[1]	values[0]	values[4]	470	1			T5	5		T18	8		T31	8
auto[1]	values[0]	values[5]	397	1			T30	7		T205	14		T193	17
auto[1]	values[0]	values[6]	426	1			T34	9		T204	6		T246	12
auto[1]	values[0]	values[7]	328	1			T20	6		T35	9		T247	10
auto[1]	values[1]	values[0]	381	1			T5	10		T18	10		T193	34
auto[1]	values[1]	values[1]	547	1			T5	11		T28	9		T31	17
auto[1]	values[1]	values[2]	414	1			T31	14		T34	65		T248	11
auto[1]	values[1]	values[3]	510	1			T20	7		T156	7		T202	16
auto[1]	values[1]	values[4]	444	1			T29	14		T141	6		T249	16
auto[1]	values[1]	values[5]	369	1			T28	12		T195	9		T159	25
auto[1]	values[1]	values[6]	353	1			T30	7		T31	5		T207	10
auto[1]	values[1]	values[7]	357	1			T31	9		T193	4		T160	29
auto[1]	values[2]	values[0]	405	1			T20	13		T28	13		T29	10
auto[1]	values[2]	values[1]	472	1			T20	3		T28	8		T191	30
auto[1]	values[2]	values[2]	753	1			T29	73		T30	15		T210	10
auto[1]	values[2]	values[3]	428	1			T5	5		T28	16		T33	19
auto[1]	values[2]	values[4]	360	1			T34	10		T195	10		T157	11
auto[1]	values[2]	values[5]	258	1			T156	4		T189	4		T79	4
auto[1]	values[2]	values[6]	568	1			T27	26		T31	12		T33	7
auto[1]	values[2]	values[7]	462	1			T28	7		T196	7		T250	10
auto[1]	values[3]	values[0]	382	1			T156	8		T29	16		T193	8
auto[1]	values[3]	values[1]	600	1			T18	6		T140	6		T34	14
auto[1]	values[3]	values[2]	370	1			T31	15		T33	10		T34	15
auto[1]	values[3]	values[3]	422	1			T20	7		T30	21		T33	11
auto[1]	values[3]	values[4]	331	1			T29	39		T35	12		T160	4
auto[1]	values[3]	values[5]	608	1			T20	4		T166	20		T30	10
auto[1]	values[3]	values[6]	423	1			T33	13		T210	7		T158	5
auto[1]	values[3]	values[7]	438	1			T164	7		T33	23		T193	13
auto[1]	values[4]	values[0]	608	1			T166	10		T34	12		T206	10
auto[1]	values[4]	values[1]	436	1			T34	3		T193	5		T251	9
auto[1]	values[4]	values[2]	363	1			T20	12		T30	8		T35	9
auto[1]	values[4]	values[3]	498	1			T34	38		T195	82		T193	11
auto[1]	values[4]	values[4]	417	1			T31	5		T34	11		T203	4
auto[1]	values[4]	values[5]	330	1			T5	5		T20	8		T166	7
auto[1]	values[4]	values[6]	563	1			T5	10		T28	10		T185	24
auto[1]	values[4]	values[7]	305	1			T5	10		T20	8		T28	5
auto[1]	values[5]	values[0]	425	1			T34	29		T252	6		T196	5
auto[1]	values[5]	values[1]	433	1			T5	22		T195	28		T206	24
auto[1]	values[5]	values[2]	446	1			T210	10		T204	10		T246	13
auto[1]	values[5]	values[3]	202	1			T34	8		T210	13		T253	14
auto[1]	values[5]	values[4]	635	1			T29	6		T30	10		T141	7
auto[1]	values[5]	values[5]	454	1			T5	11		T20	7		T29	58
auto[1]	values[5]	values[6]	583	1			T5	45		T18	8		T20	10
auto[1]	values[5]	values[7]	597	1			T20	72		T28	11		T156	5
auto[1]	values[6]	values[0]	495	1			T166	12		T140	7		T29	13
auto[1]	values[6]	values[1]	420	1			T5	7		T29	36		T157	14
auto[1]	values[6]	values[2]	469	1			T28	8		T193	6		T206	6
auto[1]	values[6]	values[3]	509	1			T28	12		T184	10		T34	26
auto[1]	values[6]	values[4]	442	1			T28	12		T166	21		T34	15
auto[1]	values[6]	values[5]	277	1			T166	12		T29	10		T212	9
auto[1]	values[6]	values[6]	392	1			T28	9		T166	8		T34	16
auto[1]	values[6]	values[7]	310	1			T20	41		T195	3		T160	8
auto[1]	values[7]	values[0]	382	1			T28	9		T34	19		T218	30
auto[1]	values[7]	values[1]	529	1			T29	10		T34	4		T141	18
auto[1]	values[7]	values[2]	585	1			T5	42		T32	24		T34	4
auto[1]	values[7]	values[3]	442	1			T20	4		T29	9		T34	39
auto[1]	values[7]	values[4]	289	1			T30	10		T202	35		T251	11
auto[1]	values[7]	values[5]	300	1			T20	9		T140	8		T34	20
auto[1]	values[7]	values[6]	301	1			T29	22		T246	30		T202	19
auto[1]	values[7]	values[7]	235	1			T31	13		T184	12		T34	9