Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34637

1

T3

13

T5

177

T10

15

auto[1]

114301

1

T1

203

T2

6

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	3333	1			T1	4		T3	2		T5	9
auto[4:7]	59657	1			T1	40		T5	133		T8	151
auto[8:11]	3191	1			T1	2		T2	3		T5	11
auto[12:15]	814	1			T1	4		T5	2		T8	1
auto[16:19]	769	1			T3	2		T8	5		T10	8
auto[20:23]	4589	1			T1	11		T5	13		T8	25
auto[24:27]	769	1			T1	2		T5	1		T8	2
auto[28:31]	866	1			T1	3		T5	2		T8	7
auto[32:35]	866	1			T1	1		T5	4		T8	10
auto[36:39]	844	1			T1	3		T5	6		T8	7
auto[40:43]	802	1			T1	4		T5	1		T8	3
auto[44:47]	885	1			T1	4		T5	2		T8	3
auto[48:51]	839	1			T5	1		T8	2		T9	1
auto[52:55]	4662	1			T1	6		T3	6		T5	16
auto[56:59]	3325	1			T1	1		T3	2		T5	13
auto[60:63]	823	1			T5	2		T25	5		T20	3
auto[64:67]	780	1			T1	4		T5	6		T8	1
auto[68:71]	788	1			T5	4		T8	2		T9	3
auto[72:75]	789	1			T1	3		T5	10		T8	3
auto[76:79]	880	1			T1	1		T5	1		T8	4
auto[80:83]	857	1			T1	2		T5	2		T8	4
auto[84:87]	910	1			T1	1		T5	6		T8	4
auto[88:91]	4700	1			T1	9		T3	2		T5	9
auto[92:95]	831	1			T1	1		T5	2		T8	2
auto[96:99]	762	1			T5	5		T8	6		T9	3
auto[100:103]	778	1			T5	4		T8	3		T25	2
auto[104:107]	3318	1			T1	2		T5	9		T8	8
auto[108:111]	882	1			T1	3		T8	1		T9	1
auto[112:115]	857	1			T1	4		T5	1		T8	4
auto[116:119]	830	1			T1	2		T5	3		T8	1
auto[120:123]	801	1			T8	1		T17	2		T20	1
auto[124:127]	808	1			T1	7		T5	4		T8	2
auto[128:131]	855	1			T1	2		T5	1		T8	4
auto[132:135]	846	1			T1	2		T8	6		T10	2
auto[136:139]	881	1			T1	2		T5	2		T8	6
auto[140:143]	877	1			T1	3		T5	1		T8	3
auto[144:147]	840	1			T1	2		T8	8		T9	2
auto[148:151]	794	1			T5	2		T8	2		T9	2
auto[152:155]	811	1			T1	1		T5	1		T8	7
auto[156:159]	4612	1			T1	6		T3	6		T5	16
auto[160:163]	745	1			T5	4		T20	2		T43	6
auto[164:167]	811	1			T1	1		T8	2		T25	1
auto[168:171]	796	1			T1	7		T8	4		T20	1
auto[172:175]	842	1			T9	1		T10	4		T25	4
auto[176:179]	818	1			T8	3		T9	3		T25	2
auto[180:183]	4493	1			T1	10		T5	10		T8	16
auto[184:187]	3143	1			T1	1		T2	3		T5	11
auto[188:191]	819	1			T1	4		T5	2		T8	4
auto[192:195]	810	1			T1	1		T3	2		T25	2
auto[196:199]	771	1			T1	4		T5	3		T8	6
auto[200:203]	794	1			T1	2		T8	3		T9	1
auto[204:207]	851	1			T1	3		T5	3		T8	3
auto[208:211]	835	1			T1	2		T5	1		T8	3
auto[212:215]	847	1			T1	3		T5	4		T8	3
auto[216:219]	840	1			T1	5		T5	1		T8	2
auto[220:223]	821	1			T1	2		T5	1		T8	6
auto[224:227]	871	1			T1	1		T8	6		T9	5
auto[228:231]	816	1			T3	2		T5	4		T8	7
auto[232:235]	6929	1			T1	8		T3	2		T5	21
auto[236:239]	830	1			T5	3		T8	3		T9	6
auto[240:243]	788	1			T1	2		T5	3		T8	2
auto[244:247]	841	1			T1	1		T5	2		T8	3
auto[248:251]	822	1			T5	2		T8	1		T9	4
auto[252:255]	884	1			T1	4		T5	1		T8	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	1101	1			T3	1		T5	4		T10	1
auto[0:3]	auto[1]	2232	1			T1	4		T3	1		T5	5
auto[4:7]	auto[0]	13179	1			T5	65		T11	7		T13	2
auto[4:7]	auto[1]	46478	1			T1	40		T5	68		T8	151
auto[8:11]	auto[0]	1061	1			T5	6		T18	2		T20	12
auto[8:11]	auto[1]	2130	1			T1	2		T2	3		T5	5
auto[12:15]	auto[0]	184	1			T5	1		T169	2		T28	2
auto[12:15]	auto[1]	630	1			T1	4		T5	1		T8	1
auto[16:19]	auto[0]	159	1			T3	1		T10	4		T166	2
auto[16:19]	auto[1]	610	1			T3	1		T8	5		T10	4
auto[20:23]	auto[0]	1038	1			T5	4		T27	1		T18	2
auto[20:23]	auto[1]	3551	1			T1	11		T5	9		T8	25
auto[24:27]	auto[0]	175	1			T5	1		T20	5		T28	4
auto[24:27]	auto[1]	594	1			T1	2		T8	2		T9	1
auto[28:31]	auto[0]	183	1			T28	4		T140	3		T29	2
auto[28:31]	auto[1]	683	1			T1	3		T5	2		T8	7
auto[32:35]	auto[0]	188	1			T5	4		T20	2		T28	2
auto[32:35]	auto[1]	678	1			T1	1		T8	10		T9	2
auto[36:39]	auto[0]	175	1			T5	3		T20	2		T28	3
auto[36:39]	auto[1]	669	1			T1	3		T5	3		T8	7
auto[40:43]	auto[0]	167	1			T10	1		T20	2		T166	2
auto[40:43]	auto[1]	635	1			T1	4		T5	1		T8	3
auto[44:47]	auto[0]	162	1			T156	1		T166	2		T240	1
auto[44:47]	auto[1]	723	1			T1	4		T5	2		T8	3
auto[48:51]	auto[0]	184	1			T5	1		T20	4		T41	1
auto[48:51]	auto[1]	655	1			T8	2		T9	1		T20	2
auto[52:55]	auto[0]	1091	1			T3	3		T5	6		T10	2
auto[52:55]	auto[1]	3571	1			T1	6		T3	3		T5	10
auto[56:59]	auto[0]	1022	1			T3	1		T5	7		T18	2
auto[56:59]	auto[1]	2303	1			T1	1		T3	1		T5	6
auto[60:63]	auto[0]	180	1			T5	2		T20	3		T32	1
auto[60:63]	auto[1]	643	1			T25	5		T43	2		T59	6
auto[64:67]	auto[0]	139	1			T5	3		T20	3		T28	4
auto[64:67]	auto[1]	641	1			T1	4		T5	3		T8	1
auto[68:71]	auto[0]	166	1			T20	1		T166	2		T29	1
auto[68:71]	auto[1]	622	1			T5	4		T8	2		T9	3
auto[72:75]	auto[0]	185	1			T5	2		T20	4		T28	2
auto[72:75]	auto[1]	604	1			T1	3		T5	8		T8	3
auto[76:79]	auto[0]	196	1			T5	1		T28	3		T29	1
auto[76:79]	auto[1]	684	1			T1	1		T8	4		T9	4
auto[80:83]	auto[0]	192	1			T27	1		T18	3		T20	4
auto[80:83]	auto[1]	665	1			T1	2		T5	2		T8	4
auto[84:87]	auto[0]	211	1			T5	3		T27	3		T18	1
auto[84:87]	auto[1]	699	1			T1	1		T5	3		T8	4
auto[88:91]	auto[0]	1054	1			T3	1		T5	2		T13	2
auto[88:91]	auto[1]	3646	1			T1	9		T3	1		T5	7
auto[92:95]	auto[0]	181	1			T5	2		T166	4		T29	1
auto[92:95]	auto[1]	650	1			T1	1		T8	2		T9	2
auto[96:99]	auto[0]	174	1			T5	4		T34	7		T158	1
auto[96:99]	auto[1]	588	1			T5	1		T8	6		T9	3
auto[100:103]	auto[0]	161	1			T18	3		T20	3		T28	3
auto[100:103]	auto[1]	617	1			T5	4		T8	3		T25	2
auto[104:107]	auto[0]	1026	1			T5	3		T18	1		T26	1
auto[104:107]	auto[1]	2292	1			T1	2		T5	6		T8	8
auto[108:111]	auto[0]	187	1			T26	1		T28	1		T166	1
auto[108:111]	auto[1]	695	1			T1	3		T8	1		T9	1
auto[112:115]	auto[0]	186	1			T20	1		T28	1		T230	2
auto[112:115]	auto[1]	671	1			T1	4		T5	1		T8	4
auto[116:119]	auto[0]	172	1			T27	4		T20	1		T28	4
auto[116:119]	auto[1]	658	1			T1	2		T5	3		T8	1
auto[120:123]	auto[0]	156	1			T20	1		T28	3		T29	1
auto[120:123]	auto[1]	645	1			T8	1		T17	2		T43	4
auto[124:127]	auto[0]	172	1			T5	4		T20	3		T28	2
auto[124:127]	auto[1]	636	1			T1	7		T8	2		T9	1
auto[128:131]	auto[0]	147	1			T20	4		T31	1		T195	1
auto[128:131]	auto[1]	708	1			T1	2		T5	1		T8	4
auto[132:135]	auto[0]	187	1			T10	1		T20	1		T28	3
auto[132:135]	auto[1]	659	1			T1	2		T8	6		T10	1
auto[136:139]	auto[0]	210	1			T5	2		T18	4		T20	2
auto[136:139]	auto[1]	671	1			T1	2		T8	6		T9	3
auto[140:143]	auto[0]	176	1			T18	2		T156	1		T166	2
auto[140:143]	auto[1]	701	1			T1	3		T5	1		T8	3
auto[144:147]	auto[0]	172	1			T28	1		T29	2		T164	1
auto[144:147]	auto[1]	668	1			T1	2		T8	8		T9	2
auto[148:151]	auto[0]	135	1			T20	1		T156	1		T230	1
auto[148:151]	auto[1]	659	1			T5	2		T8	2		T9	2
auto[152:155]	auto[0]	154	1			T5	1		T18	4		T20	1
auto[152:155]	auto[1]	657	1			T1	1		T8	7		T25	2
auto[156:159]	auto[0]	1014	1			T3	3		T5	3		T101	1
auto[156:159]	auto[1]	3598	1			T1	6		T3	3		T5	13
auto[160:163]	auto[0]	157	1			T5	1		T20	1		T28	2
auto[160:163]	auto[1]	588	1			T5	3		T20	1		T43	6
auto[164:167]	auto[0]	160	1			T26	2		T28	2		T166	2
auto[164:167]	auto[1]	651	1			T1	1		T8	2		T25	1
auto[168:171]	auto[0]	184	1			T28	2		T156	1		T31	1
auto[168:171]	auto[1]	612	1			T1	7		T8	4		T20	1
auto[172:175]	auto[0]	191	1			T10	2		T18	2		T26	2
auto[172:175]	auto[1]	651	1			T9	1		T10	2		T25	4
auto[176:179]	auto[0]	173	1			T20	2		T28	1		T166	3
auto[176:179]	auto[1]	645	1			T8	3		T9	3		T25	2
auto[180:183]	auto[0]	1003	1			T5	3		T10	1		T125	8
auto[180:183]	auto[1]	3490	1			T1	10		T5	7		T8	16
auto[184:187]	auto[0]	1007	1			T5	4		T170	1		T18	1
auto[184:187]	auto[1]	2136	1			T1	1		T2	3		T5	7
auto[188:191]	auto[0]	169	1			T28	1		T165	1		T156	2
auto[188:191]	auto[1]	650	1			T1	4		T5	2		T8	4
auto[192:195]	auto[0]	189	1			T3	1		T20	1		T28	3
auto[192:195]	auto[1]	621	1			T1	1		T3	1		T25	2
auto[196:199]	auto[0]	165	1			T5	3		T20	3		T28	1
auto[196:199]	auto[1]	606	1			T1	4		T8	6		T9	2
auto[200:203]	auto[0]	189	1			T28	2		T140	4		T29	1
auto[200:203]	auto[1]	605	1			T1	2		T8	3		T9	1
auto[204:207]	auto[0]	197	1			T20	5		T28	4		T140	1
auto[204:207]	auto[1]	654	1			T1	3		T5	3		T8	3
auto[208:211]	auto[0]	187	1			T5	1		T18	2		T156	2
auto[208:211]	auto[1]	648	1			T1	2		T8	3		T9	1
auto[212:215]	auto[0]	194	1			T5	4		T140	2		T29	1
auto[212:215]	auto[1]	653	1			T1	3		T8	3		T18	2
auto[216:219]	auto[0]	181	1			T5	1		T26	1		T41	1
auto[216:219]	auto[1]	659	1			T1	5		T8	2		T25	1
auto[220:223]	auto[0]	167	1			T5	1		T20	2		T28	2
auto[220:223]	auto[1]	654	1			T1	2		T8	6		T9	5
auto[224:227]	auto[0]	185	1			T20	3		T28	4		T166	2
auto[224:227]	auto[1]	686	1			T1	1		T8	6		T9	5
auto[228:231]	auto[0]	180	1			T3	1		T5	3		T28	2
auto[228:231]	auto[1]	636	1			T3	1		T5	1		T8	7
auto[232:235]	auto[0]	1878	1			T3	1		T5	16		T10	3
auto[232:235]	auto[1]	5051	1			T1	8		T3	1		T5	5
auto[236:239]	auto[0]	180	1			T5	1		T20	3		T28	2
auto[236:239]	auto[1]	650	1			T5	2		T8	3		T9	6
auto[240:243]	auto[0]	148	1			T5	2		T18	2		T20	3
auto[240:243]	auto[1]	640	1			T1	2		T5	1		T8	2
auto[244:247]	auto[0]	161	1			T5	2		T27	1		T29	4
auto[244:247]	auto[1]	680	1			T1	1		T8	3		T9	2
auto[248:251]	auto[0]	208	1			T5	1		T20	1		T190	2
auto[248:251]	auto[1]	614	1			T5	1		T8	1		T9	4
auto[252:255]	auto[0]	182	1			T20	1		T28	1		T140	2
auto[252:255]	auto[1]	702	1			T1	4		T5	1		T8	1