Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	870	1			T5	5		T20	1		T28	7
auto[ReadAddrCrossIntoMailbox]	671	1			T5	1		T20	9		T28	4
auto[ReadAddrCrossOutOfMailbox]	742	1			T5	5		T20	8		T28	10
auto[ReadAddrCrossAllMailbox]	436	1			T5	4		T20	4		T28	5
auto[ReadAddrOutsideMailbox]	8122	1			T3	6		T5	42		T10	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5486

1

T3

3

T5

27

T10

2

auto[1]

5355

1

T3

3

T5

30

T10

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1865	1			T3	2		T5	5		T10	2
read_ops[0x0b]	1763	1			T5	11		T18	3		T20	20
read_ops[0x3b]	1808	1			T3	2		T5	13		T18	3
read_ops[0x6b]	1803	1			T5	8		T18	3		T26	2
read_ops[0xbb]	1731	1			T5	10		T170	2		T18	1
read_ops[0xeb]	1871	1			T3	2		T5	10		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	78	1			T28	1		T212	2		T217	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	71	1			T5	1		T29	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	52	1			T195	2		T254	1		T157	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	46	1			T34	1		T254	1		T160	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	77	1			T28	1		T212	1		T33	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	70	1			T5	1		T20	2		T28	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	48	1			T30	1		T157	1		T160	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	35	1			T20	1		T34	1		T213	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	705	1			T3	1		T10	1		T18	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	683	1			T3	1		T5	3		T10	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	76	1			T5	1		T20	1		T166	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	71	1			T28	2		T140	1		T29	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	66	1			T5	1		T29	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	53	1			T20	1		T166	1		T29	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	50	1			T20	1		T28	1		T156	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	61	1			T5	1		T28	2		T29	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	32	1			T33	2		T254	1		T210	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T34	1		T254	1		T255	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	705	1			T5	4		T18	2		T20	8
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	623	1			T5	4		T18	1		T20	9
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	72	1			T5	2		T28	2		T166	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	64	1			T29	1		T31	1		T34	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	55	1			T166	1		T33	1		T34	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	59	1			T20	1		T29	1		T184	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	62	1			T5	1		T20	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	57	1			T20	1		T29	1		T33	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	34	1			T5	1		T33	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	47	1			T5	1		T184	1		T195	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	648	1			T3	1		T5	3		T18	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	710	1			T3	1		T5	5		T18	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	67	1			T188	1		T166	1		T256	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	83	1			T188	1		T156	1		T140	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	69	1			T20	2		T28	1		T31	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	65	1			T20	1		T28	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	67	1			T20	2		T28	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	50	1			T157	1		T210	1		T141	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	33	1			T20	1		T184	1		T206	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	32	1			T5	1		T140	3		T31	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	656	1			T5	3		T18	1		T26	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	681	1			T5	4		T18	2		T26	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	65	1			T28	1		T166	1		T29	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	62	1			T5	1		T28	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	46	1			T28	2		T29	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	53	1			T20	2		T140	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	67	1			T5	1		T28	1		T166	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	50	1			T20	1		T28	1		T34	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T5	1		T28	1		T29	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	42	1			T20	1		T28	2		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	690	1			T5	1		T170	1		T18	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	628	1			T5	6		T170	1		T169	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	83	1			T217	1		T34	2		T210	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	78	1			T166	1		T217	1		T184	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	51	1			T20	1		T166	1		T33	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	56	1			T20	1		T184	1		T195	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	66	1			T5	1		T29	2		T33	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	65	1			T29	1		T34	1		T159	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	47	1			T20	1		T28	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	32	1			T28	1		T210	1		T227	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	691	1			T3	1		T5	7		T10	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	702	1			T3	1		T5	2		T10	1