Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17074897	1			T1	25133		T2	325		T3	1
all_pins[1]	17074897	1			T1	25133		T2	325		T3	1
all_pins[2]	17074897	1			T1	25133		T2	325		T3	1
all_pins[3]	17074897	1			T1	25133		T2	325		T3	1
all_pins[4]	17074897	1			T1	25133		T2	325		T3	1
all_pins[5]	17074897	1			T1	25133		T2	325		T3	1
all_pins[6]	17074897	1			T1	25133		T2	325		T3	1
all_pins[7]	17074897	1			T1	25133		T2	325		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	136045258	1			T1	201064		T2	2600		T3	8
values[0x1]	553918	1			T8	24		T16	8		T17	50
transitions[0x0=>0x1]	547942	1			T8	17		T16	6		T17	35
transitions[0x1=>0x0]	547972	1			T8	17		T16	6		T17	36

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17071227	1			T1	25133		T2	325		T3	1
all_pins[0]	values[0x1]	3670	1			T8	7		T17	8		T20	6
all_pins[0]	transitions[0x0=>0x1]	3052	1			T8	6		T17	6		T20	6
all_pins[0]	transitions[0x1=>0x0]	467	1			T8	2		T16	1		T17	2
all_pins[1]	values[0x0]	17073812	1			T1	25133		T2	325		T3	1
all_pins[1]	values[0x1]	1085	1			T8	3		T16	1		T17	4
all_pins[1]	transitions[0x0=>0x1]	782	1			T8	1		T16	1		T17	3
all_pins[1]	transitions[0x1=>0x0]	462	1			T8	4		T16	2		T17	5
all_pins[2]	values[0x0]	17074132	1			T1	25133		T2	325		T3	1
all_pins[2]	values[0x1]	765	1			T8	6		T16	2		T17	6
all_pins[2]	transitions[0x0=>0x1]	649	1			T8	6		T17	5		T18	1
all_pins[2]	transitions[0x1=>0x0]	291	1			T17	8		T20	3		T156	2
all_pins[3]	values[0x0]	17074490	1			T1	25133		T2	325		T3	1
all_pins[3]	values[0x1]	407	1			T16	2		T17	9		T20	7
all_pins[3]	transitions[0x0=>0x1]	302	1			T16	2		T17	3		T20	7
all_pins[3]	transitions[0x1=>0x0]	264	1			T8	1		T16	1		T17	6
all_pins[4]	values[0x0]	17074528	1			T1	25133		T2	325		T3	1
all_pins[4]	values[0x1]	369	1			T8	1		T16	1		T17	12
all_pins[4]	transitions[0x0=>0x1]	290	1			T16	1		T17	10		T20	1
all_pins[4]	transitions[0x1=>0x0]	12730	1			T16	1		T17	1		T18	1
all_pins[5]	values[0x0]	17062088	1			T1	25133		T2	325		T3	1
all_pins[5]	values[0x1]	12809	1			T8	1		T16	1		T17	3
all_pins[5]	transitions[0x0=>0x1]	8274	1			T16	1		T17	3		T20	160
all_pins[5]	transitions[0x1=>0x0]	529856	1			T8	2		T16	1		T17	1
all_pins[6]	values[0x0]	16540506	1			T1	25133		T2	325		T3	1
all_pins[6]	values[0x1]	534391	1			T8	3		T16	1		T17	1
all_pins[6]	transitions[0x0=>0x1]	534285	1			T8	2		T16	1		T18	2
all_pins[6]	transitions[0x1=>0x0]	316	1			T8	2		T17	6		T18	1
all_pins[7]	values[0x0]	17074475	1			T1	25133		T2	325		T3	1
all_pins[7]	values[0x1]	422	1			T8	3		T17	7		T18	1
all_pins[7]	transitions[0x0=>0x1]	308	1			T8	2		T17	5		T18	1
all_pins[7]	transitions[0x1=>0x0]	3586	1			T8	6		T17	7		T20	5