Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	8410	1			T5	107		T27	26		T169	14
values[1]	9293	1			T5	78		T18	20		T101	26
values[2]	7009	1			T5	20		T13	8		T26	52
values[3]	9062	1			T5	60		T170	2		T20	89
values[4]	9357	1			T3	26		T5	40		T125	30
values[5]	7737	1			T5	40		T11	14		T18	20
values[6]	8500	1			T5	36		T20	75		T224	14
values[7]	8353	1			T10	30		T18	20		T20	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	8888	1			T5	98		T125	30		T20	80
values[1]	9385	1			T5	93		T18	20		T26	52
values[2]	8521	1			T5	20		T18	40		T20	60
values[3]	7723	1			T5	20		T169	14		T20	28
values[4]	8096	1			T3	26		T11	14		T13	8
values[5]	8249	1			T27	26		T170	2		T20	204
values[6]	7650	1			T5	96		T20	20		T28	126
values[7]	9209	1			T5	54		T10	30		T101	26

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66562

1

T3

26

T5

378

T10

30

auto[1]

1159

1

T5

3

T20

8

T28

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	850	1			T20	20		T29	57		T257	2
auto[0]	values[0]	values[1]	1044	1			T5	52		T34	75		T195	20
auto[0]	values[0]	values[2]	992	1			T5	20		T223	28		T34	21
auto[0]	values[0]	values[3]	974	1			T169	14		T166	25		T34	23
auto[0]	values[0]	values[4]	1033	1			T85	20		T29	159		T258	2
auto[0]	values[0]	values[5]	976	1			T27	26		T20	20		T33	20
auto[0]	values[0]	values[6]	912	1			T20	19		T195	20		T159	22
auto[0]	values[0]	values[7]	1475	1			T5	33		T41	44		T28	30
auto[0]	values[1]	values[0]	1386	1			T5	42		T28	79		T34	91
auto[0]	values[1]	values[1]	1616	1			T28	50		T230	14		T31	20
auto[0]	values[1]	values[2]	1093	1			T18	20		T30	22		T193	40
auto[0]	values[1]	values[3]	782	1			T249	16		T259	16		T159	22
auto[0]	values[1]	values[4]	1199	1			T28	20		T34	20		T232	14
auto[0]	values[1]	values[5]	986	1			T20	53		T30	20		T31	20
auto[0]	values[1]	values[6]	923	1			T5	36		T166	29		T34	29
auto[0]	values[1]	values[7]	1133	1			T101	26		T30	19		T33	20
auto[0]	values[2]	values[0]	1084	1			T28	21		T30	24		T31	40
auto[0]	values[2]	values[1]	1084	1			T5	20		T26	52		T200	22
auto[0]	values[2]	values[2]	928	1			T185	24		T167	28		T193	50
auto[0]	values[2]	values[3]	667	1			T31	48		T33	20		T260	6
auto[0]	values[2]	values[4]	618	1			T13	8		T29	20		T261	20
auto[0]	values[2]	values[5]	1144	1			T20	78		T29	49		T210	20
auto[0]	values[2]	values[6]	693	1			T238	4		T189	45		T251	23
auto[0]	values[2]	values[7]	635	1			T190	26		T206	20		T262	14
auto[0]	values[3]	values[0]	1009	1			T20	40		T28	20		T166	20
auto[0]	values[3]	values[1]	1079	1			T28	56		T140	20		T193	20
auto[0]	values[3]	values[2]	1236	1			T188	10		T29	20		T34	22
auto[0]	values[3]	values[3]	1049	1			T5	20		T160	22		T250	20
auto[0]	values[3]	values[4]	1046	1			T234	14		T33	20		T34	20
auto[0]	values[3]	values[5]	1046	1			T170	2		T20	47		T30	26
auto[0]	values[3]	values[6]	1163	1			T5	20		T29	87		T34	72
auto[0]	values[3]	values[7]	1303	1			T5	20		T210	18		T233	8
auto[0]	values[4]	values[0]	1593	1			T5	20		T125	30		T34	15
auto[0]	values[4]	values[1]	1177	1			T18	20		T20	39		T240	22
auto[0]	values[4]	values[2]	1109	1			T199	14		T127	14		T29	20
auto[0]	values[4]	values[3]	987	1			T256	6		T31	25		T34	96
auto[0]	values[4]	values[4]	982	1			T3	26		T164	20		T34	68
auto[0]	values[4]	values[5]	1284	1			T229	18		T33	20		T34	19
auto[0]	values[4]	values[6]	1015	1			T5	20		T28	26		T159	20
auto[0]	values[4]	values[7]	1059	1			T29	28		T35	45		T210	20
auto[0]	values[5]	values[0]	954	1			T263	12		T34	20		T254	14
auto[0]	values[5]	values[1]	1184	1			T5	20		T28	20		T30	20
auto[0]	values[5]	values[2]	720	1			T20	20		T141	18		T236	10
auto[0]	values[5]	values[3]	819	1			T156	36		T140	20		T31	22
auto[0]	values[5]	values[4]	1007	1			T11	14		T18	20		T195	37
auto[0]	values[5]	values[5]	1107	1			T225	20		T164	22		T160	20
auto[0]	values[5]	values[6]	848	1			T5	19		T156	23		T29	48
auto[0]	values[5]	values[7]	972	1			T216	2		T33	41		T184	21
auto[0]	values[6]	values[0]	988	1			T5	36		T156	39		T29	109
auto[0]	values[6]	values[1]	1171	1			T224	14		T32	22		T35	20
auto[0]	values[6]	values[2]	980	1			T20	20		T166	20		T140	24
auto[0]	values[6]	values[3]	1242	1			T20	28		T166	33		T30	25
auto[0]	values[6]	values[4]	1103	1			T20	27		T166	40		T34	20
auto[0]	values[6]	values[5]	834	1			T243	6		T140	20		T33	20
auto[0]	values[6]	values[6]	918	1			T28	99		T239	12		T184	22
auto[0]	values[6]	values[7]	1126	1			T228	2		T140	23		T212	29
auto[0]	values[7]	values[0]	865	1			T20	20		T186	32		T212	20
auto[0]	values[7]	values[1]	884	1			T111	10		T156	20		T34	55
auto[0]	values[7]	values[2]	1325	1			T18	20		T20	20		T156	20
auto[0]	values[7]	values[3]	1077	1			T195	37		T141	20		T189	20
auto[0]	values[7]	values[4]	972	1			T28	56		T34	24		T206	65
auto[0]	values[7]	values[5]	718	1			T28	20		T31	19		T195	20
auto[0]	values[7]	values[6]	1017	1			T165	26		T205	14		T207	10
auto[0]	values[7]	values[7]	1367	1			T10	30		T29	20		T30	28
auto[1]	values[0]	values[0]	18	1			T29	1		T81	3		T264	1
auto[1]	values[0]	values[1]	21	1			T5	1		T34	1		T81	1
auto[1]	values[0]	values[2]	14	1			T196	1		T55	8		T265	1
auto[1]	values[0]	values[3]	18	1			T166	1		T34	1		T266	2
auto[1]	values[0]	values[4]	12	1			T46	1		T267	1		T268	2
auto[1]	values[0]	values[5]	19	1			T34	1		T193	2		T202	3
auto[1]	values[0]	values[6]	31	1			T20	1		T204	2		T269	2
auto[1]	values[0]	values[7]	21	1			T5	1		T166	1		T210	1
auto[1]	values[1]	values[0]	25	1			T28	2		T34	4		T202	2
auto[1]	values[1]	values[1]	30	1			T31	3		T34	1		T56	3
auto[1]	values[1]	values[2]	21	1			T30	1		T160	2		T270	1
auto[1]	values[1]	values[3]	18	1			T202	1		T250	2		T213	9
auto[1]	values[1]	values[4]	24	1			T271	3		T272	8		T265	4
auto[1]	values[1]	values[5]	25	1			T20	2		T31	3		T273	1
auto[1]	values[1]	values[6]	9	1			T195	1		T274	1		T275	1
auto[1]	values[1]	values[7]	23	1			T30	1		T33	1		T193	1
auto[1]	values[2]	values[0]	25	1			T28	1		T31	1		T195	2
auto[1]	values[2]	values[1]	18	1			T246	2		T276	2		T196	3
auto[1]	values[2]	values[2]	24	1			T167	4		T277	1		T278	1
auto[1]	values[2]	values[3]	8	1			T279	4		T251	1		T280	2
auto[1]	values[2]	values[4]	21	1			T261	14		T281	1		T282	1
auto[1]	values[2]	values[5]	24	1			T20	2		T283	2		T284	4
auto[1]	values[2]	values[6]	30	1			T189	3		T251	1		T285	4
auto[1]	values[2]	values[7]	6	1			T203	1		T277	1		T48	2
auto[1]	values[3]	values[0]	18	1			T160	1		T203	3		T250	1
auto[1]	values[3]	values[1]	8	1			T286	1		T46	1		T287	1
auto[1]	values[3]	values[2]	12	1			T34	2		T253	1		T56	1
auto[1]	values[3]	values[3]	9	1			T288	1		T289	1		T290	1
auto[1]	values[3]	values[4]	16	1			T161	2		T288	3		T291	3
auto[1]	values[3]	values[5]	16	1			T20	2		T30	1		T34	2
auto[1]	values[3]	values[6]	20	1			T34	4		T246	3		T202	1
auto[1]	values[3]	values[7]	32	1			T210	2		T79	3		T213	1
auto[1]	values[4]	values[0]	33	1			T34	5		T35	1		T202	1
auto[1]	values[4]	values[1]	21	1			T20	1		T246	1		T292	4
auto[1]	values[4]	values[2]	15	1			T293	3		T294	1		T277	1
auto[1]	values[4]	values[3]	9	1			T34	2		T56	1		T287	1
auto[1]	values[4]	values[4]	18	1			T141	1		T193	3		T79	1
auto[1]	values[4]	values[5]	14	1			T34	1		T160	1		T209	1
auto[1]	values[4]	values[6]	20	1			T204	2		T196	2		T295	2
auto[1]	values[4]	values[7]	21	1			T29	1		T35	2		T210	2
auto[1]	values[5]	values[0]	11	1			T246	1		T296	4		T288	1
auto[1]	values[5]	values[1]	16	1			T193	2		T204	1		T202	1
auto[1]	values[5]	values[2]	18	1			T141	2		T297	1		T298	1
auto[1]	values[5]	values[3]	14	1			T299	1		T297	1		T265	1
auto[1]	values[5]	values[4]	15	1			T300	4		T301	1		T302	1
auto[1]	values[5]	values[5]	18	1			T164	1		T160	2		T202	1
auto[1]	values[5]	values[6]	21	1			T5	1		T33	1		T248	3
auto[1]	values[5]	values[7]	13	1			T33	1		T195	1		T303	4
auto[1]	values[6]	values[0]	14	1			T156	2		T29	2		T193	1
auto[1]	values[6]	values[1]	21	1			T32	2		T206	1		T304	1
auto[1]	values[6]	values[2]	20	1			T196	1		T45	4		T305	2
auto[1]	values[6]	values[3]	25	1			T30	2		T306	4		T206	4
auto[1]	values[6]	values[4]	12	1			T189	1		T281	2		T293	2
auto[1]	values[6]	values[5]	17	1			T196	1		T285	1		T307	2
auto[1]	values[6]	values[6]	16	1			T28	1		T79	2		T250	1
auto[1]	values[6]	values[7]	13	1			T160	8		T271	1		T273	1
auto[1]	values[7]	values[0]	15	1			T206	1		T253	1		T56	1
auto[1]	values[7]	values[1]	11	1			T159	1		T204	1		T196	1
auto[1]	values[7]	values[2]	14	1			T34	1		T308	1		T250	2
auto[1]	values[7]	values[3]	25	1			T161	3		T213	1		T304	2
auto[1]	values[7]	values[4]	18	1			T34	1		T206	2		T79	1
auto[1]	values[7]	values[5]	21	1			T31	1		T202	2		T288	1
auto[1]	values[7]	values[6]	14	1			T81	1		T246	1		T56	2
auto[1]	values[7]	values[7]	10	1			T45	1		T46	3		T309	1