Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5637

1

T1

14

T6

2

T8

14

auto[1]

5476

1

T1

8

T8

15

T15

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6108

1

T1

22

T8

29

T15

14

auto[1]

5005

1

T6

2

T18

3

T38

48

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8773

1

T1

15

T6

2

T8

21

auto[1]

2340

1

T1

7

T8

8

T15

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	2169	1			T1	5		T8	6		T15	6
valid[1]	2281	1			T1	6		T6	1		T8	7
valid[2]	2250	1			T1	6		T8	9		T15	3
valid[3]	2208	1			T1	3		T8	2		T17	6
valid[4]	2205	1			T1	2		T6	1		T8	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	367	1			T1	1		T8	2		T17	3
auto[0]	auto[0]	valid[0]	auto[1]	488	1			T38	6		T93	2		T92	1
auto[0]	auto[0]	valid[1]	auto[0]	390	1			T1	3		T8	6		T15	1
auto[0]	auto[0]	valid[1]	auto[1]	552	1			T6	1		T18	1		T38	7
auto[0]	auto[0]	valid[2]	auto[0]	390	1			T1	1		T15	1		T18	1
auto[0]	auto[0]	valid[2]	auto[1]	509	1			T38	1		T93	1		T43	2
auto[0]	auto[0]	valid[3]	auto[0]	379	1			T1	3		T8	1		T17	2
auto[0]	auto[0]	valid[3]	auto[1]	486	1			T18	1		T38	5		T97	1
auto[0]	auto[0]	valid[4]	auto[0]	384	1			T1	2		T8	2		T15	1
auto[0]	auto[0]	valid[4]	auto[1]	519	1			T6	1		T38	4		T93	4
auto[0]	auto[1]	valid[0]	auto[0]	402	1			T1	2		T8	1		T15	5
auto[0]	auto[1]	valid[0]	auto[1]	465	1			T38	5		T93	3		T92	2
auto[0]	auto[1]	valid[1]	auto[0]	371	1			T1	1		T8	1		T15	2
auto[0]	auto[1]	valid[1]	auto[1]	482	1			T38	6		T93	1		T43	2
auto[0]	auto[1]	valid[2]	auto[0]	381	1			T1	2		T8	7		T15	2
auto[0]	auto[1]	valid[2]	auto[1]	497	1			T38	6		T93	4		T92	1
auto[0]	auto[1]	valid[3]	auto[0]	364	1			T17	2		T40	1		T59	1
auto[0]	auto[1]	valid[3]	auto[1]	516	1			T38	4		T93	2		T92	1
auto[0]	auto[1]	valid[4]	auto[0]	340	1			T8	1		T15	1		T17	2
auto[0]	auto[1]	valid[4]	auto[1]	491	1			T18	1		T38	4		T93	6
auto[1]	auto[0]	valid[0]	auto[0]	236	1			T1	1		T8	1		T17	1
auto[1]	auto[0]	valid[1]	auto[0]	249	1			T1	1		T17	3		T40	1
auto[1]	auto[0]	valid[2]	auto[0]	238	1			T1	2		T8	1		T17	3
auto[1]	auto[0]	valid[3]	auto[0]	224	1			T17	1		T59	1		T92	2
auto[1]	auto[0]	valid[4]	auto[0]	226	1			T8	1		T17	1		T18	2
auto[1]	auto[1]	valid[0]	auto[0]	211	1			T1	1		T8	2		T15	1
auto[1]	auto[1]	valid[1]	auto[0]	237	1			T1	1		T40	1		T92	2
auto[1]	auto[1]	valid[2]	auto[0]	235	1			T1	1		T8	1		T17	2
auto[1]	auto[1]	valid[3]	auto[0]	239	1			T8	1		T17	1		T18	1
auto[1]	auto[1]	valid[4]	auto[0]	245	1			T8	1		T17	1		T18	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal