Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152361

1

T1

535

T4

9

T8

680

auto[1]

54239

1

T6

2

T18

83

T38

592

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

150675

1

T1

355

T4

4

T6

2

auto[1]

55925

1

T1

180

T4

5

T8

228

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	106380	1			T1	303		T4	4		T6	2
others[1]	17294	1			T1	34		T8	53		T15	31
others[2]	17657	1			T1	40		T8	58		T15	37
others[3]	19607	1			T1	49		T4	2		T8	61
interest[1]	11474	1			T1	18		T4	1		T8	41
interest[4]	69667	1			T1	195		T4	4		T6	2
interest[64]	34188	1			T1	91		T4	2		T8	106

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	49503	1			T1	201		T4	3		T8	234
auto[0]	auto[0]	others[1]	8121	1			T1	25		T8	40		T15	24
auto[0]	auto[0]	others[2]	8321	1			T1	27		T8	44		T15	26
auto[0]	auto[0]	others[3]	9221	1			T1	32		T8	34		T15	24
auto[0]	auto[0]	interest[1]	5323	1			T1	12		T4	1		T8	30
auto[0]	auto[0]	interest[4]	32283	1			T1	127		T4	3		T8	163
auto[0]	auto[0]	interest[64]	15947	1			T1	58		T8	70		T15	50
auto[0]	auto[1]	others[0]	28342	1			T6	2		T18	45		T38	293
auto[0]	auto[1]	others[1]	4391	1			T18	5		T38	57		T93	42
auto[0]	auto[1]	others[2]	4482	1			T18	7		T38	53		T93	33
auto[0]	auto[1]	others[3]	5086	1			T18	8		T38	68		T20	2
auto[0]	auto[1]	interest[1]	3073	1			T18	4		T38	22		T93	13
auto[0]	auto[1]	interest[4]	18895	1			T6	2		T18	31		T38	179
auto[0]	auto[1]	interest[64]	8865	1			T18	14		T38	99		T93	79
auto[1]	auto[0]	others[0]	28535	1			T1	102		T4	1		T8	127
auto[1]	auto[0]	others[1]	4782	1			T1	9		T8	13		T15	7
auto[1]	auto[0]	others[2]	4854	1			T1	13		T8	14		T15	11
auto[1]	auto[0]	others[3]	5300	1			T1	17		T4	2		T8	27
auto[1]	auto[0]	interest[1]	3078	1			T1	6		T8	11		T15	9
auto[1]	auto[0]	interest[4]	18489	1			T1	68		T4	1		T8	88
auto[1]	auto[0]	interest[64]	9376	1			T1	33		T4	2		T8	36

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal