Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1628	1			T8	17		T16	7		T17	18
all_values[1]	1628	1			T8	17		T16	7		T17	18
all_values[2]	1628	1			T8	17		T16	7		T17	18
all_values[3]	1628	1			T8	17		T16	7		T17	18
all_values[4]	1628	1			T8	17		T16	7		T17	18
all_values[5]	1628	1			T8	17		T16	7		T17	18
all_values[6]	1628	1			T8	17		T16	7		T17	18
all_values[7]	1628	1			T8	17		T16	7		T17	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6912

1

T8

74

T16

36

T17

79

auto[1]

6112

1

T8

62

T16

20

T17

65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5205

1

T8

61

T16

23

T17

49

auto[1]

7819

1

T8

75

T16

33

T17

95

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7455

1

T8

81

T16

34

T17

80

auto[1]

5569

1

T8

55

T16

22

T17

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	338	1			T8	3		T16	2		T17	2
all_values[0]	auto[0]	auto[0]	auto[1]	158	1			T8	2		T16	2		T17	2
all_values[0]	auto[0]	auto[1]	auto[0]	287	1			T8	3		T17	1		T18	1
all_values[0]	auto[0]	auto[1]	auto[1]	150	1			T8	4		T17	5		T20	2
all_values[0]	auto[1]	auto[0]	auto[1]	386	1			T16	2		T17	7		T18	2
all_values[0]	auto[1]	auto[1]	auto[1]	309	1			T8	5		T16	1		T17	1
all_values[1]	auto[0]	auto[0]	auto[0]	319	1			T8	5		T16	2		T17	6
all_values[1]	auto[0]	auto[0]	auto[1]	187	1			T8	2		T16	1		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	262	1			T8	2		T16	1		T17	2
all_values[1]	auto[0]	auto[1]	auto[1]	154	1			T8	1		T16	1		T17	2
all_values[1]	auto[1]	auto[0]	auto[1]	377	1			T8	3		T16	1		T17	4
all_values[1]	auto[1]	auto[1]	auto[1]	329	1			T8	4		T16	1		T17	4
all_values[2]	auto[0]	auto[0]	auto[0]	325	1			T8	3		T16	1		T17	3
all_values[2]	auto[0]	auto[0]	auto[1]	154	1			T17	2		T18	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	267	1			T8	3		T16	2		T17	2
all_values[2]	auto[0]	auto[1]	auto[1]	164	1			T8	3		T16	1		T17	2
all_values[2]	auto[1]	auto[0]	auto[1]	381	1			T8	3		T16	2		T17	4
all_values[2]	auto[1]	auto[1]	auto[1]	337	1			T8	5		T16	1		T17	5
all_values[3]	auto[0]	auto[0]	auto[0]	326	1			T8	6		T16	3		T17	2
all_values[3]	auto[0]	auto[0]	auto[1]	146	1			T17	1		T18	1		T20	5
all_values[3]	auto[0]	auto[1]	auto[0]	299	1			T8	7		T16	1		T20	4
all_values[3]	auto[0]	auto[1]	auto[1]	165	1			T16	1		T17	3		T20	3
all_values[3]	auto[1]	auto[0]	auto[1]	375	1			T16	1		T17	6		T18	1
all_values[3]	auto[1]	auto[1]	auto[1]	317	1			T8	4		T16	1		T17	6
all_values[4]	auto[0]	auto[0]	auto[0]	331	1			T8	4		T17	2		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	169	1			T8	3		T16	3		T17	1
all_values[4]	auto[0]	auto[1]	auto[0]	286	1			T8	3		T20	1		T164	9
all_values[4]	auto[0]	auto[1]	auto[1]	158	1			T17	7		T20	2		T158	2
all_values[4]	auto[1]	auto[0]	auto[1]	368	1			T8	5		T16	2		T17	3
all_values[4]	auto[1]	auto[1]	auto[1]	316	1			T8	2		T16	2		T17	5
all_values[5]	auto[0]	auto[0]	auto[0]	518	1			T8	9		T16	2		T17	6
all_values[5]	auto[0]	auto[1]	auto[0]	424	1			T8	3		T16	1		T17	5
all_values[5]	auto[1]	auto[0]	auto[1]	356	1			T8	3		T16	3		T17	4
all_values[5]	auto[1]	auto[1]	auto[1]	330	1			T8	2		T16	1		T17	3
all_values[6]	auto[0]	auto[0]	auto[0]	345	1			T8	5		T16	1		T17	6
all_values[6]	auto[0]	auto[0]	auto[1]	152	1			T8	1		T16	2		T17	2
all_values[6]	auto[0]	auto[1]	auto[0]	298	1			T16	2		T17	5		T18	2
all_values[6]	auto[0]	auto[1]	auto[1]	161	1			T18	1		T157	2		T160	1
all_values[6]	auto[1]	auto[0]	auto[1]	358	1			T8	8		T16	1		T17	5
all_values[6]	auto[1]	auto[1]	auto[1]	314	1			T8	3		T16	1		T18	1
all_values[7]	auto[0]	auto[0]	auto[0]	313	1			T8	3		T16	3		T17	5
all_values[7]	auto[0]	auto[0]	auto[1]	163	1			T8	3		T17	1		T18	2
all_values[7]	auto[0]	auto[1]	auto[0]	267	1			T8	2		T16	2		T17	2
all_values[7]	auto[0]	auto[1]	auto[1]	169	1			T8	1		T17	3		T156	1
all_values[7]	auto[1]	auto[0]	auto[1]	367	1			T8	3		T16	2		T17	5
all_values[7]	auto[1]	auto[1]	auto[1]	349	1			T8	5		T17	2		T18	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal