| T1807 |
/workspace/coverage/default/25.spi_device_read_buffer_direct.1679775058 |
|
|
Mar 07 12:42:50 PM PST 24 |
Mar 07 12:42:54 PM PST 24 |
5988448701 ps |
| T1808 |
/workspace/coverage/default/34.spi_device_flash_and_tpm.1468795102 |
|
|
Mar 07 12:43:33 PM PST 24 |
Mar 07 12:43:49 PM PST 24 |
1218113058 ps |
| T1809 |
/workspace/coverage/default/8.spi_device_intercept.2340277943 |
|
|
Mar 07 02:43:21 PM PST 24 |
Mar 07 02:43:33 PM PST 24 |
3119880633 ps |
| T1810 |
/workspace/coverage/default/48.spi_device_flash_mode.1280164371 |
|
|
Mar 07 02:46:55 PM PST 24 |
Mar 07 02:47:19 PM PST 24 |
4561869584 ps |
| T1811 |
/workspace/coverage/default/30.spi_device_upload.255477087 |
|
|
Mar 07 12:43:12 PM PST 24 |
Mar 07 12:43:22 PM PST 24 |
8910686008 ps |
| T1812 |
/workspace/coverage/default/7.spi_device_flash_mode.881974283 |
|
|
Mar 07 12:41:26 PM PST 24 |
Mar 07 12:42:04 PM PST 24 |
28373667988 ps |
| T1813 |
/workspace/coverage/default/30.spi_device_flash_all.886438477 |
|
|
Mar 07 12:43:11 PM PST 24 |
Mar 07 12:43:45 PM PST 24 |
4372540398 ps |
| T1814 |
/workspace/coverage/default/10.spi_device_intercept.3176959043 |
|
|
Mar 07 02:43:36 PM PST 24 |
Mar 07 02:43:41 PM PST 24 |
629113471 ps |
| T1815 |
/workspace/coverage/default/16.spi_device_flash_and_tpm.45791932 |
|
|
Mar 07 12:42:25 PM PST 24 |
Mar 07 12:43:15 PM PST 24 |
23927716377 ps |
| T1816 |
/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4261939837 |
|
|
Mar 07 02:43:18 PM PST 24 |
Mar 07 02:49:40 PM PST 24 |
302691515780 ps |
| T1817 |
/workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.550333952 |
|
|
Mar 07 12:43:09 PM PST 24 |
Mar 07 12:46:29 PM PST 24 |
244638913969 ps |
| T1818 |
/workspace/coverage/default/0.spi_device_tpm_sts_read.1518004959 |
|
|
Mar 07 12:40:47 PM PST 24 |
Mar 07 12:40:48 PM PST 24 |
46687752 ps |
| T1819 |
/workspace/coverage/default/31.spi_device_tpm_sts_read.3093171613 |
|
|
Mar 07 12:43:15 PM PST 24 |
Mar 07 12:43:16 PM PST 24 |
123529116 ps |
| T1820 |
/workspace/coverage/default/8.spi_device_flash_all.1800692924 |
|
|
Mar 07 12:41:39 PM PST 24 |
Mar 07 12:41:57 PM PST 24 |
1744766282 ps |
| T1821 |
/workspace/coverage/default/31.spi_device_alert_test.921688758 |
|
|
Mar 07 02:45:28 PM PST 24 |
Mar 07 02:45:29 PM PST 24 |
13439152 ps |
| T1822 |
/workspace/coverage/default/1.spi_device_tpm_rw.4001187739 |
|
|
Mar 07 12:40:47 PM PST 24 |
Mar 07 12:40:50 PM PST 24 |
237109646 ps |
| T1823 |
/workspace/coverage/default/34.spi_device_tpm_all.1143541260 |
|
|
Mar 07 12:43:15 PM PST 24 |
Mar 07 12:43:42 PM PST 24 |
4938857887 ps |
| T1824 |
/workspace/coverage/default/30.spi_device_tpm_sts_read.4051685749 |
|
|
Mar 07 02:45:25 PM PST 24 |
Mar 07 02:45:25 PM PST 24 |
74593215 ps |
| T1825 |
/workspace/coverage/default/14.spi_device_intercept.2902372789 |
|
|
Mar 07 02:43:58 PM PST 24 |
Mar 07 02:44:01 PM PST 24 |
254095432 ps |
| T1826 |
/workspace/coverage/default/3.spi_device_stress_all.3328279310 |
|
|
Mar 07 12:41:00 PM PST 24 |
Mar 07 12:53:55 PM PST 24 |
864158315063 ps |
| T1827 |
/workspace/coverage/default/22.spi_device_tpm_rw.2996662206 |
|
|
Mar 07 02:44:39 PM PST 24 |
Mar 07 02:44:40 PM PST 24 |
56501953 ps |
| T1828 |
/workspace/coverage/default/33.spi_device_mailbox.2400513799 |
|
|
Mar 07 02:45:35 PM PST 24 |
Mar 07 02:45:55 PM PST 24 |
13730050395 ps |
| T1829 |
/workspace/coverage/default/44.spi_device_cfg_cmd.469768386 |
|
|
Mar 07 12:43:54 PM PST 24 |
Mar 07 12:43:57 PM PST 24 |
626308866 ps |
| T1830 |
/workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2638632304 |
|
|
Mar 07 02:42:58 PM PST 24 |
Mar 07 02:43:10 PM PST 24 |
927038281 ps |
| T1831 |
/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2403181245 |
|
|
Mar 07 02:44:45 PM PST 24 |
Mar 07 02:45:05 PM PST 24 |
5409723192 ps |
| T1832 |
/workspace/coverage/default/12.spi_device_csb_read.367670783 |
|
|
Mar 07 12:41:52 PM PST 24 |
Mar 07 12:41:53 PM PST 24 |
59576640 ps |
| T1833 |
/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2733632807 |
|
|
Mar 07 02:46:32 PM PST 24 |
Mar 07 02:46:39 PM PST 24 |
1930087326 ps |
| T1834 |
/workspace/coverage/default/7.spi_device_flash_all.1870501526 |
|
|
Mar 07 12:41:26 PM PST 24 |
Mar 07 12:42:43 PM PST 24 |
24035651154 ps |
| T1835 |
/workspace/coverage/default/14.spi_device_ram_cfg.3070243882 |
|
|
Mar 07 02:44:00 PM PST 24 |
Mar 07 02:44:00 PM PST 24 |
27452388 ps |
| T1836 |
/workspace/coverage/default/35.spi_device_alert_test.1787492795 |
|
|
Mar 07 12:43:29 PM PST 24 |
Mar 07 12:43:30 PM PST 24 |
14542003 ps |
| T1837 |
/workspace/coverage/default/2.spi_device_intercept.431515104 |
|
|
Mar 07 02:42:54 PM PST 24 |
Mar 07 02:42:58 PM PST 24 |
1970087485 ps |
| T1838 |
/workspace/coverage/default/11.spi_device_intercept.3955829731 |
|
|
Mar 07 12:41:49 PM PST 24 |
Mar 07 12:41:53 PM PST 24 |
1169728670 ps |
| T1839 |
/workspace/coverage/default/29.spi_device_intercept.3907492282 |
|
|
Mar 07 02:45:16 PM PST 24 |
Mar 07 02:45:26 PM PST 24 |
6183160680 ps |
| T1840 |
/workspace/coverage/default/42.spi_device_mailbox.2307765733 |
|
|
Mar 07 12:43:55 PM PST 24 |
Mar 07 12:44:39 PM PST 24 |
11737118370 ps |
| T1841 |
/workspace/coverage/default/13.spi_device_tpm_all.4139914984 |
|
|
Mar 07 02:43:51 PM PST 24 |
Mar 07 02:43:58 PM PST 24 |
6861626979 ps |
| T1842 |
/workspace/coverage/default/17.spi_device_mailbox.2558309909 |
|
|
Mar 07 12:42:21 PM PST 24 |
Mar 07 12:42:28 PM PST 24 |
694090794 ps |
| T1843 |
/workspace/coverage/default/5.spi_device_read_buffer_direct.464603431 |
|
|
Mar 07 02:43:14 PM PST 24 |
Mar 07 02:43:19 PM PST 24 |
654187207 ps |
| T1844 |
/workspace/coverage/default/3.spi_device_tpm_rw.3917630080 |
|
|
Mar 07 12:41:01 PM PST 24 |
Mar 07 12:41:03 PM PST 24 |
67015609 ps |
| T1845 |
/workspace/coverage/default/21.spi_device_tpm_rw.3869380279 |
|
|
Mar 07 12:42:40 PM PST 24 |
Mar 07 12:42:43 PM PST 24 |
234723066 ps |
| T1846 |
/workspace/coverage/default/39.spi_device_intercept.4073778904 |
|
|
Mar 07 02:46:11 PM PST 24 |
Mar 07 02:46:19 PM PST 24 |
1958978200 ps |
| T1847 |
/workspace/coverage/default/7.spi_device_pass_cmd_filtering.3323243535 |
|
|
Mar 07 12:41:24 PM PST 24 |
Mar 07 12:42:00 PM PST 24 |
52188372524 ps |
| T1848 |
/workspace/coverage/default/17.spi_device_ram_cfg.2261919332 |
|
|
Mar 07 12:42:23 PM PST 24 |
Mar 07 12:42:24 PM PST 24 |
18392843 ps |
| T1849 |
/workspace/coverage/default/26.spi_device_pass_cmd_filtering.1198775182 |
|
|
Mar 07 02:45:00 PM PST 24 |
Mar 07 02:45:03 PM PST 24 |
541915896 ps |
| T1850 |
/workspace/coverage/default/16.spi_device_ram_cfg.2193859345 |
|
|
Mar 07 12:42:07 PM PST 24 |
Mar 07 12:42:09 PM PST 24 |
29597005 ps |
| T1851 |
/workspace/coverage/default/14.spi_device_stress_all.2512560540 |
|
|
Mar 07 12:42:09 PM PST 24 |
Mar 07 12:48:04 PM PST 24 |
105953290055 ps |
| T1852 |
/workspace/coverage/default/27.spi_device_tpm_sts_read.2370140024 |
|
|
Mar 07 12:43:01 PM PST 24 |
Mar 07 12:43:02 PM PST 24 |
288774186 ps |
| T1853 |
/workspace/coverage/default/6.spi_device_alert_test.1921448378 |
|
|
Mar 07 12:41:14 PM PST 24 |
Mar 07 12:41:15 PM PST 24 |
42764779 ps |
| T1854 |
/workspace/coverage/default/11.spi_device_pass_cmd_filtering.112624030 |
|
|
Mar 07 12:41:48 PM PST 24 |
Mar 07 12:42:05 PM PST 24 |
2273614309 ps |
| T1855 |
/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.382063429 |
|
|
Mar 07 12:43:29 PM PST 24 |
Mar 07 12:43:45 PM PST 24 |
5268865055 ps |
| T1856 |
/workspace/coverage/default/2.spi_device_mailbox.1307064545 |
|
|
Mar 07 12:41:00 PM PST 24 |
Mar 07 12:41:33 PM PST 24 |
9783266722 ps |
| T1857 |
/workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3943848099 |
|
|
Mar 07 12:43:25 PM PST 24 |
Mar 07 12:43:26 PM PST 24 |
257468434 ps |
| T1858 |
/workspace/coverage/default/36.spi_device_tpm_sts_read.2262667723 |
|
|
Mar 07 02:45:59 PM PST 24 |
Mar 07 02:46:00 PM PST 24 |
115829975 ps |
| T1859 |
/workspace/coverage/default/38.spi_device_mailbox.3727728955 |
|
|
Mar 07 02:46:01 PM PST 24 |
Mar 07 02:46:10 PM PST 24 |
992590493 ps |
| T1860 |
/workspace/coverage/default/44.spi_device_tpm_sts_read.4073088634 |
|
|
Mar 07 12:43:54 PM PST 24 |
Mar 07 12:43:56 PM PST 24 |
93281973 ps |
| T1861 |
/workspace/coverage/default/24.spi_device_flash_and_tpm.2178636821 |
|
|
Mar 07 12:42:46 PM PST 24 |
Mar 07 12:45:28 PM PST 24 |
45037521216 ps |
| T1862 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.938548116 |
|
|
Mar 07 02:42:55 PM PST 24 |
Mar 07 02:43:07 PM PST 24 |
8768462745 ps |
| T1863 |
/workspace/coverage/default/21.spi_device_csb_read.3789827329 |
|
|
Mar 07 12:42:35 PM PST 24 |
Mar 07 12:42:36 PM PST 24 |
16285423 ps |
| T1864 |
/workspace/coverage/default/43.spi_device_flash_and_tpm.2000391848 |
|
|
Mar 07 12:44:03 PM PST 24 |
Mar 07 12:47:50 PM PST 24 |
137877193553 ps |
| T1865 |
/workspace/coverage/default/33.spi_device_alert_test.1158730519 |
|
|
Mar 07 02:45:37 PM PST 24 |
Mar 07 02:45:38 PM PST 24 |
19960123 ps |
| T1866 |
/workspace/coverage/default/25.spi_device_csb_read.1146097729 |
|
|
Mar 07 02:44:50 PM PST 24 |
Mar 07 02:44:51 PM PST 24 |
18584561 ps |
| T1867 |
/workspace/coverage/default/3.spi_device_intercept.685875117 |
|
|
Mar 07 02:43:04 PM PST 24 |
Mar 07 02:43:09 PM PST 24 |
570886945 ps |
| T1868 |
/workspace/coverage/default/13.spi_device_mem_parity.1517925977 |
|
|
Mar 07 02:43:50 PM PST 24 |
Mar 07 02:43:51 PM PST 24 |
36235259 ps |
| T1869 |
/workspace/coverage/default/32.spi_device_intercept.1933905484 |
|
|
Mar 07 12:43:16 PM PST 24 |
Mar 07 12:43:38 PM PST 24 |
32081906946 ps |
| T1870 |
/workspace/coverage/default/31.spi_device_tpm_rw.1165314982 |
|
|
Mar 07 12:43:08 PM PST 24 |
Mar 07 12:43:14 PM PST 24 |
1761951424 ps |
| T1871 |
/workspace/coverage/default/34.spi_device_mailbox.4162378622 |
|
|
Mar 07 12:43:27 PM PST 24 |
Mar 07 12:43:38 PM PST 24 |
1475006163 ps |
| T1872 |
/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1284948493 |
|
|
Mar 07 12:40:59 PM PST 24 |
Mar 07 12:41:40 PM PST 24 |
52036722517 ps |
| T1873 |
/workspace/coverage/default/33.spi_device_flash_and_tpm.3589746510 |
|
|
Mar 07 02:45:35 PM PST 24 |
Mar 07 02:45:50 PM PST 24 |
1256570978 ps |
| T1874 |
/workspace/coverage/default/1.spi_device_tpm_sts_read.257379750 |
|
|
Mar 07 12:40:48 PM PST 24 |
Mar 07 12:40:49 PM PST 24 |
163814843 ps |
| T1875 |
/workspace/coverage/default/11.spi_device_mailbox.53285031 |
|
|
Mar 07 12:41:51 PM PST 24 |
Mar 07 12:42:39 PM PST 24 |
69984948493 ps |
| T1876 |
/workspace/coverage/default/39.spi_device_upload.3901663610 |
|
|
Mar 07 12:43:42 PM PST 24 |
Mar 07 12:43:50 PM PST 24 |
492566544 ps |
| T1877 |
/workspace/coverage/default/37.spi_device_pass_cmd_filtering.2805289803 |
|
|
Mar 07 12:43:28 PM PST 24 |
Mar 07 12:43:31 PM PST 24 |
2096376799 ps |
| T1878 |
/workspace/coverage/default/38.spi_device_csb_read.366774939 |
|
|
Mar 07 02:46:04 PM PST 24 |
Mar 07 02:46:06 PM PST 24 |
156199048 ps |
| T1879 |
/workspace/coverage/default/48.spi_device_tpm_all.836315191 |
|
|
Mar 07 12:44:17 PM PST 24 |
Mar 07 12:44:52 PM PST 24 |
10918881207 ps |
| T1880 |
/workspace/coverage/default/25.spi_device_flash_mode.632985258 |
|
|
Mar 07 02:44:58 PM PST 24 |
Mar 07 02:45:13 PM PST 24 |
1447458657 ps |
| T1881 |
/workspace/coverage/default/47.spi_device_pass_cmd_filtering.3450450106 |
|
|
Mar 07 02:46:46 PM PST 24 |
Mar 07 02:46:52 PM PST 24 |
444644971 ps |
| T1882 |
/workspace/coverage/default/22.spi_device_alert_test.2922584742 |
|
|
Mar 07 02:44:42 PM PST 24 |
Mar 07 02:44:43 PM PST 24 |
15635508 ps |
| T1883 |
/workspace/coverage/default/23.spi_device_flash_all.1857111208 |
|
|
Mar 07 12:42:48 PM PST 24 |
Mar 07 12:46:10 PM PST 24 |
467768362286 ps |
| T1884 |
/workspace/coverage/default/43.spi_device_flash_all.2283218153 |
|
|
Mar 07 12:43:59 PM PST 24 |
Mar 07 12:45:54 PM PST 24 |
29160589254 ps |
| T1885 |
/workspace/coverage/default/23.spi_device_flash_all.3881481978 |
|
|
Mar 07 02:44:42 PM PST 24 |
Mar 07 02:48:10 PM PST 24 |
94786835148 ps |
| T1886 |
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1825349596 |
|
|
Mar 07 02:43:24 PM PST 24 |
Mar 07 02:43:33 PM PST 24 |
4975938590 ps |
| T1887 |
/workspace/coverage/default/33.spi_device_upload.1077724057 |
|
|
Mar 07 02:45:33 PM PST 24 |
Mar 07 02:45:36 PM PST 24 |
309169430 ps |
| T1888 |
/workspace/coverage/default/41.spi_device_flash_and_tpm.1005871990 |
|
|
Mar 07 02:46:21 PM PST 24 |
Mar 07 02:51:16 PM PST 24 |
59183135870 ps |
| T1889 |
/workspace/coverage/default/47.spi_device_tpm_rw.3681857853 |
|
|
Mar 07 02:47:00 PM PST 24 |
Mar 07 02:47:01 PM PST 24 |
45672197 ps |
| T1890 |
/workspace/coverage/default/25.spi_device_intercept.3033059877 |
|
|
Mar 07 12:42:58 PM PST 24 |
Mar 07 12:43:03 PM PST 24 |
565689276 ps |
| T1891 |
/workspace/coverage/default/10.spi_device_read_buffer_direct.2954212457 |
|
|
Mar 07 02:43:34 PM PST 24 |
Mar 07 02:43:38 PM PST 24 |
487215249 ps |
| T1892 |
/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.679867453 |
|
|
Mar 07 02:43:06 PM PST 24 |
Mar 07 02:43:13 PM PST 24 |
482028588 ps |
| T1893 |
/workspace/coverage/default/37.spi_device_upload.1807123683 |
|
|
Mar 07 12:43:32 PM PST 24 |
Mar 07 12:43:42 PM PST 24 |
1333789580 ps |
| T1894 |
/workspace/coverage/default/16.spi_device_tpm_all.19353780 |
|
|
Mar 07 02:44:09 PM PST 24 |
Mar 07 02:45:23 PM PST 24 |
106074504608 ps |
| T1895 |
/workspace/coverage/default/25.spi_device_upload.3148232471 |
|
|
Mar 07 12:42:56 PM PST 24 |
Mar 07 12:43:00 PM PST 24 |
182365701 ps |
| T1896 |
/workspace/coverage/default/41.spi_device_tpm_rw.347389051 |
|
|
Mar 07 02:46:27 PM PST 24 |
Mar 07 02:46:28 PM PST 24 |
30725292 ps |
| T1897 |
/workspace/coverage/default/29.spi_device_flash_and_tpm.1429784793 |
|
|
Mar 07 12:43:10 PM PST 24 |
Mar 07 12:44:02 PM PST 24 |
5794352028 ps |
| T1898 |
/workspace/coverage/default/45.spi_device_intercept.1363228250 |
|
|
Mar 07 12:44:11 PM PST 24 |
Mar 07 12:44:16 PM PST 24 |
3997835002 ps |
| T1899 |
/workspace/coverage/default/5.spi_device_flash_and_tpm.821298029 |
|
|
Mar 07 12:41:16 PM PST 24 |
Mar 07 12:48:59 PM PST 24 |
231368459495 ps |
| T1900 |
/workspace/coverage/default/45.spi_device_flash_mode.1632134063 |
|
|
Mar 07 12:44:04 PM PST 24 |
Mar 07 12:44:24 PM PST 24 |
4413930248 ps |
| T1901 |
/workspace/coverage/default/41.spi_device_tpm_all.2787806902 |
|
|
Mar 07 12:43:47 PM PST 24 |
Mar 07 12:44:36 PM PST 24 |
10854587404 ps |
| T1902 |
/workspace/coverage/default/47.spi_device_tpm_all.3631536177 |
|
|
Mar 07 12:44:04 PM PST 24 |
Mar 07 12:44:21 PM PST 24 |
10437145544 ps |
| T1903 |
/workspace/coverage/default/31.spi_device_read_buffer_direct.3642875015 |
|
|
Mar 07 12:43:10 PM PST 24 |
Mar 07 12:43:14 PM PST 24 |
198725770 ps |
| T1904 |
/workspace/coverage/default/3.spi_device_cfg_cmd.3788195476 |
|
|
Mar 07 02:43:12 PM PST 24 |
Mar 07 02:43:16 PM PST 24 |
1431647580 ps |
| T1905 |
/workspace/coverage/default/36.spi_device_flash_and_tpm.2897484681 |
|
|
Mar 07 12:43:31 PM PST 24 |
Mar 07 12:44:27 PM PST 24 |
15017242335 ps |
| T1906 |
/workspace/coverage/default/49.spi_device_read_buffer_direct.771200518 |
|
|
Mar 07 12:44:19 PM PST 24 |
Mar 07 12:44:26 PM PST 24 |
5569235879 ps |
| T1907 |
/workspace/coverage/default/12.spi_device_flash_all.3370176831 |
|
|
Mar 07 12:41:51 PM PST 24 |
Mar 07 12:44:03 PM PST 24 |
36433110503 ps |
| T1908 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3821943284 |
|
|
Mar 07 12:42:36 PM PST 24 |
Mar 07 12:42:39 PM PST 24 |
611905552 ps |
| T1909 |
/workspace/coverage/default/9.spi_device_mem_parity.797817544 |
|
|
Mar 07 02:43:24 PM PST 24 |
Mar 07 02:43:25 PM PST 24 |
103638133 ps |
| T1910 |
/workspace/coverage/default/29.spi_device_flash_all.2485316656 |
|
|
Mar 07 02:45:16 PM PST 24 |
Mar 07 02:46:34 PM PST 24 |
62932710389 ps |
| T1911 |
/workspace/coverage/default/22.spi_device_mailbox.1184833653 |
|
|
Mar 07 02:44:46 PM PST 24 |
Mar 07 02:44:49 PM PST 24 |
400554506 ps |
| T1912 |
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2961853563 |
|
|
Mar 07 02:43:17 PM PST 24 |
Mar 07 02:43:22 PM PST 24 |
419957424 ps |
| T1913 |
/workspace/coverage/default/28.spi_device_tpm_rw.4227987192 |
|
|
Mar 07 12:42:58 PM PST 24 |
Mar 07 12:43:00 PM PST 24 |
107887396 ps |
| T1914 |
/workspace/coverage/default/28.spi_device_mailbox.2603680295 |
|
|
Mar 07 12:42:58 PM PST 24 |
Mar 07 12:43:30 PM PST 24 |
6904589939 ps |
| T1915 |
/workspace/coverage/default/29.spi_device_tpm_sts_read.3414849287 |
|
|
Mar 07 02:45:17 PM PST 24 |
Mar 07 02:45:18 PM PST 24 |
91641505 ps |
| T1916 |
/workspace/coverage/default/4.spi_device_flash_mode.4063207869 |
|
|
Mar 07 12:41:13 PM PST 24 |
Mar 07 12:41:38 PM PST 24 |
4649386980 ps |
| T1917 |
/workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3403240160 |
|
|
Mar 07 12:42:29 PM PST 24 |
Mar 07 12:47:55 PM PST 24 |
46785285902 ps |
| T1918 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.2051760073 |
|
|
Mar 07 01:08:45 PM PST 24 |
Mar 07 01:08:46 PM PST 24 |
14695346 ps |
| T1919 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2329767580 |
|
|
Mar 07 01:08:33 PM PST 24 |
Mar 07 01:08:35 PM PST 24 |
30087434 ps |
| T1920 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2709376856 |
|
|
Mar 07 01:19:53 PM PST 24 |
Mar 07 01:19:54 PM PST 24 |
25579478 ps |
| T1921 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.665052010 |
|
|
Mar 07 01:08:50 PM PST 24 |
Mar 07 01:08:55 PM PST 24 |
322505161 ps |
| T1922 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.3504201320 |
|
|
Mar 07 01:08:58 PM PST 24 |
Mar 07 01:08:59 PM PST 24 |
16816132 ps |
| T102 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.197803900 |
|
|
Mar 07 01:08:34 PM PST 24 |
Mar 07 01:08:37 PM PST 24 |
200663934 ps |
| T103 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1886752639 |
|
|
Mar 07 01:08:40 PM PST 24 |
Mar 07 01:08:41 PM PST 24 |
35025676 ps |
| T1923 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3481856935 |
|
|
Mar 07 01:08:44 PM PST 24 |
Mar 07 01:08:45 PM PST 24 |
208575623 ps |
| T1924 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1104848339 |
|
|
Mar 07 01:08:35 PM PST 24 |
Mar 07 01:08:38 PM PST 24 |
117541254 ps |
| T1925 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.632268467 |
|
|
Mar 07 01:19:51 PM PST 24 |
Mar 07 01:19:51 PM PST 24 |
30198309 ps |
| T128 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3002133122 |
|
|
Mar 07 01:19:51 PM PST 24 |
Mar 07 01:19:53 PM PST 24 |
19436982 ps |
| T1926 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1280112429 |
|
|
Mar 07 01:08:34 PM PST 24 |
Mar 07 01:08:38 PM PST 24 |
42634793 ps |
| T150 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1432792333 |
|
|
Mar 07 01:19:31 PM PST 24 |
Mar 07 01:19:32 PM PST 24 |
290960916 ps |
| T1927 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3448335857 |
|
|
Mar 07 01:08:45 PM PST 24 |
Mar 07 01:08:46 PM PST 24 |
38493101 ps |
| T1928 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.291644276 |
|
|
Mar 07 01:19:41 PM PST 24 |
Mar 07 01:19:42 PM PST 24 |
26442074 ps |
| T104 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3457734124 |
|
|
Mar 07 01:19:52 PM PST 24 |
Mar 07 01:20:10 PM PST 24 |
302741250 ps |
| T129 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3150473835 |
|
|
Mar 07 01:19:38 PM PST 24 |
Mar 07 01:19:40 PM PST 24 |
27298931 ps |
| T105 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1829514820 |
|
|
Mar 07 01:08:44 PM PST 24 |
Mar 07 01:08:47 PM PST 24 |
45777336 ps |
| T1929 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.663611206 |
|
|
Mar 07 01:08:31 PM PST 24 |
Mar 07 01:08:33 PM PST 24 |
225312527 ps |
| T1930 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.2822946490 |
|
|
Mar 07 01:20:01 PM PST 24 |
Mar 07 01:20:02 PM PST 24 |
27387805 ps |
| T1931 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.1714722622 |
|
|
Mar 07 01:08:53 PM PST 24 |
Mar 07 01:08:54 PM PST 24 |
14630599 ps |
| T1932 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.570604371 |
|
|
Mar 07 01:19:52 PM PST 24 |
Mar 07 01:19:53 PM PST 24 |
15138293 ps |
| T126 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.624341222 |
|
|
Mar 07 01:08:48 PM PST 24 |
Mar 07 01:08:50 PM PST 24 |
54828079 ps |
| T130 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2783016691 |
|
|
Mar 07 01:19:55 PM PST 24 |
Mar 07 01:19:57 PM PST 24 |
247939577 ps |
| T1933 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.574097410 |
|
|
Mar 07 01:20:01 PM PST 24 |
Mar 07 01:20:03 PM PST 24 |
54277063 ps |
| T1934 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.1653023528 |
|
|
Mar 07 01:08:46 PM PST 24 |
Mar 07 01:08:46 PM PST 24 |
59559516 ps |
| T151 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.792020723 |
|
|
Mar 07 01:08:44 PM PST 24 |
Mar 07 01:08:49 PM PST 24 |
196362947 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1679601505 |
|
|
Mar 07 01:19:32 PM PST 24 |
Mar 07 01:19:33 PM PST 24 |
35469549 ps |
| T106 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1853743970 |
|
|
Mar 07 01:19:48 PM PST 24 |
Mar 07 01:19:59 PM PST 24 |
201556506 ps |
| T1935 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2593775837 |
|
|
Mar 07 01:19:53 PM PST 24 |
Mar 07 01:19:54 PM PST 24 |
44139244 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1208113541 |
|
|
Mar 07 01:19:28 PM PST 24 |
Mar 07 01:19:32 PM PST 24 |
136934202 ps |
| T132 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3868975018 |
|
|
Mar 07 01:08:38 PM PST 24 |
Mar 07 01:08:40 PM PST 24 |
31074206 ps |
| T1936 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1209725833 |
|
|
Mar 07 01:19:47 PM PST 24 |
Mar 07 01:19:48 PM PST 24 |
37029217 ps |
| T133 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2432640842 |
|
|
Mar 07 01:08:30 PM PST 24 |
Mar 07 01:08:52 PM PST 24 |
4136631754 ps |
| T134 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1547623949 |
|
|
Mar 07 01:08:30 PM PST 24 |
Mar 07 01:08:32 PM PST 24 |
158670709 ps |
| T108 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2677466074 |
|
|
Mar 07 01:19:52 PM PST 24 |
Mar 07 01:19:54 PM PST 24 |
44247377 ps |
| T109 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.431618526 |
|
|
Mar 07 01:08:47 PM PST 24 |
Mar 07 01:08:50 PM PST 24 |
111487441 ps |
| T1937 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.2274181482 |
|
|
Mar 07 01:19:55 PM PST 24 |
Mar 07 01:19:56 PM PST 24 |
22126092 ps |
| T107 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2699591646 |
|
|
Mar 07 01:08:31 PM PST 24 |
Mar 07 01:08:53 PM PST 24 |
5687467255 ps |
| T152 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1626659491 |
|
|
Mar 07 01:19:51 PM PST 24 |
Mar 07 01:19:55 PM PST 24 |
394112243 ps |
| T88 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3286575794 |
|
|
Mar 07 01:19:27 PM PST 24 |
Mar 07 01:19:28 PM PST 24 |
74077169 ps |
| T1938 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.422449891 |
|
|
Mar 07 01:08:59 PM PST 24 |
Mar 07 01:09:01 PM PST 24 |
77154891 ps |
| T123 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.605691043 |
|
|
Mar 07 01:19:48 PM PST 24 |
Mar 07 01:19:50 PM PST 24 |
410010043 ps |
| T1939 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3426187506 |
|
|
Mar 07 01:20:02 PM PST 24 |
Mar 07 01:20:04 PM PST 24 |
46181183 ps |
| T89 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1011190878 |
|
|
Mar 07 01:08:31 PM PST 24 |
Mar 07 01:08:33 PM PST 24 |
68494253 ps |
| T1940 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.441374821 |
|
|
Mar 07 01:19:51 PM PST 24 |
Mar 07 01:19:55 PM PST 24 |
1206260137 ps |
| T1941 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1564065825 |
|
|
Mar 07 01:08:32 PM PST 24 |
Mar 07 01:08:36 PM PST 24 |
117231490 ps |
| T119 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2036018681 |
|
|
Mar 07 01:19:49 PM PST 24 |
Mar 07 01:20:03 PM PST 24 |
478377596 ps |
| T1942 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2927520163 |
|
|
Mar 07 01:19:52 PM PST 24 |
Mar 07 01:19:53 PM PST 24 |
14894850 ps |
| T153 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2383737664 |
|
|
Mar 07 01:08:39 PM PST 24 |
Mar 07 01:08:40 PM PST 24 |
111122867 ps |
| T1943 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.3439596429 |
|
|
Mar 07 01:08:59 PM PST 24 |
Mar 07 01:09:00 PM PST 24 |
12266006 ps |
| T154 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4272967694 |
|
|
Mar 07 01:08:32 PM PST 24 |
Mar 07 01:08:43 PM PST 24 |
443151113 ps |
| T1944 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.964428255 |
|
|
Mar 07 01:20:04 PM PST 24 |
Mar 07 01:20:04 PM PST 24 |
59637717 ps |
| T1945 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1810606923 |
|
|
Mar 07 01:08:55 PM PST 24 |
Mar 07 01:08:56 PM PST 24 |
21378672 ps |
| T112 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3169428361 |
|
|
Mar 07 01:08:49 PM PST 24 |
Mar 07 01:08:56 PM PST 24 |
296082887 ps |
| T114 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.240382778 |
|
|
Mar 07 01:19:39 PM PST 24 |
Mar 07 01:19:41 PM PST 24 |
55847544 ps |
| T173 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2829940636 |
|
|
Mar 07 01:19:53 PM PST 24 |
Mar 07 01:20:06 PM PST 24 |
398734356 ps |
| T135 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.300887209 |
|
|
Mar 07 01:08:46 PM PST 24 |
Mar 07 01:08:48 PM PST 24 |
243815823 ps |
| T136 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3028167779 |
|
|
Mar 07 01:19:40 PM PST 24 |
Mar 07 01:19:42 PM PST 24 |
94391047 ps |
| T1946 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3541011116 |
|
|
Mar 07 01:08:56 PM PST 24 |
Mar 07 01:08:57 PM PST 24 |
23760063 ps |
| T138 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.149188685 |
|
|
Mar 07 01:19:29 PM PST 24 |
Mar 07 01:19:31 PM PST 24 |
51249850 ps |
| T1947 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3515926334 |
|
|
Mar 07 01:19:38 PM PST 24 |
Mar 07 01:19:41 PM PST 24 |
61970226 ps |
| T1948 |
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.2023132266 |
|
|
Mar 07 01:08:48 PM PST 24 |
Mar 07 01:08:49 PM PST 24 |
19932940 ps |
| T1949 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.2646700989 |
|
|
Mar 07 01:08:36 PM PST 24 |
Mar 07 01:08:37 PM PST 24 |
16696667 ps |
| T155 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2923369938 |
|
|
Mar 07 01:19:46 PM PST 24 |
Mar 07 01:19:49 PM PST 24 |
242868233 ps |
| T137 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3495220519 |
|
|
Mar 07 01:08:45 PM PST 24 |
Mar 07 01:08:47 PM PST 24 |
91158041 ps |
| T1950 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1021912998 |
|
|
Mar 07 01:08:46 PM PST 24 |
Mar 07 01:08:47 PM PST 24 |
67184871 ps |
| T113 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2008192280 |
|
|
Mar 07 01:19:47 PM PST 24 |
Mar 07 01:19:51 PM PST 24 |
44297892 ps |
| T120 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2046199226 |
|
|
Mar 07 01:19:40 PM PST 24 |
Mar 07 01:19:45 PM PST 24 |
889557914 ps |
| T1951 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.250068303 |
|
|
Mar 07 01:08:55 PM PST 24 |
Mar 07 01:08:56 PM PST 24 |
57804302 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.348146012 |
|
|
Mar 07 01:08:31 PM PST 24 |
Mar 07 01:08:32 PM PST 24 |
26731028 ps |
| T1952 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.3054059509 |
|
|
Mar 07 01:08:47 PM PST 24 |
Mar 07 01:08:48 PM PST 24 |
39400081 ps |
| T1953 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3504002621 |
|
|
Mar 07 01:19:51 PM PST 24 |
Mar 07 01:19:55 PM PST 24 |
263842525 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2572910949 |
|
|
Mar 07 01:08:35 PM PST 24 |
Mar 07 01:08:39 PM PST 24 |
97109615 ps |
| T115 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2597787322 |
|
|
Mar 07 01:08:37 PM PST 24 |
Mar 07 01:08:42 PM PST 24 |
334956692 ps |
| T117 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2343312160 |
|
|
Mar 07 01:19:50 PM PST 24 |
Mar 07 01:19:56 PM PST 24 |
706562721 ps |
| T1954 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4034324176 |
|
|
Mar 07 01:08:40 PM PST 24 |
Mar 07 01:08:40 PM PST 24 |
76456097 ps |
| T1955 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2952916746 |
|
|
Mar 07 01:08:35 PM PST 24 |
Mar 07 01:08:38 PM PST 24 |
21375804 ps |
| T1956 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.646955115 |
|
|
Mar 07 01:08:33 PM PST 24 |
Mar 07 01:08:36 PM PST 24 |
63480352 ps |
| T1957 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4091792271 |
|
|
Mar 07 01:08:33 PM PST 24 |
Mar 07 01:08:37 PM PST 24 |
74702687 ps |
| T1958 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.378497426 |
|
|
Mar 07 01:19:32 PM PST 24 |
Mar 07 01:19:34 PM PST 24 |
111991843 ps |
| T163 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1503245719 |
|
|
Mar 07 01:08:37 PM PST 24 |
Mar 07 01:08:39 PM PST 24 |
63606115 ps |
| T121 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.169875303 |
|
|
Mar 07 01:19:29 PM PST 24 |
Mar 07 01:19:33 PM PST 24 |
473341624 ps |
| T1959 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.2390738650 |
|
|
Mar 07 01:19:40 PM PST 24 |
Mar 07 01:19:41 PM PST 24 |
13377343 ps |
| T1960 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.1424889497 |
|
|
Mar 07 01:08:57 PM PST 24 |
Mar 07 01:08:58 PM PST 24 |
62452977 ps |
| T118 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2896251951 |
|
|
Mar 07 01:19:52 PM PST 24 |
Mar 07 01:19:56 PM PST 24 |
274217481 ps |
| T1961 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.223932904 |
|
|
Mar 07 01:08:44 PM PST 24 |
Mar 07 01:08:47 PM PST 24 |
324130039 ps |
| T1962 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3991452106 |
|
|
Mar 07 01:20:02 PM PST 24 |
Mar 07 01:20:03 PM PST 24 |
35672278 ps |
| T1963 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.14953708 |
|
|
Mar 07 01:08:37 PM PST 24 |
Mar 07 01:08:39 PM PST 24 |
116474438 ps |
| T1964 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.2141242316 |
|
|
Mar 07 01:08:48 PM PST 24 |
Mar 07 01:08:48 PM PST 24 |
34354274 ps |
| T1965 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.2177290528 |
|
|
Mar 07 01:19:52 PM PST 24 |
Mar 07 01:19:52 PM PST 24 |
61028525 ps |
| T181 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.146184807 |
|
|
Mar 07 01:08:48 PM PST 24 |
Mar 07 01:09:08 PM PST 24 |
1014186445 ps |
| T1966 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.823227967 |
|
|
Mar 07 01:19:54 PM PST 24 |
Mar 07 01:19:55 PM PST 24 |
12071944 ps |
| T1967 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.28013177 |
|
|
Mar 07 01:19:21 PM PST 24 |
Mar 07 01:19:23 PM PST 24 |
75590946 ps |
| T1968 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2715545960 |
|
|
Mar 07 01:08:48 PM PST 24 |
Mar 07 01:08:50 PM PST 24 |
47867842 ps |
| T1969 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3299867495 |
|
|
Mar 07 01:19:52 PM PST 24 |
Mar 07 01:19:54 PM PST 24 |
324199620 ps |
| T1970 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.852286055 |
|
|
Mar 07 01:08:36 PM PST 24 |
Mar 07 01:08:39 PM PST 24 |
506053947 ps |
| T1971 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1359163132 |
|
|
Mar 07 01:08:47 PM PST 24 |
Mar 07 01:08:48 PM PST 24 |
101386584 ps |
| T175 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3049084626 |
|
|
Mar 07 01:08:38 PM PST 24 |
Mar 07 01:08:50 PM PST 24 |
215883150 ps |
| T1972 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1630775366 |
|
|
Mar 07 01:19:30 PM PST 24 |
Mar 07 01:19:39 PM PST 24 |
2053560304 ps |
| T1973 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1801470459 |
|
|
Mar 07 01:19:29 PM PST 24 |
Mar 07 01:19:31 PM PST 24 |
579922230 ps |
| T1974 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.436310858 |
|
|
Mar 07 01:19:38 PM PST 24 |
Mar 07 01:19:39 PM PST 24 |
86438679 ps |
| T1975 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2963009590 |
|
|
Mar 07 01:08:33 PM PST 24 |
Mar 07 01:08:35 PM PST 24 |
47031601 ps |
| T1976 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3388184439 |
|
|
Mar 07 01:19:38 PM PST 24 |
Mar 07 01:20:02 PM PST 24 |
1275950056 ps |
| T1977 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.734001086 |
|
|
Mar 07 01:19:38 PM PST 24 |
Mar 07 01:19:40 PM PST 24 |
29501492 ps |
| T1978 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.3679715645 |
|
|
Mar 07 01:19:54 PM PST 24 |
Mar 07 01:19:55 PM PST 24 |
48313626 ps |
| T1979 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3778304721 |
|
|
Mar 07 01:08:29 PM PST 24 |
Mar 07 01:08:31 PM PST 24 |
148837875 ps |
| T1980 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.3172350211 |
|
|
Mar 07 01:08:56 PM PST 24 |
Mar 07 01:08:57 PM PST 24 |
50280963 ps |
| T1981 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.3195117464 |
|
|
Mar 07 01:08:47 PM PST 24 |
Mar 07 01:08:48 PM PST 24 |
40191314 ps |
| T1982 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3161513348 |
|
|
Mar 07 01:19:51 PM PST 24 |
Mar 07 01:19:53 PM PST 24 |
240926106 ps |
| T1983 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4151357842 |
|
|
Mar 07 01:08:29 PM PST 24 |
Mar 07 01:08:30 PM PST 24 |
39877107 ps |
| T183 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3490885695 |
|
|
Mar 07 01:19:50 PM PST 24 |
Mar 07 01:19:57 PM PST 24 |
665848910 ps |
| T1984 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3542327354 |
|
|
Mar 07 01:08:30 PM PST 24 |
Mar 07 01:08:31 PM PST 24 |
16548558 ps |
| T1985 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.2046938866 |
|
|
Mar 07 01:19:53 PM PST 24 |
Mar 07 01:19:54 PM PST 24 |
24280199 ps |
| T182 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3339211463 |
|
|
Mar 07 01:19:38 PM PST 24 |
Mar 07 01:19:45 PM PST 24 |
349057486 ps |
| T1986 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2999389856 |
|
|
Mar 07 01:19:53 PM PST 24 |
Mar 07 01:19:57 PM PST 24 |
918748601 ps |
| T1987 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.3209346592 |
|
|
Mar 07 01:19:37 PM PST 24 |
Mar 07 01:19:38 PM PST 24 |
12724788 ps |
| T1988 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3014863055 |
|
|
Mar 07 01:19:40 PM PST 24 |
Mar 07 01:19:43 PM PST 24 |
396635591 ps |
| T1989 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1334038218 |
|
|
Mar 07 01:19:39 PM PST 24 |
Mar 07 01:19:43 PM PST 24 |
503879284 ps |
| T1990 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3049724157 |
|
|
Mar 07 01:19:47 PM PST 24 |
Mar 07 01:19:51 PM PST 24 |
456608290 ps |
| T1991 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1507781174 |
|
|
Mar 07 01:19:55 PM PST 24 |
Mar 07 01:19:56 PM PST 24 |
21714422 ps |
| T1992 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2627819608 |
|
|
Mar 07 01:08:29 PM PST 24 |
Mar 07 01:08:32 PM PST 24 |
74471719 ps |
| T1993 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.2025041815 |
|
|
Mar 07 01:08:32 PM PST 24 |
Mar 07 01:08:33 PM PST 24 |
40834883 ps |
| T1994 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2075401385 |
|
|
Mar 07 01:08:48 PM PST 24 |
Mar 07 01:08:52 PM PST 24 |
133293879 ps |
| T1995 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2400232015 |
|
|
Mar 07 01:08:46 PM PST 24 |
Mar 07 01:08:49 PM PST 24 |
211107613 ps |
| T1996 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.2342390140 |
|
|
Mar 07 01:20:01 PM PST 24 |
Mar 07 01:20:02 PM PST 24 |
15194540 ps |
| T1997 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.955515244 |
|
|
Mar 07 01:08:46 PM PST 24 |
Mar 07 01:08:47 PM PST 24 |
28213067 ps |
| T1998 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.2918351564 |
|
|
Mar 07 01:08:51 PM PST 24 |
Mar 07 01:08:51 PM PST 24 |
13153089 ps |
| T1999 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1627789438 |
|
|
Mar 07 01:08:33 PM PST 24 |
Mar 07 01:08:35 PM PST 24 |
54775205 ps |
| T2000 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.3967075360 |
|
|
Mar 07 01:20:05 PM PST 24 |
Mar 07 01:20:06 PM PST 24 |
132733215 ps |
| T174 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3766987203 |
|
|
Mar 07 01:19:37 PM PST 24 |
Mar 07 01:19:58 PM PST 24 |
1836275243 ps |
| T179 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4192260053 |
|
|
Mar 07 01:19:40 PM PST 24 |
Mar 07 01:20:00 PM PST 24 |
310498397 ps |
| T2001 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4293413856 |
|
|
Mar 07 01:08:32 PM PST 24 |
Mar 07 01:08:35 PM PST 24 |
83403574 ps |
| T2002 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.822538056 |
|
|
Mar 07 01:08:37 PM PST 24 |
Mar 07 01:08:42 PM PST 24 |
812901751 ps |
| T180 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.993476170 |
|
|
Mar 07 01:08:46 PM PST 24 |
Mar 07 01:08:59 PM PST 24 |
3205764735 ps |
| T2003 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1477650193 |
|
|
Mar 07 01:19:54 PM PST 24 |
Mar 07 01:19:58 PM PST 24 |
122516089 ps |
| T2004 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1916061949 |
|
|
Mar 07 01:08:35 PM PST 24 |
Mar 07 01:08:55 PM PST 24 |
1204029816 ps |
| T2005 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.678883138 |
|
|
Mar 07 01:19:47 PM PST 24 |
Mar 07 01:19:51 PM PST 24 |
132501612 ps |
| T2006 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1528617085 |
|
|
Mar 07 01:08:32 PM PST 24 |
Mar 07 01:08:36 PM PST 24 |
77965070 ps |