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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.38 94.44 98.61 89.36 97.08 95.82 98.22


Total test records in report: 2211
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T91 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3921467236 Mar 07 01:19:30 PM PST 24 Mar 07 01:19:31 PM PST 24 18057747 ps
T2007 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1209242964 Mar 07 01:08:34 PM PST 24 Mar 07 01:08:38 PM PST 24 175996645 ps
T2008 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2831199839 Mar 07 01:19:36 PM PST 24 Mar 07 01:19:49 PM PST 24 183534011 ps
T2009 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.908556693 Mar 07 01:08:46 PM PST 24 Mar 07 01:08:47 PM PST 24 51741105 ps
T2010 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.717364968 Mar 07 01:08:47 PM PST 24 Mar 07 01:08:51 PM PST 24 42604395 ps
T2011 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.955978912 Mar 07 01:08:34 PM PST 24 Mar 07 01:08:36 PM PST 24 28923404 ps
T2012 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4248973779 Mar 07 01:19:51 PM PST 24 Mar 07 01:19:54 PM PST 24 71367935 ps
T2013 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2718484697 Mar 07 01:19:40 PM PST 24 Mar 07 01:19:53 PM PST 24 314818180 ps
T2014 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1249938460 Mar 07 01:08:48 PM PST 24 Mar 07 01:08:48 PM PST 24 78290752 ps
T176 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3563021449 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:49 PM PST 24 4322139633 ps
T2015 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.19081703 Mar 07 01:19:51 PM PST 24 Mar 07 01:20:10 PM PST 24 809334208 ps
T2016 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2496899873 Mar 07 01:08:31 PM PST 24 Mar 07 01:08:33 PM PST 24 240460050 ps
T2017 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1531800446 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:54 PM PST 24 45598657 ps
T2018 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4159550558 Mar 07 01:20:04 PM PST 24 Mar 07 01:20:05 PM PST 24 16820223 ps
T2019 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3029456202 Mar 07 01:19:31 PM PST 24 Mar 07 01:19:33 PM PST 24 69472642 ps
T2020 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1537293526 Mar 07 01:19:27 PM PST 24 Mar 07 01:19:35 PM PST 24 2196748547 ps
T2021 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3779548843 Mar 07 01:19:23 PM PST 24 Mar 07 01:19:24 PM PST 24 31080684 ps
T2022 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4201242283 Mar 07 01:20:03 PM PST 24 Mar 07 01:20:04 PM PST 24 68153678 ps
T2023 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.762143188 Mar 07 01:08:45 PM PST 24 Mar 07 01:08:47 PM PST 24 34697067 ps
T2024 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.696226035 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:42 PM PST 24 164891784 ps
T2025 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.15284485 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:57 PM PST 24 166795844 ps
T2026 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1786492702 Mar 07 01:19:50 PM PST 24 Mar 07 01:20:14 PM PST 24 1640809642 ps
T2027 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1393241533 Mar 07 01:08:54 PM PST 24 Mar 07 01:08:56 PM PST 24 21355014 ps
T2028 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.814599570 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:55 PM PST 24 1021849631 ps
T171 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2619685546 Mar 07 01:08:35 PM PST 24 Mar 07 01:08:39 PM PST 24 491004173 ps
T2029 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3035934451 Mar 07 01:08:51 PM PST 24 Mar 07 01:09:00 PM PST 24 2320537480 ps
T2030 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3904645897 Mar 07 01:08:44 PM PST 24 Mar 07 01:08:47 PM PST 24 71648462 ps
T2031 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3539626441 Mar 07 01:20:03 PM PST 24 Mar 07 01:20:04 PM PST 24 14830305 ps
T2032 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1062300738 Mar 07 01:08:59 PM PST 24 Mar 07 01:09:01 PM PST 24 26189509 ps
T2033 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2692096667 Mar 07 01:19:51 PM PST 24 Mar 07 01:19:54 PM PST 24 375648715 ps
T2034 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2618430978 Mar 07 01:08:51 PM PST 24 Mar 07 01:08:53 PM PST 24 42854551 ps
T2035 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1582425497 Mar 07 01:08:44 PM PST 24 Mar 07 01:08:47 PM PST 24 287246521 ps
T2036 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.478373277 Mar 07 01:19:32 PM PST 24 Mar 07 01:19:33 PM PST 24 81571683 ps
T2037 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2365114016 Mar 07 01:08:53 PM PST 24 Mar 07 01:08:54 PM PST 24 15288597 ps
T2038 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.408477873 Mar 07 01:19:51 PM PST 24 Mar 07 01:19:55 PM PST 24 265781299 ps
T2039 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1351700998 Mar 07 01:19:23 PM PST 24 Mar 07 01:19:25 PM PST 24 76958395 ps
T2040 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3509993986 Mar 07 01:19:43 PM PST 24 Mar 07 01:19:46 PM PST 24 147181074 ps
T2041 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.859077991 Mar 07 01:08:43 PM PST 24 Mar 07 01:08:47 PM PST 24 129368326 ps
T2042 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2104530257 Mar 07 01:19:51 PM PST 24 Mar 07 01:19:54 PM PST 24 383006231 ps
T2043 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4234206696 Mar 07 01:08:51 PM PST 24 Mar 07 01:08:55 PM PST 24 929630226 ps
T2044 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2494792835 Mar 07 01:19:30 PM PST 24 Mar 07 01:19:32 PM PST 24 148549523 ps
T2045 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1525626795 Mar 07 01:09:00 PM PST 24 Mar 07 01:09:01 PM PST 24 15123957 ps
T2046 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1174094409 Mar 07 01:19:40 PM PST 24 Mar 07 01:19:44 PM PST 24 618895099 ps
T2047 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3371718769 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:35 PM PST 24 94032958 ps
T2048 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1049416852 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:42 PM PST 24 45320801 ps
T2049 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2012994842 Mar 07 01:19:40 PM PST 24 Mar 07 01:19:41 PM PST 24 120097067 ps
T2050 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2708842544 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:35 PM PST 24 480932783 ps
T2051 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1119373969 Mar 07 01:08:47 PM PST 24 Mar 07 01:08:50 PM PST 24 101971724 ps
T2052 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1116114703 Mar 07 01:08:53 PM PST 24 Mar 07 01:08:54 PM PST 24 35648549 ps
T2053 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2652543235 Mar 07 01:08:35 PM PST 24 Mar 07 01:08:38 PM PST 24 142912616 ps
T2054 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.502354932 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:55 PM PST 24 281460203 ps
T177 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2646047014 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:53 PM PST 24 3892530236 ps
T2055 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3667745889 Mar 07 01:08:48 PM PST 24 Mar 07 01:08:50 PM PST 24 190367188 ps
T2056 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4049453421 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:33 PM PST 24 25511953 ps
T2057 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2638299214 Mar 07 01:08:30 PM PST 24 Mar 07 01:08:33 PM PST 24 201499837 ps
T2058 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1279337549 Mar 07 01:08:45 PM PST 24 Mar 07 01:08:47 PM PST 24 234176820 ps
T2059 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.53719883 Mar 07 01:08:46 PM PST 24 Mar 07 01:08:50 PM PST 24 153776363 ps
T2060 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.317750803 Mar 07 01:08:48 PM PST 24 Mar 07 01:08:51 PM PST 24 67481534 ps
T2061 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1998812498 Mar 07 01:19:38 PM PST 24 Mar 07 01:19:40 PM PST 24 26329606 ps
T2062 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2810527003 Mar 07 01:19:48 PM PST 24 Mar 07 01:19:48 PM PST 24 40375672 ps
T2063 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1810938679 Mar 07 01:08:57 PM PST 24 Mar 07 01:08:58 PM PST 24 19140740 ps
T2064 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1007435827 Mar 07 01:19:32 PM PST 24 Mar 07 01:19:37 PM PST 24 61698358 ps
T2065 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.83920702 Mar 07 01:19:28 PM PST 24 Mar 07 01:19:29 PM PST 24 12657104 ps
T2066 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1245825480 Mar 07 01:19:51 PM PST 24 Mar 07 01:19:54 PM PST 24 370095601 ps
T2067 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3428884710 Mar 07 01:19:42 PM PST 24 Mar 07 01:19:46 PM PST 24 192543946 ps
T2068 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1054796923 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:53 PM PST 24 690307575 ps
T178 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1194256828 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:40 PM PST 24 674249933 ps
T2069 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4100551383 Mar 07 01:19:36 PM PST 24 Mar 07 01:19:39 PM PST 24 175577468 ps
T2070 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1312664339 Mar 07 01:08:29 PM PST 24 Mar 07 01:08:30 PM PST 24 13382771 ps
T2071 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.755115149 Mar 07 01:08:55 PM PST 24 Mar 07 01:08:56 PM PST 24 36866844 ps
T2072 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3948152685 Mar 07 01:19:52 PM PST 24 Mar 07 01:20:12 PM PST 24 1510967513 ps
T2073 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2366198858 Mar 07 01:19:50 PM PST 24 Mar 07 01:19:55 PM PST 24 160941422 ps
T2074 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.106022650 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:39 PM PST 24 1130362219 ps
T2075 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1636148172 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:54 PM PST 24 40883057 ps
T2076 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2375170283 Mar 07 01:19:31 PM PST 24 Mar 07 01:19:32 PM PST 24 37357499 ps
T2077 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2944957239 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:53 PM PST 24 14068593 ps
T2078 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1785120640 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:34 PM PST 24 24563470 ps
T2079 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3685787922 Mar 07 01:19:48 PM PST 24 Mar 07 01:19:49 PM PST 24 12744047 ps
T2080 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2805537842 Mar 07 01:19:41 PM PST 24 Mar 07 01:19:45 PM PST 24 171610626 ps
T2081 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.619925957 Mar 07 01:08:34 PM PST 24 Mar 07 01:08:35 PM PST 24 55636130 ps
T2082 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2454675585 Mar 07 01:19:38 PM PST 24 Mar 07 01:19:39 PM PST 24 14154001 ps
T2083 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1096497054 Mar 07 01:19:31 PM PST 24 Mar 07 01:19:32 PM PST 24 19813513 ps
T2084 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.935644864 Mar 07 01:08:29 PM PST 24 Mar 07 01:08:42 PM PST 24 191846408 ps
T2085 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1531291883 Mar 07 01:19:29 PM PST 24 Mar 07 01:19:31 PM PST 24 157262444 ps
T2086 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2815220971 Mar 07 01:08:34 PM PST 24 Mar 07 01:08:37 PM PST 24 38887952 ps
T2087 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3895834410 Mar 07 01:19:32 PM PST 24 Mar 07 01:19:49 PM PST 24 672672457 ps
T2088 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1314872009 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:53 PM PST 24 105497648 ps
T2089 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3943637424 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:35 PM PST 24 356752929 ps
T2090 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2125055687 Mar 07 01:19:33 PM PST 24 Mar 07 01:19:51 PM PST 24 276381590 ps
T2091 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.577515194 Mar 07 01:08:31 PM PST 24 Mar 07 01:08:32 PM PST 24 13026665 ps
T2092 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4285541004 Mar 07 01:20:03 PM PST 24 Mar 07 01:20:05 PM PST 24 129813371 ps
T2093 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2476398244 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:54 PM PST 24 235553022 ps
T2094 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.113630307 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:40 PM PST 24 467672235 ps
T2095 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2051841884 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:54 PM PST 24 50179886 ps
T2096 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4091808081 Mar 07 01:08:56 PM PST 24 Mar 07 01:08:57 PM PST 24 24746856 ps
T2097 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2118501066 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:53 PM PST 24 22217124 ps
T2098 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1965516475 Mar 07 01:19:32 PM PST 24 Mar 07 01:19:32 PM PST 24 33736946 ps
T2099 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2525981277 Mar 07 01:08:30 PM PST 24 Mar 07 01:08:34 PM PST 24 48260172 ps
T2100 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4036763378 Mar 07 01:08:29 PM PST 24 Mar 07 01:08:36 PM PST 24 110672359 ps
T2101 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1931384537 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:37 PM PST 24 178682227 ps
T2102 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2605092911 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:43 PM PST 24 192778483 ps
T2103 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2684659970 Mar 07 01:08:46 PM PST 24 Mar 07 01:09:06 PM PST 24 3711361151 ps
T2104 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.297508350 Mar 07 01:19:41 PM PST 24 Mar 07 01:19:45 PM PST 24 518463425 ps
T2105 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2370349791 Mar 07 01:19:40 PM PST 24 Mar 07 01:19:41 PM PST 24 15119898 ps
T2106 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.717631052 Mar 07 01:08:46 PM PST 24 Mar 07 01:08:49 PM PST 24 93358213 ps
T2107 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.558638816 Mar 07 01:08:34 PM PST 24 Mar 07 01:08:42 PM PST 24 1175227928 ps
T2108 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1023432067 Mar 07 01:19:31 PM PST 24 Mar 07 01:19:35 PM PST 24 257465513 ps
T2109 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1952987825 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:36 PM PST 24 115113577 ps
T2110 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3136519856 Mar 07 01:19:55 PM PST 24 Mar 07 01:19:55 PM PST 24 38689663 ps
T2111 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3991326146 Mar 07 01:08:48 PM PST 24 Mar 07 01:08:49 PM PST 24 17724638 ps
T2112 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.847718617 Mar 07 01:19:27 PM PST 24 Mar 07 01:19:42 PM PST 24 842696144 ps
T2113 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1327733909 Mar 07 01:19:50 PM PST 24 Mar 07 01:20:10 PM PST 24 1026515435 ps
T2114 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1107830994 Mar 07 01:08:49 PM PST 24 Mar 07 01:08:57 PM PST 24 350488661 ps
T2115 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4026990705 Mar 07 01:08:30 PM PST 24 Mar 07 01:08:32 PM PST 24 122931253 ps
T2116 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3886414747 Mar 07 01:08:46 PM PST 24 Mar 07 01:09:08 PM PST 24 789784131 ps
T2117 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3073636429 Mar 07 01:08:28 PM PST 24 Mar 07 01:08:32 PM PST 24 604154344 ps
T2118 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3802526195 Mar 07 01:19:41 PM PST 24 Mar 07 01:19:43 PM PST 24 102926797 ps
T2119 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1487583243 Mar 07 01:19:37 PM PST 24 Mar 07 01:19:42 PM PST 24 1486836239 ps
T2120 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2474595493 Mar 07 01:08:45 PM PST 24 Mar 07 01:08:47 PM PST 24 38213896 ps
T2121 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3211087534 Mar 07 01:08:56 PM PST 24 Mar 07 01:08:57 PM PST 24 14830514 ps
T2122 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1573296959 Mar 07 01:08:52 PM PST 24 Mar 07 01:08:53 PM PST 24 43770825 ps
T2123 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3892538077 Mar 07 01:19:42 PM PST 24 Mar 07 01:19:44 PM PST 24 30749959 ps
T2124 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3233602841 Mar 07 01:20:07 PM PST 24 Mar 07 01:20:08 PM PST 24 33377708 ps
T172 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4045875824 Mar 07 01:19:48 PM PST 24 Mar 07 01:19:54 PM PST 24 372005372 ps
T2125 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.17978172 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:52 PM PST 24 25228251 ps
T2126 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1049814772 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:43 PM PST 24 1653248707 ps
T2127 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2527636374 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:33 PM PST 24 14580831 ps
T2128 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1254888957 Mar 07 01:08:29 PM PST 24 Mar 07 01:08:30 PM PST 24 31227607 ps
T2129 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4209356191 Mar 07 01:19:30 PM PST 24 Mar 07 01:19:42 PM PST 24 943985011 ps
T2130 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2284316102 Mar 07 01:19:45 PM PST 24 Mar 07 01:19:49 PM PST 24 326067906 ps
T2131 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2001241384 Mar 07 01:08:46 PM PST 24 Mar 07 01:08:47 PM PST 24 34371595 ps
T2132 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1813420352 Mar 07 01:08:34 PM PST 24 Mar 07 01:08:35 PM PST 24 11408385 ps
T2133 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.892178402 Mar 07 01:19:42 PM PST 24 Mar 07 01:19:46 PM PST 24 215974538 ps
T2134 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1227965364 Mar 07 01:08:31 PM PST 24 Mar 07 01:08:34 PM PST 24 91240009 ps
T2135 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4014792411 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:55 PM PST 24 220771466 ps
T2136 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1284173341 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:53 PM PST 24 34270523 ps
T2137 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2816471563 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:35 PM PST 24 30629425 ps
T2138 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.269093959 Mar 07 01:20:02 PM PST 24 Mar 07 01:20:03 PM PST 24 33595131 ps
T2139 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1631030168 Mar 07 01:08:30 PM PST 24 Mar 07 01:09:09 PM PST 24 2705793608 ps
T2140 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1246424851 Mar 07 01:08:31 PM PST 24 Mar 07 01:08:56 PM PST 24 4299377081 ps
T2141 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1869432621 Mar 07 01:19:54 PM PST 24 Mar 07 01:19:58 PM PST 24 422724252 ps
T2142 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.356965688 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:41 PM PST 24 58044803 ps
T2143 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2530333837 Mar 07 01:19:55 PM PST 24 Mar 07 01:19:57 PM PST 24 58863773 ps
T2144 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1880161336 Mar 07 01:08:56 PM PST 24 Mar 07 01:08:57 PM PST 24 139894151 ps
T2145 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.828083671 Mar 07 01:08:30 PM PST 24 Mar 07 01:08:32 PM PST 24 38634658 ps
T2146 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1763204927 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:58 PM PST 24 1566044735 ps
T2147 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.674697915 Mar 07 01:08:31 PM PST 24 Mar 07 01:08:40 PM PST 24 376465800 ps
T2148 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2461893903 Mar 07 01:19:41 PM PST 24 Mar 07 01:19:44 PM PST 24 90890652 ps
T2149 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1475311892 Mar 07 01:08:36 PM PST 24 Mar 07 01:08:38 PM PST 24 39825245 ps
T2150 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3260884208 Mar 07 01:08:50 PM PST 24 Mar 07 01:08:53 PM PST 24 53557289 ps
T2151 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4094230726 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:56 PM PST 24 206293507 ps
T2152 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2702731444 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:36 PM PST 24 100441255 ps
T2153 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2794568723 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:57 PM PST 24 547788706 ps
T2154 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.48087263 Mar 07 01:08:30 PM PST 24 Mar 07 01:08:41 PM PST 24 183806402 ps
T2155 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.705338381 Mar 07 01:08:55 PM PST 24 Mar 07 01:08:56 PM PST 24 16393313 ps
T2156 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.301388391 Mar 07 01:19:31 PM PST 24 Mar 07 01:19:32 PM PST 24 29768030 ps
T2157 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1555741736 Mar 07 01:19:27 PM PST 24 Mar 07 01:19:29 PM PST 24 75530326 ps
T2158 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2187140072 Mar 07 01:19:27 PM PST 24 Mar 07 01:20:02 PM PST 24 1046549123 ps
T2159 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3029916166 Mar 07 01:19:50 PM PST 24 Mar 07 01:19:52 PM PST 24 40902670 ps
T2160 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1150561848 Mar 07 01:19:30 PM PST 24 Mar 07 01:19:38 PM PST 24 223798967 ps
T2161 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3415381940 Mar 07 01:19:42 PM PST 24 Mar 07 01:20:02 PM PST 24 1036824927 ps
T2162 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.708140261 Mar 07 01:19:46 PM PST 24 Mar 07 01:19:59 PM PST 24 206669850 ps
T2163 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.742253818 Mar 07 01:19:28 PM PST 24 Mar 07 01:19:30 PM PST 24 138161750 ps
T2164 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4049303954 Mar 07 01:08:53 PM PST 24 Mar 07 01:08:56 PM PST 24 69013180 ps
T2165 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.835112830 Mar 07 01:08:35 PM PST 24 Mar 07 01:09:05 PM PST 24 1934683678 ps
T2166 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1480895789 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:36 PM PST 24 151045698 ps
T2167 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.988777464 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:53 PM PST 24 12361765 ps
T2168 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1080857958 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:57 PM PST 24 230365895 ps
T2169 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2075182427 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:56 PM PST 24 148012199 ps
T2170 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.139087486 Mar 07 01:08:31 PM PST 24 Mar 07 01:08:33 PM PST 24 24042385 ps
T2171 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2027297204 Mar 07 01:19:40 PM PST 24 Mar 07 01:19:41 PM PST 24 44751005 ps
T2172 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3368514008 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:34 PM PST 24 49133582 ps
T2173 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2477684184 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:40 PM PST 24 191125919 ps
T2174 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1746170147 Mar 07 01:08:38 PM PST 24 Mar 07 01:08:49 PM PST 24 200375651 ps
T2175 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2804806730 Mar 07 01:19:42 PM PST 24 Mar 07 01:19:42 PM PST 24 50160437 ps
T2176 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.958896416 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:53 PM PST 24 39069699 ps
T2177 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3487448405 Mar 07 01:19:32 PM PST 24 Mar 07 01:19:45 PM PST 24 989072418 ps
T2178 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3628311624 Mar 07 01:08:48 PM PST 24 Mar 07 01:08:52 PM PST 24 38711369 ps
T2179 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2528145233 Mar 07 01:08:28 PM PST 24 Mar 07 01:08:29 PM PST 24 180777436 ps
T2180 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.784042290 Mar 07 01:08:45 PM PST 24 Mar 07 01:08:46 PM PST 24 15377686 ps
T2181 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3237633900 Mar 07 01:19:38 PM PST 24 Mar 07 01:19:45 PM PST 24 143067214 ps
T2182 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1992336054 Mar 07 01:08:50 PM PST 24 Mar 07 01:08:59 PM PST 24 1216842417 ps
T2183 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.783093261 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:55 PM PST 24 144955193 ps
T2184 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1139437452 Mar 07 01:19:46 PM PST 24 Mar 07 01:19:47 PM PST 24 46513081 ps
T2185 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1623885915 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:34 PM PST 24 36763740 ps
T2186 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4019802542 Mar 07 01:08:48 PM PST 24 Mar 07 01:08:59 PM PST 24 392498041 ps
T2187 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.327303545 Mar 07 01:19:52 PM PST 24 Mar 07 01:19:54 PM PST 24 27520545 ps
T2188 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.60690611 Mar 07 01:19:53 PM PST 24 Mar 07 01:19:53 PM PST 24 45801730 ps
T2189 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.278578668 Mar 07 01:08:51 PM PST 24 Mar 07 01:08:52 PM PST 24 97368822 ps
T2190 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3588789529 Mar 07 01:08:46 PM PST 24 Mar 07 01:08:49 PM PST 24 189594643 ps
T2191 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2261168321 Mar 07 01:19:40 PM PST 24 Mar 07 01:19:43 PM PST 24 573101106 ps
T2192 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4216913517 Mar 07 01:08:47 PM PST 24 Mar 07 01:08:48 PM PST 24 29096974 ps
T2193 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.347658817 Mar 07 01:08:28 PM PST 24 Mar 07 01:08:30 PM PST 24 75023806 ps
T2194 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.423926244 Mar 07 01:08:47 PM PST 24 Mar 07 01:09:05 PM PST 24 2953377527 ps
T2195 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2893666035 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:47 PM PST 24 320225589 ps
T2196 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1225731653 Mar 07 01:20:02 PM PST 24 Mar 07 01:20:02 PM PST 24 15726466 ps
T2197 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3218196268 Mar 07 01:08:53 PM PST 24 Mar 07 01:08:56 PM PST 24 161404214 ps
T2198 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2514253605 Mar 07 01:19:46 PM PST 24 Mar 07 01:19:48 PM PST 24 100171299 ps
T2199 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2775650206 Mar 07 01:08:46 PM PST 24 Mar 07 01:08:48 PM PST 24 75064172 ps
T2200 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2512085881 Mar 07 01:08:48 PM PST 24 Mar 07 01:08:49 PM PST 24 23711587 ps
T2201 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3320244037 Mar 07 01:08:46 PM PST 24 Mar 07 01:08:48 PM PST 24 90685283 ps
T2202 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3139674200 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:34 PM PST 24 38524627 ps
T2203 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.629394870 Mar 07 01:08:47 PM PST 24 Mar 07 01:08:50 PM PST 24 619823049 ps
T2204 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2116221954 Mar 07 01:19:29 PM PST 24 Mar 07 01:19:36 PM PST 24 264689276 ps
T2205 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.505508612 Mar 07 01:08:30 PM PST 24 Mar 07 01:08:31 PM PST 24 24791044 ps
T2206 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1607734931 Mar 07 01:19:49 PM PST 24 Mar 07 01:19:51 PM PST 24 27067044 ps
T2207 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.458109367 Mar 07 01:19:39 PM PST 24 Mar 07 01:19:41 PM PST 24 105890527 ps
T2208 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1760296488 Mar 07 01:19:51 PM PST 24 Mar 07 01:19:52 PM PST 24 34816306 ps
T2209 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1555155167 Mar 07 01:08:32 PM PST 24 Mar 07 01:08:33 PM PST 24 11489414 ps
T2210 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3288670285 Mar 07 01:20:00 PM PST 24 Mar 07 01:20:01 PM PST 24 23715296 ps
T2211 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1245141762 Mar 07 01:08:33 PM PST 24 Mar 07 01:08:35 PM PST 24 92885873 ps

Test location /workspace/coverage/default/10.spi_device_stress_all.679230721
Short name T8
Test name
Test status
Simulation time 118593630085 ps
CPU time 453.69 seconds
Started Mar 07 02:43:34 PM PST 24
Finished Mar 07 02:51:08 PM PST 24
Peak memory 259208 kb
Host smart-304bc0a2-71fe-465f-84b0-413b81a61305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679230721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.679230721
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.129231637
Short name T18
Test name
Test status
Simulation time 2772432524 ps
CPU time 55.66 seconds
Started Mar 07 02:45:40 PM PST 24
Finished Mar 07 02:46:36 PM PST 24
Peak memory 240468 kb
Host smart-0d0d8e08-9f56-45f9-8c27-6fe3115e4b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129231637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.129231637
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_upload.2256709825
Short name T26
Test name
Test status
Simulation time 3454751704 ps
CPU time 9.19 seconds
Started Mar 07 12:43:55 PM PST 24
Finished Mar 07 12:44:04 PM PST 24
Peak memory 221004 kb
Host smart-015906e5-a28d-4edc-b74e-359af9461021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256709825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2256709825
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.217419643
Short name T34
Test name
Test status
Simulation time 114477412320 ps
CPU time 363.42 seconds
Started Mar 07 12:44:20 PM PST 24
Finished Mar 07 12:50:24 PM PST 24
Peak memory 306560 kb
Host smart-cfbb3d31-f381-4f5d-ac09-59a4f30f84d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217419643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.217419643
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.605691043
Short name T123
Test name
Test status
Simulation time 410010043 ps
CPU time 2.73 seconds
Started Mar 07 01:19:48 PM PST 24
Finished Mar 07 01:19:50 PM PST 24
Peak memory 215784 kb
Host smart-af29eac3-9ca5-4702-8d0c-2508b26d8587
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605691043 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.605691043
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.806700773
Short name T156
Test name
Test status
Simulation time 9153691346 ps
CPU time 132.82 seconds
Started Mar 07 02:43:21 PM PST 24
Finished Mar 07 02:45:33 PM PST 24
Peak memory 254164 kb
Host smart-b02ced88-b5e8-47af-9b6e-db67fa1d8b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806700773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.806700773
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.4025372818
Short name T492
Test name
Test status
Simulation time 34067669 ps
CPU time 0.72 seconds
Started Mar 07 02:43:53 PM PST 24
Finished Mar 07 02:43:53 PM PST 24
Peak memory 215588 kb
Host smart-8762bae3-688d-45a7-b3ce-de5ec3a54b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025372818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.4025372818
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1489023231
Short name T20
Test name
Test status
Simulation time 88008773302 ps
CPU time 418.02 seconds
Started Mar 07 02:46:13 PM PST 24
Finished Mar 07 02:53:12 PM PST 24
Peak memory 256264 kb
Host smart-1c1a33db-5c29-4f70-a2bb-df71525e04c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489023231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1489023231
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3042807936
Short name T110
Test name
Test status
Simulation time 482698711 ps
CPU time 8.44 seconds
Started Mar 07 12:43:36 PM PST 24
Finished Mar 07 12:43:45 PM PST 24
Peak memory 240604 kb
Host smart-f6e1340c-ddae-4d94-bf2b-fb53a978217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042807936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3042807936
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1747827444
Short name T206
Test name
Test status
Simulation time 11760274827 ps
CPU time 89.09 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:45:40 PM PST 24
Peak memory 252192 kb
Host smart-c1c5e4ac-d61e-4130-b121-af1a75daa1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747827444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1747827444
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2699591646
Short name T107
Test name
Test status
Simulation time 5687467255 ps
CPU time 21.49 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:53 PM PST 24
Peak memory 214796 kb
Host smart-a01744dd-5a41-4f37-a77a-9acceaeb7bca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699591646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2699591646
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.836141955
Short name T33
Test name
Test status
Simulation time 45234123939 ps
CPU time 311.08 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:48:59 PM PST 24
Peak memory 249120 kb
Host smart-c08375be-0fee-4a38-bad1-926c9f3dfa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836141955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.836141955
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2756392653
Short name T61
Test name
Test status
Simulation time 13707604 ps
CPU time 0.73 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:44:11 PM PST 24
Peak memory 204428 kb
Host smart-e4d4deb2-aec4-4db8-8d48-689b093aa815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756392653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2756392653
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1687785383
Short name T202
Test name
Test status
Simulation time 823008708625 ps
CPU time 377.34 seconds
Started Mar 07 02:42:55 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 249940 kb
Host smart-87176b85-438c-43eb-ad1c-c770af23c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687785383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1687785383
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3126085952
Short name T139
Test name
Test status
Simulation time 61577314077 ps
CPU time 236.58 seconds
Started Mar 07 12:42:35 PM PST 24
Finished Mar 07 12:46:31 PM PST 24
Peak memory 249240 kb
Host smart-570fc7ab-ffbf-45b3-ba9d-08ffef4894d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126085952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3126085952
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1590927206
Short name T74
Test name
Test status
Simulation time 289853442 ps
CPU time 1.08 seconds
Started Mar 07 12:40:50 PM PST 24
Finished Mar 07 12:40:51 PM PST 24
Peak memory 235456 kb
Host smart-4e89c444-d93d-414d-bcca-ae9150c26356
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590927206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1590927206
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.292576622
Short name T196
Test name
Test status
Simulation time 453963008410 ps
CPU time 509.95 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:52:18 PM PST 24
Peak memory 273816 kb
Host smart-9b2966d9-803b-4a81-bb5b-8a67bbf734d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292576622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.292576622
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1011190878
Short name T89
Test name
Test status
Simulation time 68494253 ps
CPU time 1.52 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 206520 kb
Host smart-abf7e488-e57f-4a9e-9b21-aa4b4a049613
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011190878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1011190878
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3169428361
Short name T112
Test name
Test status
Simulation time 296082887 ps
CPU time 5.44 seconds
Started Mar 07 01:08:49 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 214852 kb
Host smart-0735b7ff-6f9a-4713-84c4-17b84ab063c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169428361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3169428361
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.94471355
Short name T5
Test name
Test status
Simulation time 303456539792 ps
CPU time 325.95 seconds
Started Mar 07 02:44:26 PM PST 24
Finished Mar 07 02:49:52 PM PST 24
Peak memory 252896 kb
Host smart-d652ba13-9a0a-4ecf-a1e1-c33528daefbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94471355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.94471355
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.958061781
Short name T7
Test name
Test status
Simulation time 58097423 ps
CPU time 1.04 seconds
Started Mar 07 02:42:44 PM PST 24
Finished Mar 07 02:42:45 PM PST 24
Peak memory 217244 kb
Host smart-537724af-493d-479b-8a62-65ca82c82000
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958061781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.958061781
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1174378985
Short name T87
Test name
Test status
Simulation time 18297172933 ps
CPU time 156.31 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:45:47 PM PST 24
Peak memory 252060 kb
Host smart-3af8af22-c6f5-4c91-acbb-991a4575248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174378985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1174378985
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.580242636
Short name T46
Test name
Test status
Simulation time 27538539417 ps
CPU time 140.58 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:45:37 PM PST 24
Peak memory 269740 kb
Host smart-93e44605-bc10-41ac-bc05-5a817e7ab2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580242636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.580242636
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3210120690
Short name T250
Test name
Test status
Simulation time 3545183866 ps
CPU time 57.22 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:44:25 PM PST 24
Peak memory 255060 kb
Host smart-8c711b10-5237-435d-9227-518cc64780cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210120690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3210120690
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2866340494
Short name T298
Test name
Test status
Simulation time 24531877258 ps
CPU time 148.67 seconds
Started Mar 07 02:46:14 PM PST 24
Finished Mar 07 02:48:43 PM PST 24
Peak memory 272792 kb
Host smart-c5a38b74-9140-460f-9813-6a6e9283a46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866340494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2866340494
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1707998438
Short name T246
Test name
Test status
Simulation time 34402686374 ps
CPU time 73.95 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:43:06 PM PST 24
Peak memory 265928 kb
Host smart-871feaca-0ab4-4b18-8ad0-8782c2cb7ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707998438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1707998438
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.173105476
Short name T251
Test name
Test status
Simulation time 1228146995883 ps
CPU time 507.3 seconds
Started Mar 07 02:44:27 PM PST 24
Finished Mar 07 02:52:55 PM PST 24
Peak memory 264936 kb
Host smart-68ac32a8-8046-4e21-8de4-7a22a0c93030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173105476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.173105476
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.360926727
Short name T1360
Test name
Test status
Simulation time 78436996719 ps
CPU time 585.15 seconds
Started Mar 07 02:44:36 PM PST 24
Finished Mar 07 02:54:21 PM PST 24
Peak memory 266028 kb
Host smart-9cd39f39-d38c-4825-96df-2b5ad8c081e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360926727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.360926727
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3766987203
Short name T174
Test name
Test status
Simulation time 1836275243 ps
CPU time 21.13 seconds
Started Mar 07 01:19:37 PM PST 24
Finished Mar 07 01:19:58 PM PST 24
Peak memory 214760 kb
Host smart-750cc389-6d01-482a-9657-dbba49ee01a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766987203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3766987203
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1689375896
Short name T93
Test name
Test status
Simulation time 18384639807 ps
CPU time 16.18 seconds
Started Mar 07 12:42:06 PM PST 24
Finished Mar 07 12:42:23 PM PST 24
Peak memory 216188 kb
Host smart-adce2c14-b16b-4d94-9cbf-4ffe33ae94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689375896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1689375896
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.273523629
Short name T83
Test name
Test status
Simulation time 7055064056 ps
CPU time 25.96 seconds
Started Mar 07 02:45:27 PM PST 24
Finished Mar 07 02:45:53 PM PST 24
Peak memory 248212 kb
Host smart-7e6d5ff1-1c3a-4c01-840c-9ae7bab14d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273523629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.273523629
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1764382733
Short name T1161
Test name
Test status
Simulation time 263568463652 ps
CPU time 961.82 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:59:58 PM PST 24
Peak memory 298320 kb
Host smart-1b019d9c-9465-484d-bece-1f7813ea5570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764382733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1764382733
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.715430374
Short name T30
Test name
Test status
Simulation time 55788999726 ps
CPU time 413.37 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:50:08 PM PST 24
Peak memory 254160 kb
Host smart-516a8593-6a69-4574-a8a5-5cf3bc568d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715430374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
715430374
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2343312160
Short name T117
Test name
Test status
Simulation time 706562721 ps
CPU time 5.48 seconds
Started Mar 07 01:19:50 PM PST 24
Finished Mar 07 01:19:56 PM PST 24
Peak memory 214816 kb
Host smart-018806dc-b815-447d-960f-c89007157c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343312160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2343312160
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3832114631
Short name T186
Test name
Test status
Simulation time 59920002223 ps
CPU time 10.56 seconds
Started Mar 07 02:42:45 PM PST 24
Finished Mar 07 02:42:56 PM PST 24
Peak memory 233632 kb
Host smart-a620d1dc-fca2-4606-81f6-5e0cfd9541fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832114631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3832114631
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1304764570
Short name T79
Test name
Test status
Simulation time 94434823426 ps
CPU time 253.86 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:47:42 PM PST 24
Peak memory 253588 kb
Host smart-eb845f3c-5861-41e2-9408-a6cee152977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304764570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1304764570
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2722964582
Short name T1750
Test name
Test status
Simulation time 745618725120 ps
CPU time 672.37 seconds
Started Mar 07 12:42:10 PM PST 24
Finished Mar 07 12:53:23 PM PST 24
Peak memory 272324 kb
Host smart-a221a4a6-1f10-46d3-b31f-daa195474ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722964582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2722964582
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.159604295
Short name T146
Test name
Test status
Simulation time 540318924 ps
CPU time 10.42 seconds
Started Mar 07 02:45:06 PM PST 24
Finished Mar 07 02:45:17 PM PST 24
Peak memory 234620 kb
Host smart-a9844073-6032-4270-b082-72c088c1e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159604295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.159604295
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3563021449
Short name T176
Test name
Test status
Simulation time 4322139633 ps
CPU time 16.1 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 214728 kb
Host smart-688d3fbe-4aa9-42f6-89a4-d9c7d81aec89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563021449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3563021449
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.543715682
Short name T141
Test name
Test status
Simulation time 47993797108 ps
CPU time 315.94 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:47:08 PM PST 24
Peak memory 256460 kb
Host smart-5f012b6c-d9a3-41b9-a6a5-3ffb231f5cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543715682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.543715682
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2047158044
Short name T1796
Test name
Test status
Simulation time 5531529284 ps
CPU time 54.62 seconds
Started Mar 07 02:44:09 PM PST 24
Finished Mar 07 02:45:04 PM PST 24
Peak memory 251128 kb
Host smart-df43a589-5a99-418e-becd-1720557147f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047158044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2047158044
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4233583511
Short name T282
Test name
Test status
Simulation time 263956759080 ps
CPU time 140.74 seconds
Started Mar 07 12:42:28 PM PST 24
Finished Mar 07 12:44:50 PM PST 24
Peak memory 232688 kb
Host smart-d670d3c3-ab7b-49c2-8142-b085ebedd86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233583511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4233583511
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3390403285
Short name T1213
Test name
Test status
Simulation time 456073899697 ps
CPU time 228.37 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:46:25 PM PST 24
Peak memory 256000 kb
Host smart-e395fc8b-1786-470a-9ffe-1cbef1a43785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390403285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3390403285
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3685214983
Short name T1676
Test name
Test status
Simulation time 55497284826 ps
CPU time 284.56 seconds
Started Mar 07 02:45:10 PM PST 24
Finished Mar 07 02:49:55 PM PST 24
Peak memory 268788 kb
Host smart-1dfea0b9-0470-4012-b47e-2c1adfb13e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685214983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3685214983
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1730796312
Short name T17
Test name
Test status
Simulation time 4658145277 ps
CPU time 43.03 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:42:52 PM PST 24
Peak memory 240160 kb
Host smart-66eb9acd-82d3-4238-8bf9-d4782e0b74f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730796312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1730796312
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1334038218
Short name T1989
Test name
Test status
Simulation time 503879284 ps
CPU time 4.05 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:43 PM PST 24
Peak memory 214888 kb
Host smart-2b6e71ef-acf3-46aa-b2ad-7e15eaabdf27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334038218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1334038218
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2036018681
Short name T119
Test name
Test status
Simulation time 478377596 ps
CPU time 12.89 seconds
Started Mar 07 01:19:49 PM PST 24
Finished Mar 07 01:20:03 PM PST 24
Peak memory 214708 kb
Host smart-9d7ccf4d-0e35-48cf-ad2a-935dd8aef15a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036018681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2036018681
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4272967694
Short name T154
Test name
Test status
Simulation time 443151113 ps
CPU time 10.1 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:43 PM PST 24
Peak memory 214740 kb
Host smart-bb6a5d1b-a04c-4401-b2b7-80a52234c664
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272967694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4272967694
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.847718617
Short name T2112
Test name
Test status
Simulation time 842696144 ps
CPU time 14.71 seconds
Started Mar 07 01:19:27 PM PST 24
Finished Mar 07 01:19:42 PM PST 24
Peak memory 214752 kb
Host smart-611930b4-90c0-4fd0-b883-03b34e7d20cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847718617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.847718617
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4209356191
Short name T2129
Test name
Test status
Simulation time 943985011 ps
CPU time 12.2 seconds
Started Mar 07 01:19:30 PM PST 24
Finished Mar 07 01:19:42 PM PST 24
Peak memory 206052 kb
Host smart-3db24668-8279-4bed-8245-ae4cba11b509
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209356191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4209356191
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.48087263
Short name T2154
Test name
Test status
Simulation time 183806402 ps
CPU time 11.39 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:41 PM PST 24
Peak memory 206180 kb
Host smart-73dda319-cd0a-4ec9-bef3-c366e50793bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48087263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
bit_bash.48087263
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1351700998
Short name T2039
Test name
Test status
Simulation time 76958395 ps
CPU time 1.56 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:25 PM PST 24
Peak memory 206540 kb
Host smart-157491f6-b7f6-4959-9ddd-96727dee73db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351700998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1351700998
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3943637424
Short name T2089
Test name
Test status
Simulation time 356752929 ps
CPU time 3.03 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 214860 kb
Host smart-2da39dbf-887f-493f-be58-17425f97a9b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943637424 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3943637424
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4100551383
Short name T2069
Test name
Test status
Simulation time 175577468 ps
CPU time 2.74 seconds
Started Mar 07 01:19:36 PM PST 24
Finished Mar 07 01:19:39 PM PST 24
Peak memory 215868 kb
Host smart-07a64d6d-6aae-43db-9ddb-51ed3bc8ac8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100551383 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4100551383
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2638299214
Short name T2057
Test name
Test status
Simulation time 201499837 ps
CPU time 2.51 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 214720 kb
Host smart-3ed8d0c6-e68c-45c9-aae8-b7b4cc78f6c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638299214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
638299214
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.742253818
Short name T2163
Test name
Test status
Simulation time 138161750 ps
CPU time 2.38 seconds
Started Mar 07 01:19:28 PM PST 24
Finished Mar 07 01:19:30 PM PST 24
Peak memory 214768 kb
Host smart-c6ba6887-d86f-47ce-bc2a-f0c7d5bd5c09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742253818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.742253818
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3542327354
Short name T1984
Test name
Test status
Simulation time 16548558 ps
CPU time 0.82 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:31 PM PST 24
Peak memory 202524 kb
Host smart-8375dd85-8cd4-4494-ace9-3302a057d4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542327354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
542327354
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3779548843
Short name T2021
Test name
Test status
Simulation time 31080684 ps
CPU time 0.75 seconds
Started Mar 07 01:19:23 PM PST 24
Finished Mar 07 01:19:24 PM PST 24
Peak memory 202796 kb
Host smart-01979137-9b62-44ab-ab5c-4ffb0a7aebd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779548843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
779548843
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.14953708
Short name T1963
Test name
Test status
Simulation time 116474438 ps
CPU time 2.31 seconds
Started Mar 07 01:08:37 PM PST 24
Finished Mar 07 01:08:39 PM PST 24
Peak memory 214620 kb
Host smart-30370df0-22db-4cc7-8ad7-367eae8abcea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14953708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_d
evice_mem_partial_access.14953708
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1801470459
Short name T1973
Test name
Test status
Simulation time 579922230 ps
CPU time 2.28 seconds
Started Mar 07 01:19:29 PM PST 24
Finished Mar 07 01:19:31 PM PST 24
Peak memory 214664 kb
Host smart-e2890bea-c789-4438-931e-43a2861b289b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801470459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1801470459
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1312664339
Short name T2070
Test name
Test status
Simulation time 13382771 ps
CPU time 0.65 seconds
Started Mar 07 01:08:29 PM PST 24
Finished Mar 07 01:08:30 PM PST 24
Peak memory 202392 kb
Host smart-ddae6d13-bfe2-4300-adee-55c01b4011d4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312664339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1312664339
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.83920702
Short name T2065
Test name
Test status
Simulation time 12657104 ps
CPU time 0.67 seconds
Started Mar 07 01:19:28 PM PST 24
Finished Mar 07 01:19:29 PM PST 24
Peak memory 202436 kb
Host smart-e516b7d9-c52d-4f55-99e5-ca8af403f739
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83920702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_
walk.83920702
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1280112429
Short name T1926
Test name
Test status
Simulation time 42634793 ps
CPU time 2.9 seconds
Started Mar 07 01:08:34 PM PST 24
Finished Mar 07 01:08:38 PM PST 24
Peak memory 214480 kb
Host smart-dc29e039-3dda-4c6c-a341-03a9a323ede2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280112429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1280112429
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.678883138
Short name T2005
Test name
Test status
Simulation time 132501612 ps
CPU time 3.38 seconds
Started Mar 07 01:19:47 PM PST 24
Finished Mar 07 01:19:51 PM PST 24
Peak memory 214388 kb
Host smart-cdfbe3e6-e10b-4e15-862e-a30c55941814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678883138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.678883138
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2525981277
Short name T2099
Test name
Test status
Simulation time 48260172 ps
CPU time 3.69 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:34 PM PST 24
Peak memory 214960 kb
Host smart-f9b7347c-a90b-4d3a-a92c-d94991cc4269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525981277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
525981277
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.28013177
Short name T1967
Test name
Test status
Simulation time 75590946 ps
CPU time 2.31 seconds
Started Mar 07 01:19:21 PM PST 24
Finished Mar 07 01:19:23 PM PST 24
Peak memory 214780 kb
Host smart-67319285-1e15-4226-8cee-3ad3122bc499
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.28013177
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2116221954
Short name T2204
Test name
Test status
Simulation time 264689276 ps
CPU time 7.49 seconds
Started Mar 07 01:19:29 PM PST 24
Finished Mar 07 01:19:36 PM PST 24
Peak memory 215156 kb
Host smart-2a1017b5-f175-4e86-894b-b30497fa8787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116221954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2116221954
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1630775366
Short name T1972
Test name
Test status
Simulation time 2053560304 ps
CPU time 8.32 seconds
Started Mar 07 01:19:30 PM PST 24
Finished Mar 07 01:19:39 PM PST 24
Peak memory 206444 kb
Host smart-0f7275d8-b6f4-4360-b4f6-a074df092774
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630775366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1630775366
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2432640842
Short name T133
Test name
Test status
Simulation time 4136631754 ps
CPU time 21.98 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:52 PM PST 24
Peak memory 214780 kb
Host smart-c0971b97-e81a-424b-9619-51d56b09621a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432640842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2432640842
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2187140072
Short name T2158
Test name
Test status
Simulation time 1046549123 ps
CPU time 34.76 seconds
Started Mar 07 01:19:27 PM PST 24
Finished Mar 07 01:20:02 PM PST 24
Peak memory 206444 kb
Host smart-306319c3-a385-4254-b2f1-71a5488b6b93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187140072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2187140072
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.935644864
Short name T2084
Test name
Test status
Simulation time 191846408 ps
CPU time 12.52 seconds
Started Mar 07 01:08:29 PM PST 24
Finished Mar 07 01:08:42 PM PST 24
Peak memory 206448 kb
Host smart-1af89038-3ae7-4ac0-b49b-158e971f6b7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935644864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.935644864
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.348146012
Short name T90
Test name
Test status
Simulation time 26731028 ps
CPU time 0.95 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:32 PM PST 24
Peak memory 206076 kb
Host smart-2f2c91ee-4e83-49d2-b0fb-e9f6a470d110
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348146012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.348146012
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3921467236
Short name T91
Test name
Test status
Simulation time 18057747 ps
CPU time 1.15 seconds
Started Mar 07 01:19:30 PM PST 24
Finished Mar 07 01:19:31 PM PST 24
Peak memory 206344 kb
Host smart-86000d3d-de6e-45ca-b10b-fb4b729de436
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921467236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3921467236
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1208113541
Short name T122
Test name
Test status
Simulation time 136934202 ps
CPU time 3.89 seconds
Started Mar 07 01:19:28 PM PST 24
Finished Mar 07 01:19:32 PM PST 24
Peak memory 215884 kb
Host smart-89d80f43-a14a-4d9c-8504-10c8e4c66237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208113541 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1208113541
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1564065825
Short name T1941
Test name
Test status
Simulation time 117231490 ps
CPU time 3.72 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 215856 kb
Host smart-27692129-1396-4b30-89f0-e0e4383b9e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564065825 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1564065825
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1555741736
Short name T2157
Test name
Test status
Simulation time 75530326 ps
CPU time 2.15 seconds
Started Mar 07 01:19:27 PM PST 24
Finished Mar 07 01:19:29 PM PST 24
Peak memory 214736 kb
Host smart-275f5af0-d75d-4afb-a41b-727cec861938
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555741736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
555741736
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3368514008
Short name T2172
Test name
Test status
Simulation time 49133582 ps
CPU time 1.46 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:34 PM PST 24
Peak memory 214676 kb
Host smart-d6e67c72-5ec1-492e-a96d-6fbfe5a1d871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368514008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
368514008
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1623885915
Short name T2185
Test name
Test status
Simulation time 36763740 ps
CPU time 0.82 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:34 PM PST 24
Peak memory 202640 kb
Host smart-00bc2127-6603-4da8-a9e4-9b39a222c914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623885915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
623885915
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.291644276
Short name T1928
Test name
Test status
Simulation time 26442074 ps
CPU time 0.69 seconds
Started Mar 07 01:19:41 PM PST 24
Finished Mar 07 01:19:42 PM PST 24
Peak memory 202512 kb
Host smart-cc077065-8e43-4892-af86-21dc4e49d2f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291644276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.291644276
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.149188685
Short name T138
Test name
Test status
Simulation time 51249850 ps
CPU time 1.68 seconds
Started Mar 07 01:19:29 PM PST 24
Finished Mar 07 01:19:31 PM PST 24
Peak memory 214720 kb
Host smart-8976302a-9ce5-4d77-82c1-a3ba02b01f6f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149188685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.149188685
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3778304721
Short name T1979
Test name
Test status
Simulation time 148837875 ps
CPU time 1.35 seconds
Started Mar 07 01:08:29 PM PST 24
Finished Mar 07 01:08:31 PM PST 24
Peak memory 214616 kb
Host smart-2d72312d-baf4-4938-b9cf-cb72866f9347
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778304721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3778304721
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2375170283
Short name T2076
Test name
Test status
Simulation time 37357499 ps
CPU time 0.65 seconds
Started Mar 07 01:19:31 PM PST 24
Finished Mar 07 01:19:32 PM PST 24
Peak memory 202800 kb
Host smart-2918ccc9-ec34-4ea8-abb9-1ae608f54873
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375170283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2375170283
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.577515194
Short name T2091
Test name
Test status
Simulation time 13026665 ps
CPU time 0.66 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:32 PM PST 24
Peak memory 202428 kb
Host smart-d9f8c080-b545-41e0-8da6-4be436c0b1de
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577515194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.577515194
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1531291883
Short name T2085
Test name
Test status
Simulation time 157262444 ps
CPU time 1.79 seconds
Started Mar 07 01:19:29 PM PST 24
Finished Mar 07 01:19:31 PM PST 24
Peak memory 214512 kb
Host smart-42a15916-e9ec-4a54-8543-15fbc13284ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531291883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1531291883
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4026990705
Short name T2115
Test name
Test status
Simulation time 122931253 ps
CPU time 1.87 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:32 PM PST 24
Peak memory 206404 kb
Host smart-b73362c2-ba13-47de-8247-9b15fa5eb4c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026990705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4026990705
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1023432067
Short name T2108
Test name
Test status
Simulation time 257465513 ps
CPU time 3.7 seconds
Started Mar 07 01:19:31 PM PST 24
Finished Mar 07 01:19:35 PM PST 24
Peak memory 214756 kb
Host smart-7ba2bd94-b8eb-4254-9e79-4bacf0336b12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023432067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
023432067
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1227965364
Short name T2134
Test name
Test status
Simulation time 91240009 ps
CPU time 2.65 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:34 PM PST 24
Peak memory 214724 kb
Host smart-a8a3a6f8-6123-4da3-b1b3-6816257af7c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227965364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
227965364
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1537293526
Short name T2020
Test name
Test status
Simulation time 2196748547 ps
CPU time 8.3 seconds
Started Mar 07 01:19:27 PM PST 24
Finished Mar 07 01:19:35 PM PST 24
Peak memory 214844 kb
Host smart-a6210bad-1db2-4bf9-a1d2-842c36a83728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537293526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1537293526
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4036763378
Short name T2100
Test name
Test status
Simulation time 110672359 ps
CPU time 6.78 seconds
Started Mar 07 01:08:29 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 214716 kb
Host smart-427d018b-fe58-4e25-93d0-4e65e50e0830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036763378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.4036763378
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.197803900
Short name T102
Test name
Test status
Simulation time 200663934 ps
CPU time 1.79 seconds
Started Mar 07 01:08:34 PM PST 24
Finished Mar 07 01:08:37 PM PST 24
Peak memory 214752 kb
Host smart-0841c870-8aa2-4208-a332-1ad070e6a106
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197803900 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.197803900
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3428884710
Short name T2067
Test name
Test status
Simulation time 192543946 ps
CPU time 3.85 seconds
Started Mar 07 01:19:42 PM PST 24
Finished Mar 07 01:19:46 PM PST 24
Peak memory 216404 kb
Host smart-57c767e7-174e-4b51-86b9-06e0392b1c19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428884710 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3428884710
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3150473835
Short name T129
Test name
Test status
Simulation time 27298931 ps
CPU time 1.87 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:19:40 PM PST 24
Peak memory 214712 kb
Host smart-c7bedb81-96a0-4d48-bec4-d6b8cd81c568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150473835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3150473835
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.955978912
Short name T2011
Test name
Test status
Simulation time 28923404 ps
CPU time 1.13 seconds
Started Mar 07 01:08:34 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 206444 kb
Host smart-b0d4def0-a912-41e5-89ae-35e6c54a74e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955978912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.955978912
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1555155167
Short name T2209
Test name
Test status
Simulation time 11489414 ps
CPU time 0.79 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 202584 kb
Host smart-5b8e4c12-5c12-4502-8ba7-edbabb2d3291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555155167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1555155167
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2810527003
Short name T2062
Test name
Test status
Simulation time 40375672 ps
CPU time 0.72 seconds
Started Mar 07 01:19:48 PM PST 24
Finished Mar 07 01:19:48 PM PST 24
Peak memory 202572 kb
Host smart-34ab0719-d002-4c65-a451-401501e0a0e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810527003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2810527003
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1952987825
Short name T2109
Test name
Test status
Simulation time 115113577 ps
CPU time 1.88 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 214676 kb
Host smart-abd13ac7-f951-461b-a151-6298094b83e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952987825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1952987825
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2923369938
Short name T155
Test name
Test status
Simulation time 242868233 ps
CPU time 2.98 seconds
Started Mar 07 01:19:46 PM PST 24
Finished Mar 07 01:19:49 PM PST 24
Peak memory 214652 kb
Host smart-a1be2734-0923-4061-9ebe-5a296952c2ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923369938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2923369938
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2496899873
Short name T2016
Test name
Test status
Simulation time 240460050 ps
CPU time 2.47 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 214764 kb
Host smart-1b4e3909-7985-41f0-b03d-b05c8e91db00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496899873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2496899873
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2646047014
Short name T177
Test name
Test status
Simulation time 3892530236 ps
CPU time 21.16 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:53 PM PST 24
Peak memory 214788 kb
Host smart-7fe6d209-7c2d-49b8-9335-6f34b2f6c381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646047014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2646047014
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4192260053
Short name T179
Test name
Test status
Simulation time 310498397 ps
CPU time 19.4 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:20:00 PM PST 24
Peak memory 215068 kb
Host smart-91b60cb5-8efb-490c-91e4-77ff635b52ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192260053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4192260053
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.327303545
Short name T2187
Test name
Test status
Simulation time 27520545 ps
CPU time 1.78 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 214804 kb
Host smart-cebfaeef-7178-4486-96d7-4663da3e61ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327303545 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.327303545
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3588789529
Short name T2190
Test name
Test status
Simulation time 189594643 ps
CPU time 3.46 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 216192 kb
Host smart-f977eadb-6d37-4dd7-9996-319e1d5f9970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588789529 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3588789529
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1279337549
Short name T2058
Test name
Test status
Simulation time 234176820 ps
CPU time 2.1 seconds
Started Mar 07 01:08:45 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 206560 kb
Host smart-df54c81c-f782-42d9-90d1-f8519c82353f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279337549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1279337549
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1314872009
Short name T2088
Test name
Test status
Simulation time 105497648 ps
CPU time 1.71 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 214676 kb
Host smart-767713d0-150f-4767-ab73-04739a739850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314872009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1314872009
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2390738650
Short name T1959
Test name
Test status
Simulation time 13377343 ps
CPU time 0.69 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:41 PM PST 24
Peak memory 202536 kb
Host smart-28bdea4b-a816-4c29-936f-d8acc3590861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390738650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2390738650
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.955515244
Short name T1997
Test name
Test status
Simulation time 28213067 ps
CPU time 0.78 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 202852 kb
Host smart-490e043f-6978-4357-8cba-1d68a91e1b85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955515244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.955515244
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4094230726
Short name T2151
Test name
Test status
Simulation time 206293507 ps
CPU time 4.18 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:56 PM PST 24
Peak memory 214776 kb
Host smart-a5d15537-6fc3-4cbb-8b9e-fb0497439baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094230726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4094230726
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.53719883
Short name T2059
Test name
Test status
Simulation time 153776363 ps
CPU time 4.01 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:50 PM PST 24
Peak memory 214528 kb
Host smart-7a65e374-65db-4858-90c7-664d76bb1488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53719883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sp
i_device_same_csr_outstanding.53719883
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2461893903
Short name T2148
Test name
Test status
Simulation time 90890652 ps
CPU time 2.1 seconds
Started Mar 07 01:19:41 PM PST 24
Finished Mar 07 01:19:44 PM PST 24
Peak memory 214796 kb
Host smart-018fe662-8c72-4f89-aa41-b69b94f14172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461893903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2461893903
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3904645897
Short name T2030
Test name
Test status
Simulation time 71648462 ps
CPU time 2.29 seconds
Started Mar 07 01:08:44 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 214776 kb
Host smart-4517dc31-bda4-4ced-8ff7-76241fee30ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904645897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3904645897
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1992336054
Short name T2182
Test name
Test status
Simulation time 1216842417 ps
CPU time 8.73 seconds
Started Mar 07 01:08:50 PM PST 24
Finished Mar 07 01:08:59 PM PST 24
Peak memory 214664 kb
Host smart-4c825c54-8327-4c6b-b417-4ca0976ebed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992336054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1992336054
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.708140261
Short name T2162
Test name
Test status
Simulation time 206669850 ps
CPU time 12.7 seconds
Started Mar 07 01:19:46 PM PST 24
Finished Mar 07 01:19:59 PM PST 24
Peak memory 221252 kb
Host smart-f0de9074-5039-4e15-b7b3-b0df23f27c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708140261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.708140261
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1607734931
Short name T2206
Test name
Test status
Simulation time 27067044 ps
CPU time 1.67 seconds
Started Mar 07 01:19:49 PM PST 24
Finished Mar 07 01:19:51 PM PST 24
Peak memory 214808 kb
Host smart-65c94dd0-2fc0-4ac1-bdca-27a18143275e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607734931 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1607734931
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4234206696
Short name T2043
Test name
Test status
Simulation time 929630226 ps
CPU time 4.2 seconds
Started Mar 07 01:08:51 PM PST 24
Finished Mar 07 01:08:55 PM PST 24
Peak memory 216116 kb
Host smart-d5fa9aa8-2b13-4cf3-952a-0cc2fdc2b49e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234206696 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4234206696
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2476398244
Short name T2093
Test name
Test status
Simulation time 235553022 ps
CPU time 1.17 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 206468 kb
Host smart-c1f60d16-4eef-4412-badd-a8257913fb42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476398244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2476398244
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4049303954
Short name T2164
Test name
Test status
Simulation time 69013180 ps
CPU time 2.24 seconds
Started Mar 07 01:08:53 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 206400 kb
Host smart-90d82309-2354-42c8-9554-6f1b6251c613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049303954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4049303954
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1653023528
Short name T1934
Test name
Test status
Simulation time 59559516 ps
CPU time 0.72 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:46 PM PST 24
Peak memory 202592 kb
Host smart-f62d2855-abea-430b-b5c6-521e0b457772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653023528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1653023528
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2709376856
Short name T1920
Test name
Test status
Simulation time 25579478 ps
CPU time 0.75 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 202640 kb
Host smart-83faecd2-edc4-49df-a7db-4cdd89f814ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709376856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2709376856
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1626659491
Short name T152
Test name
Test status
Simulation time 394112243 ps
CPU time 3.75 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 214504 kb
Host smart-de3a022d-84f0-4e2f-be0c-20f288b4e6b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626659491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1626659491
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.792020723
Short name T151
Test name
Test status
Simulation time 196362947 ps
CPU time 4.28 seconds
Started Mar 07 01:08:44 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 206468 kb
Host smart-18929a79-ce63-4ee7-ae98-fdb7ce358037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792020723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.792020723
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1869432621
Short name T2141
Test name
Test status
Simulation time 422724252 ps
CPU time 3.5 seconds
Started Mar 07 01:19:54 PM PST 24
Finished Mar 07 01:19:58 PM PST 24
Peak memory 214700 kb
Host smart-ddb5117b-bfde-4a3e-a3d1-2cb340a96fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869432621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1869432621
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1786492702
Short name T2026
Test name
Test status
Simulation time 1640809642 ps
CPU time 23.49 seconds
Started Mar 07 01:19:50 PM PST 24
Finished Mar 07 01:20:14 PM PST 24
Peak memory 215072 kb
Host smart-fb032329-7003-4e2c-af0e-4f99cb34ded4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786492702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1786492702
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3035934451
Short name T2029
Test name
Test status
Simulation time 2320537480 ps
CPU time 8.83 seconds
Started Mar 07 01:08:51 PM PST 24
Finished Mar 07 01:09:00 PM PST 24
Peak memory 214936 kb
Host smart-d7d6058c-2e3e-48ba-a408-a709920960f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035934451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3035934451
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3504002621
Short name T1953
Test name
Test status
Simulation time 263842525 ps
CPU time 4.07 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 216124 kb
Host smart-89447953-012e-48d7-a5ee-d28056fb10f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504002621 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3504002621
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.624341222
Short name T126
Test name
Test status
Simulation time 54828079 ps
CPU time 1.83 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:50 PM PST 24
Peak memory 214724 kb
Host smart-fefd2255-3c48-4699-a6e5-4d6353fd383d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624341222 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.624341222
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2783016691
Short name T130
Test name
Test status
Simulation time 247939577 ps
CPU time 2.09 seconds
Started Mar 07 01:19:55 PM PST 24
Finished Mar 07 01:19:57 PM PST 24
Peak memory 214680 kb
Host smart-cca3b3ef-de06-440b-9e4d-88b90afc3e1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783016691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2783016691
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3260884208
Short name T2150
Test name
Test status
Simulation time 53557289 ps
CPU time 1.94 seconds
Started Mar 07 01:08:50 PM PST 24
Finished Mar 07 01:08:53 PM PST 24
Peak memory 214724 kb
Host smart-2e5bd3aa-abf2-4767-88d4-07d4de006f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260884208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3260884208
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2118501066
Short name T2097
Test name
Test status
Simulation time 22217124 ps
CPU time 0.7 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 202384 kb
Host smart-d5d39cce-ca22-4b1b-a594-b94ab4b116dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118501066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2118501066
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3195117464
Short name T1981
Test name
Test status
Simulation time 40191314 ps
CPU time 0.69 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 202520 kb
Host smart-85fd6443-0373-4173-ae88-6e68111abcc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195117464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3195117464
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2075182427
Short name T2169
Test name
Test status
Simulation time 148012199 ps
CPU time 3.28 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:56 PM PST 24
Peak memory 214676 kb
Host smart-ca8713c9-9b3e-433d-8c4d-0ee1621d6b84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075182427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2075182427
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.717364968
Short name T2010
Test name
Test status
Simulation time 42604395 ps
CPU time 2.82 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:08:51 PM PST 24
Peak memory 206560 kb
Host smart-ddfaf551-a92a-4a26-bcde-99cba08b4dfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717364968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.717364968
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.223932904
Short name T1961
Test name
Test status
Simulation time 324130039 ps
CPU time 2.36 seconds
Started Mar 07 01:08:44 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 214720 kb
Host smart-384668a2-f674-45bb-99d2-da4099ae9a72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223932904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.223932904
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2829940636
Short name T173
Test name
Test status
Simulation time 398734356 ps
CPU time 12.8 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 215308 kb
Host smart-e7bee120-02ba-40b2-a779-b0df78c5d0a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829940636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2829940636
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3886414747
Short name T2116
Test name
Test status
Simulation time 789784131 ps
CPU time 21.64 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:09:08 PM PST 24
Peak memory 214688 kb
Host smart-11c43877-998a-4126-8625-8f50bc6446a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886414747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3886414747
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2104530257
Short name T2042
Test name
Test status
Simulation time 383006231 ps
CPU time 2.67 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 215876 kb
Host smart-0d18cc72-fb8b-4a93-a4dd-8d3132bd30fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104530257 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2104530257
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.859077991
Short name T2041
Test name
Test status
Simulation time 129368326 ps
CPU time 3.81 seconds
Started Mar 07 01:08:43 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 217620 kb
Host smart-7b08877b-bb01-40d8-b5bb-8ecf2f58ab7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859077991 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.859077991
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.300887209
Short name T135
Test name
Test status
Simulation time 243815823 ps
CPU time 2.03 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 206536 kb
Host smart-5803c9cb-ca38-482d-b1e4-d0fd9cdfc82d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300887209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.300887209
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4248973779
Short name T2012
Test name
Test status
Simulation time 71367935 ps
CPU time 2.53 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 214724 kb
Host smart-8fe540c5-2357-4024-9fa3-7c309bf20bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248973779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4248973779
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3448335857
Short name T1927
Test name
Test status
Simulation time 38493101 ps
CPU time 0.7 seconds
Started Mar 07 01:08:45 PM PST 24
Finished Mar 07 01:08:46 PM PST 24
Peak memory 202576 kb
Host smart-d10afa38-430c-4131-90ec-f9ef5eb0cab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448335857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3448335857
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.632268467
Short name T1925
Test name
Test status
Simulation time 30198309 ps
CPU time 0.7 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:51 PM PST 24
Peak memory 202860 kb
Host smart-9b2a4855-9ec6-4472-9f4c-a5ff869de4ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632268467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.632268467
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2075401385
Short name T1994
Test name
Test status
Simulation time 133293879 ps
CPU time 3.16 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:52 PM PST 24
Peak memory 214712 kb
Host smart-406bbb8c-edc6-4a2e-ae3b-8cfd0e5dd2bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075401385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2075401385
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3299867495
Short name T1969
Test name
Test status
Simulation time 324199620 ps
CPU time 1.98 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 206592 kb
Host smart-e0e8aec7-4faa-458e-a7ad-54b64947743a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299867495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3299867495
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2474595493
Short name T2120
Test name
Test status
Simulation time 38213896 ps
CPU time 2.33 seconds
Started Mar 07 01:08:45 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 214764 kb
Host smart-875db43f-c439-43dc-b65a-47028707a93e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474595493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2474595493
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2677466074
Short name T108
Test name
Test status
Simulation time 44247377 ps
CPU time 1.7 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 214872 kb
Host smart-6342e9ce-db46-45d8-a94a-4a4676cb8272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677466074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2677466074
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1327733909
Short name T2113
Test name
Test status
Simulation time 1026515435 ps
CPU time 19.88 seconds
Started Mar 07 01:19:50 PM PST 24
Finished Mar 07 01:20:10 PM PST 24
Peak memory 214692 kb
Host smart-b7fa4847-96d7-49a5-ade7-67544baab11a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327733909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1327733909
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.993476170
Short name T180
Test name
Test status
Simulation time 3205764735 ps
CPU time 13.02 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:59 PM PST 24
Peak memory 214760 kb
Host smart-ea743667-cc5d-458f-a252-4bb7b43a363f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993476170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.993476170
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1477650193
Short name T2003
Test name
Test status
Simulation time 122516089 ps
CPU time 3.59 seconds
Started Mar 07 01:19:54 PM PST 24
Finished Mar 07 01:19:58 PM PST 24
Peak memory 216188 kb
Host smart-a119cf2e-3873-49fd-a190-4fbd78a81243
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477650193 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1477650193
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3320244037
Short name T2201
Test name
Test status
Simulation time 90685283 ps
CPU time 1.8 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 214868 kb
Host smart-2d5b0e81-02fd-489a-a789-b484dda4d62f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320244037 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3320244037
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3029916166
Short name T2159
Test name
Test status
Simulation time 40902670 ps
CPU time 1.44 seconds
Started Mar 07 01:19:50 PM PST 24
Finished Mar 07 01:19:52 PM PST 24
Peak memory 214668 kb
Host smart-f82e872e-65b5-47a2-a669-19d72544f1ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029916166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3029916166
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3495220519
Short name T137
Test name
Test status
Simulation time 91158041 ps
CPU time 1.34 seconds
Started Mar 07 01:08:45 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 206492 kb
Host smart-ef61d4c3-117f-432a-8381-d84b8ddbc4a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495220519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3495220519
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1021912998
Short name T1950
Test name
Test status
Simulation time 67184871 ps
CPU time 0.76 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 202540 kb
Host smart-b497149c-6a60-4467-a0f3-4f3bfb349698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021912998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1021912998
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2177290528
Short name T1965
Test name
Test status
Simulation time 61028525 ps
CPU time 0.76 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:52 PM PST 24
Peak memory 202592 kb
Host smart-a57f85b4-e67e-4e27-89b7-7e9cc313cc26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177290528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2177290528
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2715545960
Short name T1968
Test name
Test status
Simulation time 47867842 ps
CPU time 1.73 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:50 PM PST 24
Peak memory 214568 kb
Host smart-99643f5f-49a4-4208-8657-f6d47038958a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715545960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2715545960
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.441374821
Short name T1940
Test name
Test status
Simulation time 1206260137 ps
CPU time 3.88 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 214776 kb
Host smart-f9dcb2f9-2a70-419e-befa-c239c742e32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441374821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.441374821
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2794568723
Short name T2153
Test name
Test status
Simulation time 547788706 ps
CPU time 3.68 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:57 PM PST 24
Peak memory 214788 kb
Host smart-c54cdff9-c4c8-48d6-a5a0-fbfa4d1ebd88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794568723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2794568723
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.431618526
Short name T109
Test name
Test status
Simulation time 111487441 ps
CPU time 2.79 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:08:50 PM PST 24
Peak memory 214732 kb
Host smart-4f3cee07-9f16-4f3b-aa96-7212457aa98e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431618526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.431618526
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.19081703
Short name T2015
Test name
Test status
Simulation time 809334208 ps
CPU time 18.96 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:20:10 PM PST 24
Peak memory 214736 kb
Host smart-7067c5cf-2bed-45c9-9949-68eee5a7aa92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19081703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_
tl_intg_err.19081703
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.423926244
Short name T2194
Test name
Test status
Simulation time 2953377527 ps
CPU time 17.38 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:09:05 PM PST 24
Peak memory 222960 kb
Host smart-5d98d820-f53a-47a6-a36a-e2a72e082eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423926244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.423926244
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2400232015
Short name T1995
Test name
Test status
Simulation time 211107613 ps
CPU time 2.94 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 215668 kb
Host smart-8755ae6a-898b-434b-8679-a5a055092b37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400232015 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2400232015
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3161513348
Short name T1982
Test name
Test status
Simulation time 240926106 ps
CPU time 1.84 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 214760 kb
Host smart-b7c8db80-d6b3-4cfe-9e37-bed6ad4b4930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161513348 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3161513348
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2530333837
Short name T2143
Test name
Test status
Simulation time 58863773 ps
CPU time 1.82 seconds
Started Mar 07 01:19:55 PM PST 24
Finished Mar 07 01:19:57 PM PST 24
Peak memory 214744 kb
Host smart-b47c4014-885c-48ab-b5ab-f264bda13286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530333837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2530333837
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.278578668
Short name T2189
Test name
Test status
Simulation time 97368822 ps
CPU time 1.3 seconds
Started Mar 07 01:08:51 PM PST 24
Finished Mar 07 01:08:52 PM PST 24
Peak memory 206436 kb
Host smart-482f3b16-7eb7-4a65-8fc8-f4a4a038fe8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278578668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.278578668
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1507781174
Short name T1991
Test name
Test status
Simulation time 21714422 ps
CPU time 0.71 seconds
Started Mar 07 01:19:55 PM PST 24
Finished Mar 07 01:19:56 PM PST 24
Peak memory 202548 kb
Host smart-ee99f484-4e22-4938-a56b-3851707cca73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507781174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1507781174
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3991326146
Short name T2111
Test name
Test status
Simulation time 17724638 ps
CPU time 0.71 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 202516 kb
Host smart-658cbc5f-94ad-4ca9-aa90-8b687ee50890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991326146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3991326146
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1080857958
Short name T2168
Test name
Test status
Simulation time 230365895 ps
CPU time 3.8 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:57 PM PST 24
Peak memory 214708 kb
Host smart-86f58b1b-f16d-4cd6-b6d3-df8abc12f1c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080857958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1080857958
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1119373969
Short name T2051
Test name
Test status
Simulation time 101971724 ps
CPU time 3.11 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:08:50 PM PST 24
Peak memory 206604 kb
Host smart-5bcc62a5-da1c-4ca9-b8b4-45b4837e23b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119373969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1119373969
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4045875824
Short name T172
Test name
Test status
Simulation time 372005372 ps
CPU time 5.26 seconds
Started Mar 07 01:19:48 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 214808 kb
Host smart-7f9fe5dc-83b8-4ce2-af68-c835dec07471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045875824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4045875824
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.717631052
Short name T2106
Test name
Test status
Simulation time 93358213 ps
CPU time 2.95 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 215760 kb
Host smart-7fb1fb86-00ee-4676-b4cd-56578684ce7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717631052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.717631052
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.146184807
Short name T181
Test name
Test status
Simulation time 1014186445 ps
CPU time 20.28 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:09:08 PM PST 24
Peak memory 214756 kb
Host smart-f27f0731-8106-4cfd-926b-d07c5741dce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146184807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.146184807
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3457734124
Short name T104
Test name
Test status
Simulation time 302741250 ps
CPU time 18.57 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:20:10 PM PST 24
Peak memory 214660 kb
Host smart-3cc04c98-a6ff-4317-82bf-d9efffbd196b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457734124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3457734124
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1245825480
Short name T2066
Test name
Test status
Simulation time 370095601 ps
CPU time 2.63 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 214816 kb
Host smart-3e6f212a-8af3-494d-8aa7-0ecf4e06401b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245825480 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1245825480
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.629394870
Short name T2203
Test name
Test status
Simulation time 619823049 ps
CPU time 3.52 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:08:50 PM PST 24
Peak memory 216200 kb
Host smart-3c15128b-528d-47c1-8898-04623905400a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629394870 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.629394870
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3002133122
Short name T128
Test name
Test status
Simulation time 19436982 ps
CPU time 1.31 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 214736 kb
Host smart-f509923f-e0cb-4244-b6cc-4aa4720d20d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002133122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3002133122
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3628311624
Short name T2178
Test name
Test status
Simulation time 38711369 ps
CPU time 2.45 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:52 PM PST 24
Peak memory 214684 kb
Host smart-25872218-691d-4b16-a479-9370efd22fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628311624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3628311624
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3481856935
Short name T1923
Test name
Test status
Simulation time 208575623 ps
CPU time 0.77 seconds
Started Mar 07 01:08:44 PM PST 24
Finished Mar 07 01:08:45 PM PST 24
Peak memory 202836 kb
Host smart-4b14db56-7c72-4d58-a401-3ec2559498ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481856935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3481856935
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.570604371
Short name T1932
Test name
Test status
Simulation time 15138293 ps
CPU time 0.73 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 202532 kb
Host smart-5b574a93-971f-48a3-b28a-6993ae7852dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570604371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.570604371
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2366198858
Short name T2073
Test name
Test status
Simulation time 160941422 ps
CPU time 4.35 seconds
Started Mar 07 01:19:50 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 214404 kb
Host smart-129550ef-345b-474d-8b54-4c8e55047428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366198858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2366198858
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3667745889
Short name T2055
Test name
Test status
Simulation time 190367188 ps
CPU time 1.97 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:50 PM PST 24
Peak memory 214824 kb
Host smart-31fd1cea-56da-4ac0-a49b-68493e95f261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667745889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3667745889
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2775650206
Short name T2199
Test name
Test status
Simulation time 75064172 ps
CPU time 1.62 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 214832 kb
Host smart-4f31719b-bac9-4727-af34-dbacff6fa811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775650206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2775650206
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.408477873
Short name T2038
Test name
Test status
Simulation time 265781299 ps
CPU time 3.33 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 214768 kb
Host smart-df8e9648-1cec-462f-855a-e92683b7229b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408477873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.408477873
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2684659970
Short name T2103
Test name
Test status
Simulation time 3711361151 ps
CPU time 20.64 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:09:06 PM PST 24
Peak memory 214784 kb
Host smart-733b9b3f-88b3-4613-a1ef-6efbf95fd71d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684659970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2684659970
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3490885695
Short name T183
Test name
Test status
Simulation time 665848910 ps
CPU time 6.32 seconds
Started Mar 07 01:19:50 PM PST 24
Finished Mar 07 01:19:57 PM PST 24
Peak memory 214772 kb
Host smart-2563dc3f-75e4-45c1-ba2f-53191ad1ee3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490885695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3490885695
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2618430978
Short name T2034
Test name
Test status
Simulation time 42854551 ps
CPU time 1.56 seconds
Started Mar 07 01:08:51 PM PST 24
Finished Mar 07 01:08:53 PM PST 24
Peak memory 214732 kb
Host smart-b8f8eb37-17fb-4db5-abc0-eedaeddcae91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618430978 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2618430978
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.783093261
Short name T2183
Test name
Test status
Simulation time 144955193 ps
CPU time 2.55 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 214716 kb
Host smart-8103e458-2fdf-4ebb-b8b0-4ca08615a950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783093261 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.783093261
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2692096667
Short name T2033
Test name
Test status
Simulation time 375648715 ps
CPU time 2.78 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 214660 kb
Host smart-c9651f6d-14a0-48e6-ab5c-f859e1f1c11d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692096667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2692096667
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.317750803
Short name T2060
Test name
Test status
Simulation time 67481534 ps
CPU time 2.15 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:51 PM PST 24
Peak memory 214756 kb
Host smart-8922385c-adde-47d9-bc7f-1428560c4304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317750803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.317750803
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2927520163
Short name T1942
Test name
Test status
Simulation time 14894850 ps
CPU time 0.71 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 202844 kb
Host smart-97db6f89-db5e-429a-9f7b-c66cf6c622d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927520163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2927520163
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.784042290
Short name T2180
Test name
Test status
Simulation time 15377686 ps
CPU time 0.76 seconds
Started Mar 07 01:08:45 PM PST 24
Finished Mar 07 01:08:46 PM PST 24
Peak memory 202532 kb
Host smart-277ebfae-d277-4b56-97f2-cd0e9561809a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784042290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.784042290
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1582425497
Short name T2035
Test name
Test status
Simulation time 287246521 ps
CPU time 1.76 seconds
Started Mar 07 01:08:44 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 206480 kb
Host smart-0ab4ddad-5514-489e-ab55-623d58b0fb46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582425497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1582425497
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4014792411
Short name T2135
Test name
Test status
Simulation time 220771466 ps
CPU time 1.82 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 206608 kb
Host smart-8d2e265a-148a-48a7-9900-16b67d2dd5d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014792411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4014792411
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1829514820
Short name T105
Test name
Test status
Simulation time 45777336 ps
CPU time 3.2 seconds
Started Mar 07 01:08:44 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 214740 kb
Host smart-1f3c25ac-28c2-41a8-82d8-dba29862e842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829514820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1829514820
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.502354932
Short name T2054
Test name
Test status
Simulation time 281460203 ps
CPU time 1.92 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 214740 kb
Host smart-29af7f91-c16a-465a-96b4-20ec592ffa0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502354932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.502354932
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3948152685
Short name T2072
Test name
Test status
Simulation time 1510967513 ps
CPU time 19.51 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:20:12 PM PST 24
Peak memory 214876 kb
Host smart-04faa8cf-5a50-4e45-8559-8814d258d2ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948152685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3948152685
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4019802542
Short name T2186
Test name
Test status
Simulation time 392498041 ps
CPU time 9.31 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:59 PM PST 24
Peak memory 214708 kb
Host smart-bd6f1b56-b05c-46ef-b209-fd0a8d90f3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019802542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4019802542
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1359163132
Short name T1971
Test name
Test status
Simulation time 101386584 ps
CPU time 1.74 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 214772 kb
Host smart-d2a0de90-ac4c-404e-9b12-08f9b492dcf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359163132 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1359163132
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2999389856
Short name T1986
Test name
Test status
Simulation time 918748601 ps
CPU time 3.22 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:57 PM PST 24
Peak memory 215784 kb
Host smart-f9830f8e-d2bb-43cf-8656-e606e3ae86ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999389856 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2999389856
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2593775837
Short name T1935
Test name
Test status
Simulation time 44139244 ps
CPU time 1.46 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 206468 kb
Host smart-4b17db62-ceed-4614-84fe-8eea40b98e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593775837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2593775837
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3218196268
Short name T2197
Test name
Test status
Simulation time 161404214 ps
CPU time 2.26 seconds
Started Mar 07 01:08:53 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 206376 kb
Host smart-0ba56cf0-152e-4016-91bc-b18bd1075f51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218196268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3218196268
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2141242316
Short name T1964
Test name
Test status
Simulation time 34354274 ps
CPU time 0.66 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 202856 kb
Host smart-0897f26d-0342-4eb5-b3e9-d274d82dbc32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141242316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2141242316
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3685787922
Short name T2079
Test name
Test status
Simulation time 12744047 ps
CPU time 0.88 seconds
Started Mar 07 01:19:48 PM PST 24
Finished Mar 07 01:19:49 PM PST 24
Peak memory 202876 kb
Host smart-04208765-8269-43c0-bd68-9b1c5f168710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685787922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3685787922
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.15284485
Short name T2025
Test name
Test status
Simulation time 166795844 ps
CPU time 4.67 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:57 PM PST 24
Peak memory 206468 kb
Host smart-7f0596c1-1ba6-4855-b55a-2d2a2a9dc6ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15284485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sp
i_device_same_csr_outstanding.15284485
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.665052010
Short name T1921
Test name
Test status
Simulation time 322505161 ps
CPU time 3.9 seconds
Started Mar 07 01:08:50 PM PST 24
Finished Mar 07 01:08:55 PM PST 24
Peak memory 214468 kb
Host smart-6e5586f1-79f3-4371-be35-cec6324a957d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665052010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.665052010
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2896251951
Short name T118
Test name
Test status
Simulation time 274217481 ps
CPU time 3.84 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:56 PM PST 24
Peak memory 214864 kb
Host smart-33cbe4bf-ca39-4cad-b43e-bb5629b80745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896251951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2896251951
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.762143188
Short name T2023
Test name
Test status
Simulation time 34697067 ps
CPU time 1.26 seconds
Started Mar 07 01:08:45 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 214964 kb
Host smart-267a7cf8-f6d4-433a-978a-c50e7f3fa73f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762143188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.762143188
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1107830994
Short name T2114
Test name
Test status
Simulation time 350488661 ps
CPU time 7.93 seconds
Started Mar 07 01:08:49 PM PST 24
Finished Mar 07 01:08:57 PM PST 24
Peak memory 214680 kb
Host smart-5b10977c-5e93-4147-80eb-fea3b3886238
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107830994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1107830994
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1150561848
Short name T2160
Test name
Test status
Simulation time 223798967 ps
CPU time 7.85 seconds
Started Mar 07 01:19:30 PM PST 24
Finished Mar 07 01:19:38 PM PST 24
Peak memory 206472 kb
Host smart-058d271c-d1ca-4b0a-a7b0-4aa691568779
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150561848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1150561848
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.674697915
Short name T2147
Test name
Test status
Simulation time 376465800 ps
CPU time 8.83 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:40 PM PST 24
Peak memory 206524 kb
Host smart-c22db10f-9b1e-4727-a500-4c5bd3022fae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674697915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.674697915
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1763204927
Short name T2146
Test name
Test status
Simulation time 1566044735 ps
CPU time 25.64 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:58 PM PST 24
Peak memory 206192 kb
Host smart-314800a3-9485-43b4-946c-3bf3e05e3bbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763204927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1763204927
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3388184439
Short name T1976
Test name
Test status
Simulation time 1275950056 ps
CPU time 23.62 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:20:02 PM PST 24
Peak memory 206504 kb
Host smart-9b62ea3e-f3cc-41eb-9e0e-e9850a52987c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388184439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3388184439
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2528145233
Short name T2179
Test name
Test status
Simulation time 180777436 ps
CPU time 1.35 seconds
Started Mar 07 01:08:28 PM PST 24
Finished Mar 07 01:08:29 PM PST 24
Peak memory 206480 kb
Host smart-14752da7-8c1c-4af8-a63c-6bfc4ae2baaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528145233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2528145233
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3286575794
Short name T88
Test name
Test status
Simulation time 74077169 ps
CPU time 1.28 seconds
Started Mar 07 01:19:27 PM PST 24
Finished Mar 07 01:19:28 PM PST 24
Peak memory 215744 kb
Host smart-fce2a699-6e8f-48a7-ace5-359b830ccd9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286575794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3286575794
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1209242964
Short name T2007
Test name
Test status
Simulation time 175996645 ps
CPU time 4.11 seconds
Started Mar 07 01:08:34 PM PST 24
Finished Mar 07 01:08:38 PM PST 24
Peak memory 216064 kb
Host smart-bd45ed77-5222-4a8b-b86e-3cb5225a2a6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209242964 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1209242964
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.378497426
Short name T1958
Test name
Test status
Simulation time 111991843 ps
CPU time 2.67 seconds
Started Mar 07 01:19:32 PM PST 24
Finished Mar 07 01:19:34 PM PST 24
Peak memory 214748 kb
Host smart-cdb19bc6-66a8-4612-ba8b-0e035d864826
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378497426 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.378497426
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1432792333
Short name T150
Test name
Test status
Simulation time 290960916 ps
CPU time 1.35 seconds
Started Mar 07 01:19:31 PM PST 24
Finished Mar 07 01:19:32 PM PST 24
Peak memory 206548 kb
Host smart-ff2c909b-d379-4994-990e-1c664218de49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432792333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
432792333
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2815220971
Short name T2086
Test name
Test status
Simulation time 38887952 ps
CPU time 2.46 seconds
Started Mar 07 01:08:34 PM PST 24
Finished Mar 07 01:08:37 PM PST 24
Peak memory 206424 kb
Host smart-d1b1bd22-7d5b-4b18-a5c2-86f2052b4f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815220971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
815220971
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2370349791
Short name T2105
Test name
Test status
Simulation time 15119898 ps
CPU time 0.79 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:41 PM PST 24
Peak memory 202592 kb
Host smart-a457eb6d-de30-46a6-97c4-3fd3e49c95b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370349791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
370349791
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2527636374
Short name T2127
Test name
Test status
Simulation time 14580831 ps
CPU time 0.72 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 202512 kb
Host smart-31d8d6cc-2ade-4ad5-87cb-a5716811bbcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527636374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
527636374
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1254888957
Short name T2128
Test name
Test status
Simulation time 31227607 ps
CPU time 1.32 seconds
Started Mar 07 01:08:29 PM PST 24
Finished Mar 07 01:08:30 PM PST 24
Peak memory 214600 kb
Host smart-58f79485-ea05-4315-913e-d70278bd6c1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254888957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1254888957
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2494792835
Short name T2044
Test name
Test status
Simulation time 148549523 ps
CPU time 2.25 seconds
Started Mar 07 01:19:30 PM PST 24
Finished Mar 07 01:19:32 PM PST 24
Peak memory 214604 kb
Host smart-cc720952-072a-489e-9881-2b3fae4059e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494792835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2494792835
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1813420352
Short name T2132
Test name
Test status
Simulation time 11408385 ps
CPU time 0.65 seconds
Started Mar 07 01:08:34 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 202736 kb
Host smart-973a4ff0-1bc7-4fb6-bf4c-9839004be834
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813420352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1813420352
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2454675585
Short name T2082
Test name
Test status
Simulation time 14154001 ps
CPU time 0.69 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:19:39 PM PST 24
Peak memory 202804 kb
Host smart-2bbf6543-c82d-494a-907d-7b8f5a719a05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454675585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2454675585
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1487583243
Short name T2119
Test name
Test status
Simulation time 1486836239 ps
CPU time 4.69 seconds
Started Mar 07 01:19:37 PM PST 24
Finished Mar 07 01:19:42 PM PST 24
Peak memory 214492 kb
Host smart-2ac422b2-d8b5-4b72-b900-118427759777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487583243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1487583243
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2627819608
Short name T1992
Test name
Test status
Simulation time 74471719 ps
CPU time 1.96 seconds
Started Mar 07 01:08:29 PM PST 24
Finished Mar 07 01:08:32 PM PST 24
Peak memory 206036 kb
Host smart-f0ce5c99-a130-4639-9f31-034dd9551fbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627819608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2627819608
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.169875303
Short name T121
Test name
Test status
Simulation time 473341624 ps
CPU time 3.64 seconds
Started Mar 07 01:19:29 PM PST 24
Finished Mar 07 01:19:33 PM PST 24
Peak memory 214836 kb
Host smart-c0abe494-8835-408a-a380-9cbd7e88f501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169875303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.169875303
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2619685546
Short name T171
Test name
Test status
Simulation time 491004173 ps
CPU time 4.05 seconds
Started Mar 07 01:08:35 PM PST 24
Finished Mar 07 01:08:39 PM PST 24
Peak memory 214788 kb
Host smart-594c932a-293b-4b42-954b-cf1e10722faa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619685546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
619685546
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3237633900
Short name T2181
Test name
Test status
Simulation time 143067214 ps
CPU time 7.11 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:19:45 PM PST 24
Peak memory 214712 kb
Host smart-9c5650f6-66d8-408c-a93c-c591f5eb9659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237633900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3237633900
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.558638816
Short name T2107
Test name
Test status
Simulation time 1175227928 ps
CPU time 7.75 seconds
Started Mar 07 01:08:34 PM PST 24
Finished Mar 07 01:08:42 PM PST 24
Peak memory 214688 kb
Host smart-6c3f6865-ec47-47b4-b519-a6ec0fbe7c6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558638816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.558638816
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1284173341
Short name T2136
Test name
Test status
Simulation time 34270523 ps
CPU time 0.7 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 202868 kb
Host smart-d5c1a138-293e-4dd9-91d7-a985cdd12164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284173341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1284173341
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2001241384
Short name T2131
Test name
Test status
Simulation time 34371595 ps
CPU time 0.78 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 202416 kb
Host smart-bd02f781-8206-44af-ae0b-d13cd4b41cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001241384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2001241384
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2944957239
Short name T2077
Test name
Test status
Simulation time 14068593 ps
CPU time 0.73 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 202516 kb
Host smart-8a684554-e5c3-46d9-93d6-f2f8353f9797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944957239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2944957239
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.908556693
Short name T2009
Test name
Test status
Simulation time 51741105 ps
CPU time 0.78 seconds
Started Mar 07 01:08:46 PM PST 24
Finished Mar 07 01:08:47 PM PST 24
Peak memory 202676 kb
Host smart-af9d81f0-7158-4886-9675-c7e45dd93044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908556693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.908556693
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2051760073
Short name T1918
Test name
Test status
Simulation time 14695346 ps
CPU time 0.72 seconds
Started Mar 07 01:08:45 PM PST 24
Finished Mar 07 01:08:46 PM PST 24
Peak memory 202552 kb
Host smart-bf87f4f4-7ae4-441c-b776-e3d5ef1d80e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051760073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2051760073
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.988777464
Short name T2167
Test name
Test status
Simulation time 12361765 ps
CPU time 0.77 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 202580 kb
Host smart-d516f638-d57f-4e9d-9935-1dd196948eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988777464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.988777464
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1573296959
Short name T2122
Test name
Test status
Simulation time 43770825 ps
CPU time 0.72 seconds
Started Mar 07 01:08:52 PM PST 24
Finished Mar 07 01:08:53 PM PST 24
Peak memory 202536 kb
Host smart-0532c095-c6c9-4fcc-b831-9c2a6600ba1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573296959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1573296959
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.17978172
Short name T2125
Test name
Test status
Simulation time 25228251 ps
CPU time 0.67 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:52 PM PST 24
Peak memory 202456 kb
Host smart-feaa5195-63d3-4372-9219-21003c05ad0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17978172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.17978172
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1714722622
Short name T1931
Test name
Test status
Simulation time 14630599 ps
CPU time 0.7 seconds
Started Mar 07 01:08:53 PM PST 24
Finished Mar 07 01:08:54 PM PST 24
Peak memory 202464 kb
Host smart-43ee4dd5-264e-4324-973e-6c5250ff30b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714722622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1714722622
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2051841884
Short name T2095
Test name
Test status
Simulation time 50179886 ps
CPU time 0.73 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 202816 kb
Host smart-c63aff90-5d01-4b43-8d2f-f87685a2f8ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051841884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2051841884
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2512085881
Short name T2200
Test name
Test status
Simulation time 23711587 ps
CPU time 0.73 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 202520 kb
Host smart-4265eddb-6225-41e6-a004-986b54fc7002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512085881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2512085881
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.823227967
Short name T1966
Test name
Test status
Simulation time 12071944 ps
CPU time 0.69 seconds
Started Mar 07 01:19:54 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 202512 kb
Host smart-c37452d3-2081-49c5-8353-b9bd9acf5977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823227967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.823227967
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1531800446
Short name T2017
Test name
Test status
Simulation time 45598657 ps
CPU time 0.72 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 202540 kb
Host smart-7cb51706-4eec-4382-889d-47202a14e4dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531800446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1531800446
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2365114016
Short name T2037
Test name
Test status
Simulation time 15288597 ps
CPU time 0.72 seconds
Started Mar 07 01:08:53 PM PST 24
Finished Mar 07 01:08:54 PM PST 24
Peak memory 202456 kb
Host smart-0e5c67ce-f6e2-4f43-b5df-56ad2caa2700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365114016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2365114016
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1116114703
Short name T2052
Test name
Test status
Simulation time 35648549 ps
CPU time 0.77 seconds
Started Mar 07 01:08:53 PM PST 24
Finished Mar 07 01:08:54 PM PST 24
Peak memory 202516 kb
Host smart-9b9d6278-0d5c-4054-b770-77d2276d0741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116114703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1116114703
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2046938866
Short name T1985
Test name
Test status
Simulation time 24280199 ps
CPU time 0.75 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 202564 kb
Host smart-59061000-5b0e-49a2-ba9d-69879fe4166b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046938866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2046938866
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1249938460
Short name T2014
Test name
Test status
Simulation time 78290752 ps
CPU time 0.76 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 202576 kb
Host smart-381727a3-958e-4f51-8535-d8f8e08d6984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249938460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1249938460
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.60690611
Short name T2188
Test name
Test status
Simulation time 45801730 ps
CPU time 0.69 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 202512 kb
Host smart-a2506088-350c-4fe1-b5cf-fe3c018794f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60690611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.60690611
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2023132266
Short name T1948
Test name
Test status
Simulation time 19932940 ps
CPU time 0.78 seconds
Started Mar 07 01:08:48 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 202616 kb
Host smart-c57e2375-f03d-429a-b23d-e913bfe39aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023132266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2023132266
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3136519856
Short name T2110
Test name
Test status
Simulation time 38689663 ps
CPU time 0.72 seconds
Started Mar 07 01:19:55 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 202472 kb
Host smart-05d5e8c0-d2a9-482b-aabe-8c044286cce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136519856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3136519856
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1246424851
Short name T2140
Test name
Test status
Simulation time 4299377081 ps
CPU time 24.72 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 206492 kb
Host smart-16a5ebff-8c3e-41e0-a50d-9ccb8509136d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246424851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1246424851
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3895834410
Short name T2087
Test name
Test status
Simulation time 672672457 ps
CPU time 16.61 seconds
Started Mar 07 01:19:32 PM PST 24
Finished Mar 07 01:19:49 PM PST 24
Peak memory 206528 kb
Host smart-ce9b22f2-46e9-464f-a014-f8c038524754
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895834410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3895834410
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1631030168
Short name T2139
Test name
Test status
Simulation time 2705793608 ps
CPU time 38.87 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:09:09 PM PST 24
Peak memory 206276 kb
Host smart-9dc2c2ec-217c-48f9-96f9-7280bdc95166
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631030168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1631030168
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2831199839
Short name T2008
Test name
Test status
Simulation time 183534011 ps
CPU time 12.75 seconds
Started Mar 07 01:19:36 PM PST 24
Finished Mar 07 01:19:49 PM PST 24
Peak memory 206540 kb
Host smart-39b16317-55f5-4f71-9773-78d818a0bc60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831199839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2831199839
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1998812498
Short name T2061
Test name
Test status
Simulation time 26329606 ps
CPU time 0.96 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:19:40 PM PST 24
Peak memory 206336 kb
Host smart-0552fc72-3d81-4ff0-b304-9b9a7cc2e22e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998812498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1998812498
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3139674200
Short name T2202
Test name
Test status
Simulation time 38524627 ps
CPU time 1.01 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:34 PM PST 24
Peak memory 205852 kb
Host smart-812fd39f-2fb4-4fdc-8448-645093cdf1df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139674200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3139674200
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1480895789
Short name T2166
Test name
Test status
Simulation time 151045698 ps
CPU time 3.88 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 215868 kb
Host smart-97041689-25b7-46b7-9bef-8ae30b47ee37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480895789 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1480895789
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3049724157
Short name T1990
Test name
Test status
Simulation time 456608290 ps
CPU time 3.52 seconds
Started Mar 07 01:19:47 PM PST 24
Finished Mar 07 01:19:51 PM PST 24
Peak memory 215884 kb
Host smart-8a210574-179a-484a-8b3d-50049a09a986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049724157 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3049724157
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1096497054
Short name T2083
Test name
Test status
Simulation time 19813513 ps
CPU time 1.33 seconds
Started Mar 07 01:19:31 PM PST 24
Finished Mar 07 01:19:32 PM PST 24
Peak memory 206544 kb
Host smart-2df18ec2-a178-497f-a39a-38ba567cacfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096497054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
096497054
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4293413856
Short name T2001
Test name
Test status
Simulation time 83403574 ps
CPU time 2.58 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 214748 kb
Host smart-dd90d0b5-a0d2-4061-90d2-ae373f79e3a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293413856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
293413856
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.301388391
Short name T2156
Test name
Test status
Simulation time 29768030 ps
CPU time 0.68 seconds
Started Mar 07 01:19:31 PM PST 24
Finished Mar 07 01:19:32 PM PST 24
Peak memory 202872 kb
Host smart-cfcf83b2-59e2-439f-9625-d802701b40ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301388391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.301388391
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.505508612
Short name T2205
Test name
Test status
Simulation time 24791044 ps
CPU time 0.8 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:31 PM PST 24
Peak memory 202596 kb
Host smart-051b0d1c-84ce-4772-93ce-caeeff2d682c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505508612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.505508612
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1547623949
Short name T134
Test name
Test status
Simulation time 158670709 ps
CPU time 1.34 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:32 PM PST 24
Peak memory 214632 kb
Host smart-a53bc03b-2176-4663-8758-18ef9cd98567
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547623949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1547623949
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3029456202
Short name T2019
Test name
Test status
Simulation time 69472642 ps
CPU time 2.23 seconds
Started Mar 07 01:19:31 PM PST 24
Finished Mar 07 01:19:33 PM PST 24
Peak memory 214628 kb
Host smart-171e1820-0648-4be9-b847-ece5eb6bd1ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029456202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3029456202
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1965516475
Short name T2098
Test name
Test status
Simulation time 33736946 ps
CPU time 0.65 seconds
Started Mar 07 01:19:32 PM PST 24
Finished Mar 07 01:19:32 PM PST 24
Peak memory 202452 kb
Host smart-6e12e9f2-15c1-485a-bfed-ecbd227ea5b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965516475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1965516475
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4151357842
Short name T1983
Test name
Test status
Simulation time 39877107 ps
CPU time 0.68 seconds
Started Mar 07 01:08:29 PM PST 24
Finished Mar 07 01:08:30 PM PST 24
Peak memory 202416 kb
Host smart-63dfde68-740b-4fcc-ac92-6e23a78f05d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151357842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4151357842
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3073636429
Short name T2117
Test name
Test status
Simulation time 604154344 ps
CPU time 3.2 seconds
Started Mar 07 01:08:28 PM PST 24
Finished Mar 07 01:08:32 PM PST 24
Peak memory 214304 kb
Host smart-bf3e5b78-f9f5-4b54-baee-9f88f8645628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073636429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3073636429
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.734001086
Short name T1977
Test name
Test status
Simulation time 29501492 ps
CPU time 1.96 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:19:40 PM PST 24
Peak memory 206348 kb
Host smart-61583ee9-125d-4f13-a41f-0dc1594b0b62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734001086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.734001086
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1007435827
Short name T2064
Test name
Test status
Simulation time 61698358 ps
CPU time 4.61 seconds
Started Mar 07 01:19:32 PM PST 24
Finished Mar 07 01:19:37 PM PST 24
Peak memory 214744 kb
Host smart-de0b4955-24c0-4ea0-a749-acdf5ad5f554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007435827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
007435827
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.347658817
Short name T2193
Test name
Test status
Simulation time 75023806 ps
CPU time 1.66 seconds
Started Mar 07 01:08:28 PM PST 24
Finished Mar 07 01:08:30 PM PST 24
Peak memory 214804 kb
Host smart-59dd31f8-78fe-487d-95b9-57f87685a503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347658817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.347658817
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1054796923
Short name T2068
Test name
Test status
Simulation time 690307575 ps
CPU time 13.95 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 214752 kb
Host smart-c3201cad-c148-4345-9e57-7d44e382c83f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054796923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1054796923
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.106022650
Short name T2074
Test name
Test status
Simulation time 1130362219 ps
CPU time 7.22 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:39 PM PST 24
Peak memory 214672 kb
Host smart-4b5555f2-a1b3-402b-a09f-c38ea83254bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106022650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.106022650
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2918351564
Short name T1998
Test name
Test status
Simulation time 13153089 ps
CPU time 0.71 seconds
Started Mar 07 01:08:51 PM PST 24
Finished Mar 07 01:08:51 PM PST 24
Peak memory 202504 kb
Host smart-1892182f-4860-4d08-93ac-75de6dc7dbf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918351564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2918351564
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3679715645
Short name T1978
Test name
Test status
Simulation time 48313626 ps
CPU time 0.67 seconds
Started Mar 07 01:19:54 PM PST 24
Finished Mar 07 01:19:55 PM PST 24
Peak memory 202480 kb
Host smart-c3b0e8f1-b99a-43ac-9d9b-ac7a622d13ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679715645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3679715645
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3054059509
Short name T1952
Test name
Test status
Simulation time 39400081 ps
CPU time 0.79 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 202844 kb
Host smart-4c37459f-da95-4e02-a4ac-ba8a5bc1b2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054059509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3054059509
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.958896416
Short name T2176
Test name
Test status
Simulation time 39069699 ps
CPU time 0.76 seconds
Started Mar 07 01:19:52 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 202552 kb
Host smart-ed574dd6-adbc-4f87-a861-dd98deb337f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958896416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.958896416
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2274181482
Short name T1937
Test name
Test status
Simulation time 22126092 ps
CPU time 0.7 seconds
Started Mar 07 01:19:55 PM PST 24
Finished Mar 07 01:19:56 PM PST 24
Peak memory 202496 kb
Host smart-6900bce2-52a8-4b74-8fe5-45240de6603b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274181482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2274181482
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4216913517
Short name T2192
Test name
Test status
Simulation time 29096974 ps
CPU time 0.78 seconds
Started Mar 07 01:08:47 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 202536 kb
Host smart-a02864f4-2826-4c71-a768-31f7810c2d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216913517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4216913517
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1062300738
Short name T2032
Test name
Test status
Simulation time 26189509 ps
CPU time 0.72 seconds
Started Mar 07 01:08:59 PM PST 24
Finished Mar 07 01:09:01 PM PST 24
Peak memory 202536 kb
Host smart-54fc1f09-4fbc-4085-be87-6c087597018b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062300738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1062300738
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1760296488
Short name T2208
Test name
Test status
Simulation time 34816306 ps
CPU time 0.71 seconds
Started Mar 07 01:19:51 PM PST 24
Finished Mar 07 01:19:52 PM PST 24
Peak memory 202500 kb
Host smart-b86987ca-b5bd-4a2a-8c72-9eeb91a83a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760296488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1760296488
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1636148172
Short name T2075
Test name
Test status
Simulation time 40883057 ps
CPU time 0.71 seconds
Started Mar 07 01:19:53 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 202464 kb
Host smart-e7756237-24ab-4a94-854b-e81952bcf338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636148172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1636148172
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1810606923
Short name T1945
Test name
Test status
Simulation time 21378672 ps
CPU time 0.75 seconds
Started Mar 07 01:08:55 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 202588 kb
Host smart-43127596-e17e-4d2c-b05d-31a2f0ffc97c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810606923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1810606923
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1424889497
Short name T1960
Test name
Test status
Simulation time 62452977 ps
CPU time 0.68 seconds
Started Mar 07 01:08:57 PM PST 24
Finished Mar 07 01:08:58 PM PST 24
Peak memory 202732 kb
Host smart-7dec5388-7d65-47a9-abd9-e14ceec226a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424889497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1424889497
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3991452106
Short name T1962
Test name
Test status
Simulation time 35672278 ps
CPU time 0.76 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:03 PM PST 24
Peak memory 202524 kb
Host smart-73f68a1f-3213-437d-b83d-048b5260d3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991452106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3991452106
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1880161336
Short name T2144
Test name
Test status
Simulation time 139894151 ps
CPU time 0.82 seconds
Started Mar 07 01:08:56 PM PST 24
Finished Mar 07 01:08:57 PM PST 24
Peak memory 202580 kb
Host smart-94529f69-dcf3-41ad-a2f7-1fd8fca964b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880161336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1880161336
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.269093959
Short name T2138
Test name
Test status
Simulation time 33595131 ps
CPU time 0.69 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:03 PM PST 24
Peak memory 202884 kb
Host smart-4420543c-ae56-41da-931b-9a527b16ff9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269093959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.269093959
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1393241533
Short name T2027
Test name
Test status
Simulation time 21355014 ps
CPU time 0.81 seconds
Started Mar 07 01:08:54 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 202572 kb
Host smart-e8467169-f8fc-4a96-95b3-652fa08296ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393241533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1393241533
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2822946490
Short name T1930
Test name
Test status
Simulation time 27387805 ps
CPU time 0.73 seconds
Started Mar 07 01:20:01 PM PST 24
Finished Mar 07 01:20:02 PM PST 24
Peak memory 202588 kb
Host smart-38d656c5-36af-4dff-923f-118878ec5507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822946490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2822946490
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.250068303
Short name T1951
Test name
Test status
Simulation time 57804302 ps
CPU time 0.7 seconds
Started Mar 07 01:08:55 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 202516 kb
Host smart-8518cd16-415b-44fa-a469-5be67dde6ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250068303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.250068303
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4201242283
Short name T2022
Test name
Test status
Simulation time 68153678 ps
CPU time 0.74 seconds
Started Mar 07 01:20:03 PM PST 24
Finished Mar 07 01:20:04 PM PST 24
Peak memory 202800 kb
Host smart-78af7dbe-4df8-431b-b2e9-56d57ff030a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201242283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4201242283
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3439596429
Short name T1943
Test name
Test status
Simulation time 12266006 ps
CPU time 0.74 seconds
Started Mar 07 01:08:59 PM PST 24
Finished Mar 07 01:09:00 PM PST 24
Peak memory 202460 kb
Host smart-93ff7bea-d587-4a5a-a3a6-03654a324901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439596429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3439596429
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4285541004
Short name T2092
Test name
Test status
Simulation time 129813371 ps
CPU time 0.82 seconds
Started Mar 07 01:20:03 PM PST 24
Finished Mar 07 01:20:05 PM PST 24
Peak memory 202504 kb
Host smart-e7da87f6-3028-4d05-90c7-58957d77f8a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285541004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4285541004
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.113630307
Short name T2094
Test name
Test status
Simulation time 467672235 ps
CPU time 7.6 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:40 PM PST 24
Peak memory 206456 kb
Host smart-d9b90a42-10f6-4dd5-8a0a-9bc08de2a468
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113630307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.113630307
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2893666035
Short name T2195
Test name
Test status
Simulation time 320225589 ps
CPU time 8.2 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:47 PM PST 24
Peak memory 214656 kb
Host smart-645f4c4e-9405-4f97-9e5d-c2b3af397f6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893666035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2893666035
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3487448405
Short name T2177
Test name
Test status
Simulation time 989072418 ps
CPU time 12.39 seconds
Started Mar 07 01:19:32 PM PST 24
Finished Mar 07 01:19:45 PM PST 24
Peak memory 206092 kb
Host smart-66d4a9cd-94c5-4ba7-bdd4-8892ee123e49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487448405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3487448405
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.835112830
Short name T2165
Test name
Test status
Simulation time 1934683678 ps
CPU time 29.88 seconds
Started Mar 07 01:08:35 PM PST 24
Finished Mar 07 01:09:05 PM PST 24
Peak memory 206488 kb
Host smart-ec6de54a-2e88-4883-8cab-af9729d2017d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835112830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.835112830
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.139087486
Short name T2170
Test name
Test status
Simulation time 24042385 ps
CPU time 1.34 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 206424 kb
Host smart-02b0863c-2169-4043-9675-d506012c9673
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139087486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.139087486
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.478373277
Short name T2036
Test name
Test status
Simulation time 81571683 ps
CPU time 1.01 seconds
Started Mar 07 01:19:32 PM PST 24
Finished Mar 07 01:19:33 PM PST 24
Peak memory 206192 kb
Host smart-4b1b84d2-7934-470d-a2c6-e7a0ca05af9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478373277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.478373277
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2572910949
Short name T116
Test name
Test status
Simulation time 97109615 ps
CPU time 2.78 seconds
Started Mar 07 01:08:35 PM PST 24
Finished Mar 07 01:08:39 PM PST 24
Peak memory 215784 kb
Host smart-71976742-9792-4ebc-84f6-320e01e3e6e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572910949 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2572910949
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.696226035
Short name T2024
Test name
Test status
Simulation time 164891784 ps
CPU time 3.43 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:42 PM PST 24
Peak memory 216132 kb
Host smart-92fe2708-68fe-4a76-9cab-b98a825079bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696226035 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.696226035
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2952916746
Short name T1955
Test name
Test status
Simulation time 21375804 ps
CPU time 1.26 seconds
Started Mar 07 01:08:35 PM PST 24
Finished Mar 07 01:08:38 PM PST 24
Peak memory 214696 kb
Host smart-3cc0b05f-9fcb-450c-aa79-7d124a92f3ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952916746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
952916746
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3515926334
Short name T1947
Test name
Test status
Simulation time 61970226 ps
CPU time 2.53 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:19:41 PM PST 24
Peak memory 214744 kb
Host smart-ee8b46d2-b6bf-4d4c-92d6-a607f62cfbd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515926334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
515926334
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4049453421
Short name T2056
Test name
Test status
Simulation time 25511953 ps
CPU time 0.72 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 202464 kb
Host smart-2d26b70d-9f74-4561-a668-766c6f87373f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049453421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
049453421
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.436310858
Short name T1974
Test name
Test status
Simulation time 86438679 ps
CPU time 0.74 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:19:39 PM PST 24
Peak memory 202556 kb
Host smart-e37e414e-e3e2-42a9-9441-8f7ced58673a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436310858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.436310858
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1627789438
Short name T1999
Test name
Test status
Simulation time 54775205 ps
CPU time 2.35 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 214620 kb
Host smart-4ff2d390-5215-482b-80ec-e4111617b41e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627789438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1627789438
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1679601505
Short name T131
Test name
Test status
Simulation time 35469549 ps
CPU time 1.38 seconds
Started Mar 07 01:19:32 PM PST 24
Finished Mar 07 01:19:33 PM PST 24
Peak memory 214688 kb
Host smart-4caec23d-12ab-4fde-82d8-5c7b397f2262
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679601505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1679601505
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1209725833
Short name T1936
Test name
Test status
Simulation time 37029217 ps
CPU time 0.65 seconds
Started Mar 07 01:19:47 PM PST 24
Finished Mar 07 01:19:48 PM PST 24
Peak memory 202432 kb
Host smart-a80b9a43-eef2-45bf-84de-95e2bff38233
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209725833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1209725833
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4034324176
Short name T1954
Test name
Test status
Simulation time 76456097 ps
CPU time 0.65 seconds
Started Mar 07 01:08:40 PM PST 24
Finished Mar 07 01:08:40 PM PST 24
Peak memory 202708 kb
Host smart-f9e3ec4d-3ab4-42a6-8fba-938014b1d0be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034324176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4034324176
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.663611206
Short name T1929
Test name
Test status
Simulation time 225312527 ps
CPU time 1.79 seconds
Started Mar 07 01:08:31 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 206172 kb
Host smart-a69817ba-cb4a-404a-973e-323260f9d288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663611206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.663611206
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.892178402
Short name T2133
Test name
Test status
Simulation time 215974538 ps
CPU time 4.08 seconds
Started Mar 07 01:19:42 PM PST 24
Finished Mar 07 01:19:46 PM PST 24
Peak memory 214668 kb
Host smart-0ece317f-e360-44ce-a571-7335153dc583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892178402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.892178402
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2008192280
Short name T113
Test name
Test status
Simulation time 44297892 ps
CPU time 3.18 seconds
Started Mar 07 01:19:47 PM PST 24
Finished Mar 07 01:19:51 PM PST 24
Peak memory 214912 kb
Host smart-8e1920a5-1970-47d1-8bd9-0097be85a025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008192280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
008192280
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2652543235
Short name T2053
Test name
Test status
Simulation time 142912616 ps
CPU time 2.93 seconds
Started Mar 07 01:08:35 PM PST 24
Finished Mar 07 01:08:38 PM PST 24
Peak memory 214740 kb
Host smart-46670f1a-ae53-499d-9d55-1e4287d5db7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652543235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
652543235
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1916061949
Short name T2004
Test name
Test status
Simulation time 1204029816 ps
CPU time 19.07 seconds
Started Mar 07 01:08:35 PM PST 24
Finished Mar 07 01:08:55 PM PST 24
Peak memory 214664 kb
Host smart-2f6bd1ed-d7c4-444a-9073-1107c82d3a68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916061949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1916061949
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2125055687
Short name T2090
Test name
Test status
Simulation time 276381590 ps
CPU time 18.03 seconds
Started Mar 07 01:19:33 PM PST 24
Finished Mar 07 01:19:51 PM PST 24
Peak memory 214628 kb
Host smart-228d4edd-680d-4cf5-bb4f-4b82bc9cb56f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125055687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2125055687
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2342390140
Short name T1996
Test name
Test status
Simulation time 15194540 ps
CPU time 0.76 seconds
Started Mar 07 01:20:01 PM PST 24
Finished Mar 07 01:20:02 PM PST 24
Peak memory 202516 kb
Host smart-6d8128cc-13dc-454a-815b-53b62e790742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342390140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2342390140
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.755115149
Short name T2071
Test name
Test status
Simulation time 36866844 ps
CPU time 0.76 seconds
Started Mar 07 01:08:55 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 202880 kb
Host smart-8f716aaf-18b0-4ebe-bee3-99961fbcbc3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755115149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.755115149
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1810938679
Short name T2063
Test name
Test status
Simulation time 19140740 ps
CPU time 0.73 seconds
Started Mar 07 01:08:57 PM PST 24
Finished Mar 07 01:08:58 PM PST 24
Peak memory 202528 kb
Host smart-a4dda04d-c8b6-4d19-aad2-3790df97f50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810938679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1810938679
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3426187506
Short name T1939
Test name
Test status
Simulation time 46181183 ps
CPU time 0.77 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:04 PM PST 24
Peak memory 202536 kb
Host smart-01707f03-31e9-40af-9af7-a41b47d3c595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426187506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3426187506
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3539626441
Short name T2031
Test name
Test status
Simulation time 14830305 ps
CPU time 0.74 seconds
Started Mar 07 01:20:03 PM PST 24
Finished Mar 07 01:20:04 PM PST 24
Peak memory 202536 kb
Host smart-3e4fbb9d-3a8b-4590-b82a-2f53ac4d2fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539626441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3539626441
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.705338381
Short name T2155
Test name
Test status
Simulation time 16393313 ps
CPU time 0.71 seconds
Started Mar 07 01:08:55 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 202544 kb
Host smart-ddb09e95-8147-4294-8093-14755f908ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705338381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.705338381
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3233602841
Short name T2124
Test name
Test status
Simulation time 33377708 ps
CPU time 0.7 seconds
Started Mar 07 01:20:07 PM PST 24
Finished Mar 07 01:20:08 PM PST 24
Peak memory 202540 kb
Host smart-248570b5-73e9-441a-9d08-e70c848d32ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233602841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3233602841
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4091808081
Short name T2096
Test name
Test status
Simulation time 24746856 ps
CPU time 0.81 seconds
Started Mar 07 01:08:56 PM PST 24
Finished Mar 07 01:08:57 PM PST 24
Peak memory 202592 kb
Host smart-70c8451c-59d6-4d04-9e13-16e5e57706f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091808081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4091808081
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1225731653
Short name T2196
Test name
Test status
Simulation time 15726466 ps
CPU time 0.72 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:02 PM PST 24
Peak memory 202864 kb
Host smart-14c997c4-f031-4782-b205-e9df6c568aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225731653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1225731653
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3504201320
Short name T1922
Test name
Test status
Simulation time 16816132 ps
CPU time 0.75 seconds
Started Mar 07 01:08:58 PM PST 24
Finished Mar 07 01:08:59 PM PST 24
Peak memory 202540 kb
Host smart-317779e4-a246-4b77-b377-992a427033dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504201320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3504201320
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3211087534
Short name T2121
Test name
Test status
Simulation time 14830514 ps
CPU time 0.71 seconds
Started Mar 07 01:08:56 PM PST 24
Finished Mar 07 01:08:57 PM PST 24
Peak memory 202516 kb
Host smart-cbedde8c-2951-43ac-b15a-62a24debe38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211087534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3211087534
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4159550558
Short name T2018
Test name
Test status
Simulation time 16820223 ps
CPU time 0.8 seconds
Started Mar 07 01:20:04 PM PST 24
Finished Mar 07 01:20:05 PM PST 24
Peak memory 202544 kb
Host smart-a563b56b-8090-4231-88db-9e0a943b9f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159550558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4159550558
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1525626795
Short name T2045
Test name
Test status
Simulation time 15123957 ps
CPU time 0.79 seconds
Started Mar 07 01:09:00 PM PST 24
Finished Mar 07 01:09:01 PM PST 24
Peak memory 202484 kb
Host smart-5b9009d5-1d72-4198-91eb-58e58500bf5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525626795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1525626795
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3288670285
Short name T2210
Test name
Test status
Simulation time 23715296 ps
CPU time 0.69 seconds
Started Mar 07 01:20:00 PM PST 24
Finished Mar 07 01:20:01 PM PST 24
Peak memory 202556 kb
Host smart-fc9f9f19-af92-4560-a13b-b00607110e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288670285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3288670285
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3541011116
Short name T1946
Test name
Test status
Simulation time 23760063 ps
CPU time 0.69 seconds
Started Mar 07 01:08:56 PM PST 24
Finished Mar 07 01:08:57 PM PST 24
Peak memory 202900 kb
Host smart-3fda97e8-e502-4337-8152-977a8ae67971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541011116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3541011116
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.964428255
Short name T1944
Test name
Test status
Simulation time 59637717 ps
CPU time 0.71 seconds
Started Mar 07 01:20:04 PM PST 24
Finished Mar 07 01:20:04 PM PST 24
Peak memory 202568 kb
Host smart-540c9345-a9ab-4dd0-b961-490f2ea7d95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964428255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.964428255
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.422449891
Short name T1938
Test name
Test status
Simulation time 77154891 ps
CPU time 0.71 seconds
Started Mar 07 01:08:59 PM PST 24
Finished Mar 07 01:09:01 PM PST 24
Peak memory 202512 kb
Host smart-81e0c9f5-f1f8-45af-91a6-25ad1d9e8f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422449891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.422449891
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.574097410
Short name T1933
Test name
Test status
Simulation time 54277063 ps
CPU time 0.78 seconds
Started Mar 07 01:20:01 PM PST 24
Finished Mar 07 01:20:03 PM PST 24
Peak memory 202552 kb
Host smart-52b3cba0-e0bf-47b4-b840-2e894b4641ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574097410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.574097410
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3172350211
Short name T1980
Test name
Test status
Simulation time 50280963 ps
CPU time 0.72 seconds
Started Mar 07 01:08:56 PM PST 24
Finished Mar 07 01:08:57 PM PST 24
Peak memory 202576 kb
Host smart-72f0a1cb-3654-47bf-9343-7260a266bad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172350211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3172350211
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3967075360
Short name T2000
Test name
Test status
Simulation time 132733215 ps
CPU time 0.71 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 202528 kb
Host smart-0388fb10-6e33-42e9-9a87-c3ecf8199a46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967075360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3967075360
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4091792271
Short name T1957
Test name
Test status
Simulation time 74702687 ps
CPU time 2.87 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:37 PM PST 24
Peak memory 215828 kb
Host smart-d2eb5852-adab-4508-a7ec-7f8a81669606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091792271 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4091792271
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3028167779
Short name T136
Test name
Test status
Simulation time 94391047 ps
CPU time 1.76 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:42 PM PST 24
Peak memory 206476 kb
Host smart-584c5ebd-abfb-4c58-bab5-473e30734fcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028167779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
028167779
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.828083671
Short name T2145
Test name
Test status
Simulation time 38634658 ps
CPU time 1.33 seconds
Started Mar 07 01:08:30 PM PST 24
Finished Mar 07 01:08:32 PM PST 24
Peak memory 214652 kb
Host smart-3ac51599-abaa-4cb5-b80e-e4c9e4838651
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828083671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.828083671
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1139437452
Short name T2184
Test name
Test status
Simulation time 46513081 ps
CPU time 0.71 seconds
Started Mar 07 01:19:46 PM PST 24
Finished Mar 07 01:19:47 PM PST 24
Peak memory 202868 kb
Host smart-663918ec-c1a1-4d71-887c-db4a4dcc9b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139437452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
139437452
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.619925957
Short name T2081
Test name
Test status
Simulation time 55636130 ps
CPU time 0.81 seconds
Started Mar 07 01:08:34 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 202836 kb
Host smart-ebf773e2-d8a1-40a9-aa73-43424930c870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619925957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.619925957
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1049814772
Short name T2126
Test name
Test status
Simulation time 1653248707 ps
CPU time 4.24 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:43 PM PST 24
Peak memory 206632 kb
Host smart-28c5ee2d-32e5-4fb9-81e9-aac169730d6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049814772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1049814772
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2329767580
Short name T1919
Test name
Test status
Simulation time 30087434 ps
CPU time 1.93 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 206520 kb
Host smart-a6009f0b-0237-41d3-a06c-1d47936564f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329767580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2329767580
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1245141762
Short name T2211
Test name
Test status
Simulation time 92885873 ps
CPU time 1.64 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 206588 kb
Host smart-c49fd90a-b888-4978-b541-8b1dbd3c8b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245141762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
245141762
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2046199226
Short name T120
Test name
Test status
Simulation time 889557914 ps
CPU time 4.28 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:45 PM PST 24
Peak memory 214896 kb
Host smart-99365490-e8e8-4f00-ad86-23fa837e5621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046199226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
046199226
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1194256828
Short name T178
Test name
Test status
Simulation time 674249933 ps
CPU time 7.59 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:40 PM PST 24
Peak memory 214724 kb
Host smart-343f40f0-eaf8-4ffe-a9d7-71f33581c405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194256828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1194256828
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3415381940
Short name T2161
Test name
Test status
Simulation time 1036824927 ps
CPU time 19.29 seconds
Started Mar 07 01:19:42 PM PST 24
Finished Mar 07 01:20:02 PM PST 24
Peak memory 214756 kb
Host smart-46d88352-c0e2-443e-93ad-00b20d293129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415381940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3415381940
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2261168321
Short name T2191
Test name
Test status
Simulation time 573101106 ps
CPU time 2.82 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:43 PM PST 24
Peak memory 214808 kb
Host smart-d4455ccb-f214-492f-8ff9-02ebfe592105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261168321 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2261168321
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3371718769
Short name T2047
Test name
Test status
Simulation time 94032958 ps
CPU time 2.97 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 216012 kb
Host smart-ce77f5f1-85cb-4c6d-a27b-60d5ec585067
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371718769 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3371718769
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2012994842
Short name T2049
Test name
Test status
Simulation time 120097067 ps
CPU time 1.21 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:41 PM PST 24
Peak memory 206496 kb
Host smart-44c12498-e18f-47ae-a196-f23291dffa44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012994842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
012994842
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2963009590
Short name T1975
Test name
Test status
Simulation time 47031601 ps
CPU time 1.42 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 206428 kb
Host smart-a1fcba29-de13-4352-a0fa-ac7ac81a25e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963009590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
963009590
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1785120640
Short name T2078
Test name
Test status
Simulation time 24563470 ps
CPU time 0.68 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:34 PM PST 24
Peak memory 202552 kb
Host smart-f81bbc84-f5f2-4a41-a1c5-561a14e0c421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785120640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
785120640
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2804806730
Short name T2175
Test name
Test status
Simulation time 50160437 ps
CPU time 0.72 seconds
Started Mar 07 01:19:42 PM PST 24
Finished Mar 07 01:19:42 PM PST 24
Peak memory 202864 kb
Host smart-3cd49396-efcc-4c4e-b011-90ce02c86ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804806730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
804806730
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3014863055
Short name T1988
Test name
Test status
Simulation time 396635591 ps
CPU time 3.1 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:43 PM PST 24
Peak memory 206488 kb
Host smart-794b48b4-31af-4cc0-b2da-bf19f3d3c970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014863055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3014863055
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.852286055
Short name T1970
Test name
Test status
Simulation time 506053947 ps
CPU time 3.01 seconds
Started Mar 07 01:08:36 PM PST 24
Finished Mar 07 01:08:39 PM PST 24
Peak memory 214732 kb
Host smart-23dc1baa-3ed2-4c72-86a7-caab43538b65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852286055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.852286055
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1886752639
Short name T103
Test name
Test status
Simulation time 35025676 ps
CPU time 1.22 seconds
Started Mar 07 01:08:40 PM PST 24
Finished Mar 07 01:08:41 PM PST 24
Peak memory 214748 kb
Host smart-b62a9a11-7517-4791-8ce9-90c2a14a3048
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886752639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
886752639
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2805537842
Short name T2080
Test name
Test status
Simulation time 171610626 ps
CPU time 3.96 seconds
Started Mar 07 01:19:41 PM PST 24
Finished Mar 07 01:19:45 PM PST 24
Peak memory 214820 kb
Host smart-c90d48b5-ffa4-4c80-9a50-20c21d044b63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805537842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
805537842
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1853743970
Short name T106
Test name
Test status
Simulation time 201556506 ps
CPU time 11.2 seconds
Started Mar 07 01:19:48 PM PST 24
Finished Mar 07 01:19:59 PM PST 24
Peak memory 214768 kb
Host smart-4cbcccf8-4277-4053-bfbc-0e7763893751
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853743970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1853743970
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1503245719
Short name T163
Test name
Test status
Simulation time 63606115 ps
CPU time 1.81 seconds
Started Mar 07 01:08:37 PM PST 24
Finished Mar 07 01:08:39 PM PST 24
Peak memory 214736 kb
Host smart-ea9d9245-8197-4db1-8540-a313a4542d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503245719 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1503245719
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2284316102
Short name T2130
Test name
Test status
Simulation time 326067906 ps
CPU time 4.01 seconds
Started Mar 07 01:19:45 PM PST 24
Finished Mar 07 01:19:49 PM PST 24
Peak memory 216188 kb
Host smart-ccdac1f1-b364-4c7d-9f8f-d2c99db1e453
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284316102 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2284316102
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1475311892
Short name T2149
Test name
Test status
Simulation time 39825245 ps
CPU time 1.34 seconds
Started Mar 07 01:08:36 PM PST 24
Finished Mar 07 01:08:38 PM PST 24
Peak memory 206420 kb
Host smart-0fc09a2f-3c3b-425b-bad0-95484dc39885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475311892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
475311892
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3892538077
Short name T2123
Test name
Test status
Simulation time 30749959 ps
CPU time 1.87 seconds
Started Mar 07 01:19:42 PM PST 24
Finished Mar 07 01:19:44 PM PST 24
Peak memory 206416 kb
Host smart-3a1ead86-2f22-416e-b26e-911f03cbb09f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892538077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
892538077
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2027297204
Short name T2171
Test name
Test status
Simulation time 44751005 ps
CPU time 0.7 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:41 PM PST 24
Peak memory 202520 kb
Host smart-aed1e7ac-19a9-4565-82f1-45efee5b0ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027297204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
027297204
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2816471563
Short name T2137
Test name
Test status
Simulation time 30629425 ps
CPU time 0.75 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 202576 kb
Host smart-131dfedc-280c-4f6f-ba9c-9cecfed23ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816471563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
816471563
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1104848339
Short name T1924
Test name
Test status
Simulation time 117541254 ps
CPU time 1.86 seconds
Started Mar 07 01:08:35 PM PST 24
Finished Mar 07 01:08:38 PM PST 24
Peak memory 206420 kb
Host smart-9910b211-9073-4896-b1f8-513fab133c9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104848339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1104848339
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.356965688
Short name T2142
Test name
Test status
Simulation time 58044803 ps
CPU time 1.95 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:41 PM PST 24
Peak memory 206392 kb
Host smart-b2d3ff42-e876-4141-b50e-0106abd75aaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356965688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.356965688
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1931384537
Short name T2101
Test name
Test status
Simulation time 178682227 ps
CPU time 3.53 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:37 PM PST 24
Peak memory 214872 kb
Host smart-259a34fd-a2b7-4745-9e71-af51338496a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931384537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
931384537
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.297508350
Short name T2104
Test name
Test status
Simulation time 518463425 ps
CPU time 3.41 seconds
Started Mar 07 01:19:41 PM PST 24
Finished Mar 07 01:19:45 PM PST 24
Peak memory 215700 kb
Host smart-21df646e-fea7-4016-a9b7-3a65ed28c93b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297508350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.297508350
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3339211463
Short name T182
Test name
Test status
Simulation time 349057486 ps
CPU time 7.07 seconds
Started Mar 07 01:19:38 PM PST 24
Finished Mar 07 01:19:45 PM PST 24
Peak memory 214704 kb
Host smart-7b1b20ed-377f-4efd-881c-5df6b536bfd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339211463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3339211463
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.814599570
Short name T2028
Test name
Test status
Simulation time 1021849631 ps
CPU time 22.91 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:55 PM PST 24
Peak memory 215416 kb
Host smart-9c0014ee-9ed8-4eed-9b09-81d8bf080697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814599570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.814599570
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2383737664
Short name T153
Test name
Test status
Simulation time 111122867 ps
CPU time 1.78 seconds
Started Mar 07 01:08:39 PM PST 24
Finished Mar 07 01:08:40 PM PST 24
Peak memory 214872 kb
Host smart-e1c89d6e-a15e-41c8-9062-e96d874f2dee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383737664 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2383737664
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2514253605
Short name T2198
Test name
Test status
Simulation time 100171299 ps
CPU time 1.69 seconds
Started Mar 07 01:19:46 PM PST 24
Finished Mar 07 01:19:48 PM PST 24
Peak memory 214824 kb
Host smart-ad21cefc-f3c0-437f-9be3-d2701d331b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514253605 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2514253605
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3868975018
Short name T132
Test name
Test status
Simulation time 31074206 ps
CPU time 1.9 seconds
Started Mar 07 01:08:38 PM PST 24
Finished Mar 07 01:08:40 PM PST 24
Peak memory 214764 kb
Host smart-b271206c-0ee7-45e8-a3f0-fe63018eab9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868975018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
868975018
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.458109367
Short name T2207
Test name
Test status
Simulation time 105890527 ps
CPU time 1.82 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:41 PM PST 24
Peak memory 206480 kb
Host smart-516913bd-b5df-4c70-869e-c75e00984191
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458109367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.458109367
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2025041815
Short name T1993
Test name
Test status
Simulation time 40834883 ps
CPU time 0.73 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:33 PM PST 24
Peak memory 202580 kb
Host smart-16893f87-4789-4409-bd12-53d5b182d9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025041815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
025041815
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3209346592
Short name T1987
Test name
Test status
Simulation time 12724788 ps
CPU time 0.76 seconds
Started Mar 07 01:19:37 PM PST 24
Finished Mar 07 01:19:38 PM PST 24
Peak memory 202588 kb
Host smart-3c85eb86-512e-4c3f-8509-74892f804818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209346592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
209346592
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3509993986
Short name T2040
Test name
Test status
Simulation time 147181074 ps
CPU time 3.2 seconds
Started Mar 07 01:19:43 PM PST 24
Finished Mar 07 01:19:46 PM PST 24
Peak memory 214756 kb
Host smart-48b16382-3b9f-43c9-ab73-cea55aee13f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509993986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3509993986
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.646955115
Short name T1956
Test name
Test status
Simulation time 63480352 ps
CPU time 2.78 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 214688 kb
Host smart-1f8af409-c8a8-4472-8c09-12b78237cd1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646955115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.646955115
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1049416852
Short name T2048
Test name
Test status
Simulation time 45320801 ps
CPU time 3.35 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:42 PM PST 24
Peak memory 214828 kb
Host smart-754e065d-b8e2-44f5-8284-8aa7ab79b4a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049416852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
049416852
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2597787322
Short name T115
Test name
Test status
Simulation time 334956692 ps
CPU time 4.65 seconds
Started Mar 07 01:08:37 PM PST 24
Finished Mar 07 01:08:42 PM PST 24
Peak memory 215780 kb
Host smart-8123adcc-278a-42bf-a227-173c005b3e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597787322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
597787322
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3049084626
Short name T175
Test name
Test status
Simulation time 215883150 ps
CPU time 12.28 seconds
Started Mar 07 01:08:38 PM PST 24
Finished Mar 07 01:08:50 PM PST 24
Peak memory 214704 kb
Host smart-8167a526-350e-4609-b45f-9e26d1b5ecff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049084626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3049084626
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1528617085
Short name T2006
Test name
Test status
Simulation time 77965070 ps
CPU time 3.13 seconds
Started Mar 07 01:08:32 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 215888 kb
Host smart-5f4687d6-775c-4893-a834-4be672b8cefb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528617085 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1528617085
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2605092911
Short name T2102
Test name
Test status
Simulation time 192778483 ps
CPU time 3.57 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:43 PM PST 24
Peak memory 215912 kb
Host smart-438ecb79-1f6a-4732-8231-2b2caab26ab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605092911 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2605092911
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2708842544
Short name T2050
Test name
Test status
Simulation time 480932783 ps
CPU time 1.7 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:35 PM PST 24
Peak memory 214676 kb
Host smart-fca9bf89-9de5-4618-9767-669acc0e0786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708842544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
708842544
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3802526195
Short name T2118
Test name
Test status
Simulation time 102926797 ps
CPU time 2.59 seconds
Started Mar 07 01:19:41 PM PST 24
Finished Mar 07 01:19:43 PM PST 24
Peak memory 206412 kb
Host smart-4abc740f-8021-4418-b2de-1c79ad180f69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802526195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
802526195
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2477684184
Short name T2173
Test name
Test status
Simulation time 191125919 ps
CPU time 0.71 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:40 PM PST 24
Peak memory 202520 kb
Host smart-e7db1193-2597-4c46-8695-01ce5fab2f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477684184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
477684184
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2646700989
Short name T1949
Test name
Test status
Simulation time 16696667 ps
CPU time 0.73 seconds
Started Mar 07 01:08:36 PM PST 24
Finished Mar 07 01:08:37 PM PST 24
Peak memory 202792 kb
Host smart-98bd8e70-e158-4695-b291-71f56ed2d479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646700989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
646700989
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1174094409
Short name T2046
Test name
Test status
Simulation time 618895099 ps
CPU time 4.03 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:44 PM PST 24
Peak memory 214660 kb
Host smart-c66dc438-0b9f-41ee-8a4a-139f1ae2721e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174094409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1174094409
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.822538056
Short name T2002
Test name
Test status
Simulation time 812901751 ps
CPU time 4.38 seconds
Started Mar 07 01:08:37 PM PST 24
Finished Mar 07 01:08:42 PM PST 24
Peak memory 206588 kb
Host smart-9a873856-a710-45ea-ab11-dd470d397300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822538056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.822538056
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.240382778
Short name T114
Test name
Test status
Simulation time 55847544 ps
CPU time 2.24 seconds
Started Mar 07 01:19:39 PM PST 24
Finished Mar 07 01:19:41 PM PST 24
Peak memory 215720 kb
Host smart-f1200720-4121-402d-96eb-3b9b5fcb0ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240382778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.240382778
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2702731444
Short name T2152
Test name
Test status
Simulation time 100441255 ps
CPU time 3.76 seconds
Started Mar 07 01:08:33 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 214748 kb
Host smart-c2016b37-5355-4b30-a029-5245be23f58a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702731444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
702731444
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1746170147
Short name T2174
Test name
Test status
Simulation time 200375651 ps
CPU time 11.02 seconds
Started Mar 07 01:08:38 PM PST 24
Finished Mar 07 01:08:49 PM PST 24
Peak memory 214876 kb
Host smart-6da17949-a630-4db9-bf75-52622fcab3c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746170147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1746170147
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2718484697
Short name T2013
Test name
Test status
Simulation time 314818180 ps
CPU time 12.7 seconds
Started Mar 07 01:19:40 PM PST 24
Finished Mar 07 01:19:53 PM PST 24
Peak memory 214712 kb
Host smart-45ce123c-9334-4fea-b769-4bde427adf9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718484697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2718484697
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.223519202
Short name T1228
Test name
Test status
Simulation time 35078717 ps
CPU time 0.68 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:40:48 PM PST 24
Peak memory 205212 kb
Host smart-2811dec5-b104-4736-8617-df3771e9f9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223519202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.223519202
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3950805354
Short name T1377
Test name
Test status
Simulation time 12349089 ps
CPU time 0.7 seconds
Started Mar 07 02:42:45 PM PST 24
Finished Mar 07 02:42:46 PM PST 24
Peak memory 204436 kb
Host smart-b64bbc49-fdfb-4ae1-a149-c59bac51b589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950805354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
950805354
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2008194907
Short name T1787
Test name
Test status
Simulation time 1613220984 ps
CPU time 9.25 seconds
Started Mar 07 02:42:44 PM PST 24
Finished Mar 07 02:42:53 PM PST 24
Peak memory 233968 kb
Host smart-252faea7-2e23-4352-8476-fdedbc145562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008194907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2008194907
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4001657567
Short name T127
Test name
Test status
Simulation time 259160878 ps
CPU time 3.77 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:40:51 PM PST 24
Peak memory 233616 kb
Host smart-ea07586b-ba6d-484d-b5b0-780598d4d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001657567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4001657567
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2353474693
Short name T904
Test name
Test status
Simulation time 68181869 ps
CPU time 0.78 seconds
Started Mar 07 12:40:45 PM PST 24
Finished Mar 07 12:40:46 PM PST 24
Peak memory 206324 kb
Host smart-c424fde0-10d1-4def-9d1f-cd8d764ff065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353474693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2353474693
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4128242919
Short name T365
Test name
Test status
Simulation time 82103022 ps
CPU time 0.73 seconds
Started Mar 07 02:42:39 PM PST 24
Finished Mar 07 02:42:40 PM PST 24
Peak memory 204836 kb
Host smart-b549394a-d5fe-44c1-8af1-71fc44463675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128242919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4128242919
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2059875897
Short name T1317
Test name
Test status
Simulation time 4411987645 ps
CPU time 49.02 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:41:36 PM PST 24
Peak memory 248852 kb
Host smart-60b1a8ff-eaa7-464f-a902-b351a2bee0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059875897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2059875897
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3537277967
Short name T1759
Test name
Test status
Simulation time 2782577151 ps
CPU time 36.46 seconds
Started Mar 07 02:42:46 PM PST 24
Finished Mar 07 02:43:23 PM PST 24
Peak memory 240408 kb
Host smart-b5973b42-5b7f-46c9-a81b-decc8e8b30f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537277967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3537277967
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1986782481
Short name T856
Test name
Test status
Simulation time 310739004611 ps
CPU time 544.93 seconds
Started Mar 07 02:42:43 PM PST 24
Finished Mar 07 02:51:48 PM PST 24
Peak memory 256928 kb
Host smart-390eef32-83b5-43d3-b033-e5eedb9d0e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986782481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1986782481
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2244168927
Short name T1398
Test name
Test status
Simulation time 41041278196 ps
CPU time 202.18 seconds
Started Mar 07 12:40:49 PM PST 24
Finished Mar 07 12:44:11 PM PST 24
Peak memory 253532 kb
Host smart-164194df-4d62-4a61-8122-ee639b1b5d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244168927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2244168927
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2070463844
Short name T1291
Test name
Test status
Simulation time 154957508576 ps
CPU time 231.25 seconds
Started Mar 07 02:42:46 PM PST 24
Finished Mar 07 02:46:37 PM PST 24
Peak memory 234352 kb
Host smart-70dda7b0-f52b-4ab3-a0f9-3aafaa32e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070463844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2070463844
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2172690211
Short name T1619
Test name
Test status
Simulation time 67900253544 ps
CPU time 414.27 seconds
Started Mar 07 12:40:48 PM PST 24
Finished Mar 07 12:47:43 PM PST 24
Peak memory 261892 kb
Host smart-3cfe722a-3ba9-4d9d-99c4-e715fd5fc58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172690211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2172690211
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1929205541
Short name T1488
Test name
Test status
Simulation time 5082706684 ps
CPU time 10.4 seconds
Started Mar 07 12:40:45 PM PST 24
Finished Mar 07 12:40:56 PM PST 24
Peak memory 224440 kb
Host smart-9caa5134-84cf-4cfd-8cda-3c31d96d407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929205541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1929205541
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.296195743
Short name T187
Test name
Test status
Simulation time 2299326601 ps
CPU time 13.24 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:41:01 PM PST 24
Peak memory 217896 kb
Host smart-66faa0ca-6b29-49ac-898e-31e7665aa6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296195743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.296195743
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.403582414
Short name T1263
Test name
Test status
Simulation time 13900077979 ps
CPU time 19.61 seconds
Started Mar 07 02:42:45 PM PST 24
Finished Mar 07 02:43:05 PM PST 24
Peak memory 235656 kb
Host smart-a43b3e96-75ab-4ad4-9c4f-5e715446a780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403582414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.403582414
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3677809177
Short name T1063
Test name
Test status
Simulation time 36228965078 ps
CPU time 11.13 seconds
Started Mar 07 12:40:46 PM PST 24
Finished Mar 07 12:40:57 PM PST 24
Peak memory 232692 kb
Host smart-776d9dbc-0037-4103-a7d0-4ffbddc04cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677809177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3677809177
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3970233945
Short name T205
Test name
Test status
Simulation time 5802832947 ps
CPU time 9.51 seconds
Started Mar 07 02:42:46 PM PST 24
Finished Mar 07 02:42:55 PM PST 24
Peak memory 232868 kb
Host smart-816bec4c-fff5-4111-be3c-3ea213c438ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970233945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3970233945
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.280311030
Short name T1762
Test name
Test status
Simulation time 2464731327 ps
CPU time 10.89 seconds
Started Mar 07 02:42:46 PM PST 24
Finished Mar 07 02:42:57 PM PST 24
Peak memory 217316 kb
Host smart-448dd6fb-4ee5-408a-8af7-6cdfc539f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280311030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.280311030
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2952394780
Short name T692
Test name
Test status
Simulation time 551820096 ps
CPU time 5.2 seconds
Started Mar 07 12:40:48 PM PST 24
Finished Mar 07 12:40:53 PM PST 24
Peak memory 224428 kb
Host smart-b0fecc5b-0da4-47cc-b29f-9342b14e1873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952394780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2952394780
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1143812689
Short name T669
Test name
Test status
Simulation time 24265295 ps
CPU time 0.73 seconds
Started Mar 07 02:42:43 PM PST 24
Finished Mar 07 02:42:44 PM PST 24
Peak memory 215616 kb
Host smart-54c15f1c-1d92-45bc-b318-5571eadacb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143812689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1143812689
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1567137009
Short name T1089
Test name
Test status
Simulation time 34537465 ps
CPU time 0.73 seconds
Started Mar 07 12:40:45 PM PST 24
Finished Mar 07 12:40:46 PM PST 24
Peak memory 216116 kb
Host smart-2e480cc0-4931-4189-87eb-9c0b30ab344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567137009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1567137009
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2631082377
Short name T833
Test name
Test status
Simulation time 1057013916 ps
CPU time 5.81 seconds
Started Mar 07 02:42:46 PM PST 24
Finished Mar 07 02:42:52 PM PST 24
Peak memory 219740 kb
Host smart-e38ee8db-ab69-44e6-8ec4-d58faa783b78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2631082377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2631082377
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.560708389
Short name T568
Test name
Test status
Simulation time 298224228 ps
CPU time 3.38 seconds
Started Mar 07 12:40:48 PM PST 24
Finished Mar 07 12:40:51 PM PST 24
Peak memory 219048 kb
Host smart-e629ccf3-be48-44ae-9ac7-0dc08e1579cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=560708389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.560708389
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4267649176
Short name T75
Test name
Test status
Simulation time 83075163 ps
CPU time 1.19 seconds
Started Mar 07 02:42:46 PM PST 24
Finished Mar 07 02:42:47 PM PST 24
Peak memory 235056 kb
Host smart-df9d9ad3-2d71-43fa-9048-4080ddf1510b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267649176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4267649176
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.126789456
Short name T1134
Test name
Test status
Simulation time 177764620082 ps
CPU time 339.28 seconds
Started Mar 07 02:42:46 PM PST 24
Finished Mar 07 02:48:26 PM PST 24
Peak memory 270952 kb
Host smart-a6710742-f721-4302-be34-f30eabb275b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126789456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.126789456
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4118997442
Short name T1508
Test name
Test status
Simulation time 324181117921 ps
CPU time 620.36 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:51:07 PM PST 24
Peak memory 273716 kb
Host smart-fa8b3e06-e1f9-4d14-9961-ea1b24f36085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118997442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4118997442
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1987414828
Short name T322
Test name
Test status
Simulation time 65822541015 ps
CPU time 59.81 seconds
Started Mar 07 02:42:43 PM PST 24
Finished Mar 07 02:43:43 PM PST 24
Peak memory 215788 kb
Host smart-c8faaeda-0414-4e72-b9ff-60ed027fff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987414828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1987414828
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4055594377
Short name T1379
Test name
Test status
Simulation time 20147160993 ps
CPU time 27.66 seconds
Started Mar 07 12:40:46 PM PST 24
Finished Mar 07 12:41:14 PM PST 24
Peak memory 216188 kb
Host smart-8ac3276b-1586-4d18-a08b-71e311ee6b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055594377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4055594377
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3620389385
Short name T1030
Test name
Test status
Simulation time 9969135256 ps
CPU time 7.58 seconds
Started Mar 07 02:42:44 PM PST 24
Finished Mar 07 02:42:51 PM PST 24
Peak memory 215816 kb
Host smart-23321195-4efa-4727-ba2f-759a7370195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620389385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3620389385
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3714044848
Short name T740
Test name
Test status
Simulation time 19722450038 ps
CPU time 19.97 seconds
Started Mar 07 12:40:46 PM PST 24
Finished Mar 07 12:41:07 PM PST 24
Peak memory 216196 kb
Host smart-2008f8ff-e667-4027-86bf-6460db297c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714044848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3714044848
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1928927445
Short name T1306
Test name
Test status
Simulation time 194825788 ps
CPU time 2.57 seconds
Started Mar 07 02:42:46 PM PST 24
Finished Mar 07 02:42:48 PM PST 24
Peak memory 215696 kb
Host smart-3fd7ed44-a22c-4a23-811e-a86b3d61129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928927445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1928927445
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3281715696
Short name T1378
Test name
Test status
Simulation time 366073013 ps
CPU time 1.12 seconds
Started Mar 07 12:40:49 PM PST 24
Finished Mar 07 12:40:50 PM PST 24
Peak memory 207372 kb
Host smart-f662446b-9a57-4981-a1b2-2e0eef7a5896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281715696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3281715696
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1286231220
Short name T463
Test name
Test status
Simulation time 74798049 ps
CPU time 0.81 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:41 PM PST 24
Peak memory 204868 kb
Host smart-d84c64b3-eb9a-47c4-a429-00901fca5187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286231220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1286231220
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1518004959
Short name T1818
Test name
Test status
Simulation time 46687752 ps
CPU time 0.82 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:40:48 PM PST 24
Peak memory 205428 kb
Host smart-2a84bc2a-8016-4ae1-8bd0-b3b7123b7a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518004959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1518004959
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1205167510
Short name T1737
Test name
Test status
Simulation time 6294081909 ps
CPU time 6.11 seconds
Started Mar 07 02:42:43 PM PST 24
Finished Mar 07 02:42:49 PM PST 24
Peak memory 215740 kb
Host smart-606a41d7-28af-4473-a755-114d90076696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205167510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1205167510
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_upload.528512886
Short name T1035
Test name
Test status
Simulation time 2112987074 ps
CPU time 10.27 seconds
Started Mar 07 12:40:46 PM PST 24
Finished Mar 07 12:40:56 PM PST 24
Peak memory 231580 kb
Host smart-0a05b3b3-42d8-43ec-bd0e-5f7cd28ac8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528512886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.528512886
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1009067140
Short name T1658
Test name
Test status
Simulation time 18030334 ps
CPU time 0.68 seconds
Started Mar 07 12:40:58 PM PST 24
Finished Mar 07 12:40:59 PM PST 24
Peak memory 204544 kb
Host smart-fe03292b-7343-4425-8e6c-4df2bed5cf19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009067140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
009067140
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3159719604
Short name T834
Test name
Test status
Simulation time 74660818 ps
CPU time 0.71 seconds
Started Mar 07 02:42:53 PM PST 24
Finished Mar 07 02:42:53 PM PST 24
Peak memory 204432 kb
Host smart-7f9b1bd3-ba45-4705-805f-18bf47494903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159719604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
159719604
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1050143492
Short name T874
Test name
Test status
Simulation time 125485032 ps
CPU time 2.73 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:03 PM PST 24
Peak memory 233544 kb
Host smart-16a5a83c-6f15-4817-b539-d6fe65b5f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050143492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1050143492
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1209103738
Short name T243
Test name
Test status
Simulation time 2847984258 ps
CPU time 2.84 seconds
Started Mar 07 02:42:57 PM PST 24
Finished Mar 07 02:43:01 PM PST 24
Peak memory 218804 kb
Host smart-cff04777-1033-4165-aab3-9fb3f38c8fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209103738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1209103738
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.374379125
Short name T879
Test name
Test status
Simulation time 17452026 ps
CPU time 0.73 seconds
Started Mar 07 02:42:47 PM PST 24
Finished Mar 07 02:42:48 PM PST 24
Peak memory 204836 kb
Host smart-8f96b6cc-5b6a-4a7a-84fb-62a2ca80c9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374379125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.374379125
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.740017486
Short name T891
Test name
Test status
Simulation time 29382587 ps
CPU time 0.76 seconds
Started Mar 07 12:40:48 PM PST 24
Finished Mar 07 12:40:49 PM PST 24
Peak memory 206208 kb
Host smart-8937d107-2149-44e1-8fa0-94a8036f872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740017486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.740017486
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1302681887
Short name T1227
Test name
Test status
Simulation time 10408034202 ps
CPU time 89.59 seconds
Started Mar 07 12:40:57 PM PST 24
Finished Mar 07 12:42:27 PM PST 24
Peak memory 257240 kb
Host smart-4c839568-3586-4337-b007-ab85253c00a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302681887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1302681887
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1198646705
Short name T1655
Test name
Test status
Simulation time 79137569975 ps
CPU time 99.07 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:42:35 PM PST 24
Peak memory 261372 kb
Host smart-6deb5948-2844-400f-ba24-406e9478e6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198646705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1198646705
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2150207994
Short name T1473
Test name
Test status
Simulation time 47428671329 ps
CPU time 117.51 seconds
Started Mar 07 02:42:58 PM PST 24
Finished Mar 07 02:44:56 PM PST 24
Peak memory 262740 kb
Host smart-d04348eb-ac09-4828-8d7f-be6a795973e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150207994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2150207994
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1951489521
Short name T1742
Test name
Test status
Simulation time 113951767293 ps
CPU time 192.08 seconds
Started Mar 07 02:42:56 PM PST 24
Finished Mar 07 02:46:08 PM PST 24
Peak memory 262380 kb
Host smart-26c4f343-1568-42fe-ad1e-e9b9cc019f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951489521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1951489521
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2781742134
Short name T293
Test name
Test status
Simulation time 29480112878 ps
CPU time 217.98 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:44:38 PM PST 24
Peak memory 255496 kb
Host smart-586d6237-7d44-4944-a103-03357b319168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781742134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2781742134
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1410810577
Short name T1145
Test name
Test status
Simulation time 126063317158 ps
CPU time 47.13 seconds
Started Mar 07 02:42:56 PM PST 24
Finished Mar 07 02:43:44 PM PST 24
Peak memory 245020 kb
Host smart-f315c5a8-ecbc-48aa-9266-15040d703f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410810577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1410810577
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.537788077
Short name T942
Test name
Test status
Simulation time 25533752285 ps
CPU time 34.72 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:35 PM PST 24
Peak memory 235772 kb
Host smart-d6d6c529-3378-4554-99b2-a80767aa3a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537788077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.537788077
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2548609090
Short name T651
Test name
Test status
Simulation time 124544541 ps
CPU time 2.21 seconds
Started Mar 07 02:43:00 PM PST 24
Finished Mar 07 02:43:03 PM PST 24
Peak memory 217508 kb
Host smart-22ba708f-c453-45d1-ac3e-7dedda9efea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548609090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2548609090
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3140519006
Short name T1346
Test name
Test status
Simulation time 1988725368 ps
CPU time 7.4 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:07 PM PST 24
Peak memory 233592 kb
Host smart-a1d80dd5-9f4b-4e8a-845e-a8d77bfec9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140519006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3140519006
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1621943754
Short name T1423
Test name
Test status
Simulation time 521942111 ps
CPU time 3.46 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:03 PM PST 24
Peak memory 218428 kb
Host smart-6af14a34-2a44-4c8a-a3a5-9197abcf3f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621943754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1621943754
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.556270635
Short name T1662
Test name
Test status
Simulation time 4905760222 ps
CPU time 7.36 seconds
Started Mar 07 02:42:57 PM PST 24
Finished Mar 07 02:43:05 PM PST 24
Peak memory 233032 kb
Host smart-2e6a7458-e0af-4b0d-a024-204fac8df4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556270635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.556270635
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2558529936
Short name T1503
Test name
Test status
Simulation time 18212635 ps
CPU time 1.06 seconds
Started Mar 07 02:42:43 PM PST 24
Finished Mar 07 02:42:45 PM PST 24
Peak memory 216072 kb
Host smart-ce7e4ab3-8274-4115-94f0-2226291bdf67
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558529936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2558529936
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2638632304
Short name T1830
Test name
Test status
Simulation time 927038281 ps
CPU time 11.55 seconds
Started Mar 07 02:42:58 PM PST 24
Finished Mar 07 02:43:10 PM PST 24
Peak memory 252220 kb
Host smart-d7447199-ecac-415d-830c-fb0aea36e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638632304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2638632304
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.944935092
Short name T1338
Test name
Test status
Simulation time 1369201395 ps
CPU time 5.86 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:06 PM PST 24
Peak memory 226692 kb
Host smart-608bf903-c143-4526-9343-384ba4b68338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944935092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
944935092
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2253400234
Short name T807
Test name
Test status
Simulation time 3304021435 ps
CPU time 5.78 seconds
Started Mar 07 02:42:57 PM PST 24
Finished Mar 07 02:43:03 PM PST 24
Peak memory 216992 kb
Host smart-4646d5d5-8869-42af-9844-6b100219f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253400234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2253400234
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3866228363
Short name T939
Test name
Test status
Simulation time 239114479371 ps
CPU time 34.13 seconds
Started Mar 07 12:40:48 PM PST 24
Finished Mar 07 12:41:22 PM PST 24
Peak memory 234396 kb
Host smart-d0d832b8-9f07-485e-91af-3b6f45ee8cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866228363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3866228363
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.1542997540
Short name T1361
Test name
Test status
Simulation time 18356972 ps
CPU time 0.74 seconds
Started Mar 07 02:42:47 PM PST 24
Finished Mar 07 02:42:48 PM PST 24
Peak memory 215564 kb
Host smart-283b4899-666b-4be5-83cb-683aec7956a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542997540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.1542997540
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3932115334
Short name T1344
Test name
Test status
Simulation time 22598676 ps
CPU time 0.71 seconds
Started Mar 07 12:40:46 PM PST 24
Finished Mar 07 12:40:47 PM PST 24
Peak memory 216172 kb
Host smart-debab395-f922-4608-a974-13732895cebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932115334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3932115334
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3658312992
Short name T148
Test name
Test status
Simulation time 626433538 ps
CPU time 3.94 seconds
Started Mar 07 02:42:54 PM PST 24
Finished Mar 07 02:42:58 PM PST 24
Peak memory 218236 kb
Host smart-c1dc2746-dc51-4893-843e-665b67f4e962
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658312992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3658312992
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4236433392
Short name T1578
Test name
Test status
Simulation time 314263337 ps
CPU time 4.41 seconds
Started Mar 07 12:40:57 PM PST 24
Finished Mar 07 12:41:02 PM PST 24
Peak memory 222452 kb
Host smart-7fd24f8e-5693-4806-b0cf-16769fbfeb9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4236433392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4236433392
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1165088315
Short name T72
Test name
Test status
Simulation time 173406105 ps
CPU time 1.24 seconds
Started Mar 07 02:42:59 PM PST 24
Finished Mar 07 02:43:01 PM PST 24
Peak memory 235612 kb
Host smart-8150223e-37b6-4e61-9007-ec3221ae1216
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165088315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1165088315
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.490039526
Short name T67
Test name
Test status
Simulation time 711150804 ps
CPU time 1.34 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:02 PM PST 24
Peak memory 235572 kb
Host smart-8f370f5e-0a81-4940-a092-fadf319c828b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490039526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.490039526
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1084821135
Short name T159
Test name
Test status
Simulation time 19608523752 ps
CPU time 88.86 seconds
Started Mar 07 12:40:58 PM PST 24
Finished Mar 07 12:42:28 PM PST 24
Peak memory 254264 kb
Host smart-bbf27f66-ef40-4eb7-b65c-28a2a7c02bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084821135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1084821135
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.142842952
Short name T265
Test name
Test status
Simulation time 154112019839 ps
CPU time 211.77 seconds
Started Mar 07 02:42:53 PM PST 24
Finished Mar 07 02:46:25 PM PST 24
Peak memory 255008 kb
Host smart-85d8b3d8-92f0-43e0-bd47-d2c285f4ec45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142842952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.142842952
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1018702081
Short name T1110
Test name
Test status
Simulation time 43965896136 ps
CPU time 41.84 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:41:30 PM PST 24
Peak memory 216260 kb
Host smart-ac31aa6f-4ed9-4408-91fa-bf888e5b30d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018702081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1018702081
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2887110286
Short name T1158
Test name
Test status
Simulation time 7327432640 ps
CPU time 35.22 seconds
Started Mar 07 02:43:01 PM PST 24
Finished Mar 07 02:43:36 PM PST 24
Peak memory 215704 kb
Host smart-7c4e3318-87f9-42b1-bfaa-59155520baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887110286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2887110286
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1919376033
Short name T1011
Test name
Test status
Simulation time 1221677134 ps
CPU time 3.83 seconds
Started Mar 07 02:42:44 PM PST 24
Finished Mar 07 02:42:48 PM PST 24
Peak memory 207648 kb
Host smart-c8784b48-bf93-498b-90ea-321001540d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919376033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1919376033
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2663241798
Short name T630
Test name
Test status
Simulation time 513865279 ps
CPU time 1.47 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:40:48 PM PST 24
Peak memory 206624 kb
Host smart-2a7a65b1-86e0-45b5-ab13-875a5c3158eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663241798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2663241798
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4001187739
Short name T1822
Test name
Test status
Simulation time 237109646 ps
CPU time 2.47 seconds
Started Mar 07 12:40:47 PM PST 24
Finished Mar 07 12:40:50 PM PST 24
Peak memory 216332 kb
Host smart-d889cbca-e54f-4da2-852e-c45061cd4be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001187739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4001187739
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4275199516
Short name T1138
Test name
Test status
Simulation time 492038251 ps
CPU time 12.1 seconds
Started Mar 07 02:42:58 PM PST 24
Finished Mar 07 02:43:10 PM PST 24
Peak memory 215840 kb
Host smart-fde8ddde-b9fa-4a75-bc9d-10f8a8af4409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275199516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4275199516
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.257379750
Short name T1874
Test name
Test status
Simulation time 163814843 ps
CPU time 0.89 seconds
Started Mar 07 12:40:48 PM PST 24
Finished Mar 07 12:40:49 PM PST 24
Peak memory 206436 kb
Host smart-905dfe49-f12b-4de6-95aa-8f821f8fbc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257379750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.257379750
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3068443220
Short name T1498
Test name
Test status
Simulation time 176861550 ps
CPU time 0.84 seconds
Started Mar 07 02:42:56 PM PST 24
Finished Mar 07 02:42:57 PM PST 24
Peak memory 204812 kb
Host smart-729063b1-6972-4ce6-9d70-e5c9bddd970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068443220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3068443220
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2242545345
Short name T1701
Test name
Test status
Simulation time 15149221592 ps
CPU time 34.61 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:35 PM PST 24
Peak memory 246712 kb
Host smart-7498bbfe-77d3-4cec-9003-c15c77ef617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242545345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2242545345
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_upload.3695470501
Short name T239
Test name
Test status
Simulation time 16873712009 ps
CPU time 6.43 seconds
Started Mar 07 02:42:58 PM PST 24
Finished Mar 07 02:43:05 PM PST 24
Peak memory 233240 kb
Host smart-d068d9d8-6444-4e42-985e-869e2b7b23a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695470501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3695470501
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4174201767
Short name T366
Test name
Test status
Simulation time 20397297 ps
CPU time 0.7 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 204572 kb
Host smart-114a79fe-8264-4936-828d-ea23b829797f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174201767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4174201767
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.619278343
Short name T1447
Test name
Test status
Simulation time 188988446 ps
CPU time 0.71 seconds
Started Mar 07 02:43:31 PM PST 24
Finished Mar 07 02:43:33 PM PST 24
Peak memory 203932 kb
Host smart-a7a7a222-6abb-40a7-be46-5c4684447c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619278343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.619278343
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1320528105
Short name T1273
Test name
Test status
Simulation time 74094275 ps
CPU time 2.31 seconds
Started Mar 07 02:43:34 PM PST 24
Finished Mar 07 02:43:37 PM PST 24
Peak memory 216080 kb
Host smart-0e363123-4ed4-4683-b2c7-d1ae1ae391dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320528105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1320528105
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4277444847
Short name T539
Test name
Test status
Simulation time 3389275207 ps
CPU time 5.33 seconds
Started Mar 07 12:41:51 PM PST 24
Finished Mar 07 12:41:57 PM PST 24
Peak memory 233276 kb
Host smart-f1937716-ff9f-4a14-8881-e5c821a9ecaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277444847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4277444847
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.103097285
Short name T1552
Test name
Test status
Simulation time 35680941 ps
CPU time 0.75 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:43:24 PM PST 24
Peak memory 204488 kb
Host smart-1d146b5f-c237-481c-8358-acf0ff1a1b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103097285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.103097285
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3811154927
Short name T686
Test name
Test status
Simulation time 18021143 ps
CPU time 0.84 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:41:42 PM PST 24
Peak memory 206292 kb
Host smart-fa98e1b0-41b3-4f99-b559-c4f8b699553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811154927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3811154927
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1299274677
Short name T699
Test name
Test status
Simulation time 168153520407 ps
CPU time 47.18 seconds
Started Mar 07 02:43:33 PM PST 24
Finished Mar 07 02:44:21 PM PST 24
Peak memory 237644 kb
Host smart-e55123ec-157c-4493-9a20-4d5be696dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299274677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1299274677
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.903869486
Short name T996
Test name
Test status
Simulation time 95581048306 ps
CPU time 120.83 seconds
Started Mar 07 12:41:49 PM PST 24
Finished Mar 07 12:43:50 PM PST 24
Peak memory 240936 kb
Host smart-94ea091c-c452-4925-985e-0106b4099cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903869486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.903869486
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4037134478
Short name T1675
Test name
Test status
Simulation time 75671177636 ps
CPU time 227.59 seconds
Started Mar 07 02:43:33 PM PST 24
Finished Mar 07 02:47:21 PM PST 24
Peak memory 238772 kb
Host smart-ddbc8e6d-10c2-4e15-8c2f-b069def279a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037134478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4037134478
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1483977252
Short name T621
Test name
Test status
Simulation time 32439123464 ps
CPU time 216.57 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:45:28 PM PST 24
Peak memory 257132 kb
Host smart-9d8d6963-3e8e-4eb8-9a79-2974a40e1c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483977252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1483977252
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3083590966
Short name T299
Test name
Test status
Simulation time 2528404108 ps
CPU time 51.6 seconds
Started Mar 07 02:43:34 PM PST 24
Finished Mar 07 02:44:26 PM PST 24
Peak memory 253084 kb
Host smart-305bbbf9-91ba-4308-86c3-ed1d22dcf106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083590966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3083590966
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2651523594
Short name T1257
Test name
Test status
Simulation time 66872331768 ps
CPU time 26.08 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:42:19 PM PST 24
Peak memory 234364 kb
Host smart-35b405e4-2801-4770-acd4-dca338b41ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651523594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2651523594
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.417688039
Short name T476
Test name
Test status
Simulation time 7281111461 ps
CPU time 14.42 seconds
Started Mar 07 02:43:31 PM PST 24
Finished Mar 07 02:43:46 PM PST 24
Peak memory 232096 kb
Host smart-0857701c-dbc2-402c-be79-af1831e52f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417688039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.417688039
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1645772192
Short name T1098
Test name
Test status
Simulation time 1426841486 ps
CPU time 3.8 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:41:56 PM PST 24
Peak memory 233220 kb
Host smart-3ee3169b-af90-4de7-b7c7-2e9818d8af46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645772192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1645772192
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3176959043
Short name T1814
Test name
Test status
Simulation time 629113471 ps
CPU time 4.63 seconds
Started Mar 07 02:43:36 PM PST 24
Finished Mar 07 02:43:41 PM PST 24
Peak memory 232892 kb
Host smart-7e3853ff-8ec7-4694-a62e-6d4cbd6ae492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176959043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3176959043
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3962706313
Short name T1272
Test name
Test status
Simulation time 5006515774 ps
CPU time 12.47 seconds
Started Mar 07 12:41:50 PM PST 24
Finished Mar 07 12:42:02 PM PST 24
Peak memory 235116 kb
Host smart-a5b05597-5326-4a1f-ae03-a1bc2c1c8556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962706313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3962706313
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4020920129
Short name T821
Test name
Test status
Simulation time 2445586743 ps
CPU time 12.09 seconds
Started Mar 07 02:43:33 PM PST 24
Finished Mar 07 02:43:45 PM PST 24
Peak memory 216140 kb
Host smart-e59702fa-5d65-41b2-89ea-936a35edccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020920129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4020920129
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1454625627
Short name T407
Test name
Test status
Simulation time 89456069 ps
CPU time 1.05 seconds
Started Mar 07 02:43:36 PM PST 24
Finished Mar 07 02:43:37 PM PST 24
Peak memory 215848 kb
Host smart-56874477-fb81-4cbe-acdf-61899f0e8aff
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454625627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1454625627
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1284012260
Short name T1708
Test name
Test status
Simulation time 3933817066 ps
CPU time 8.6 seconds
Started Mar 07 02:43:26 PM PST 24
Finished Mar 07 02:43:35 PM PST 24
Peak memory 238364 kb
Host smart-0beb03d3-f651-4732-8f62-5c8585e337ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284012260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1284012260
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1937894459
Short name T249
Test name
Test status
Simulation time 9233877102 ps
CPU time 24.4 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:42:16 PM PST 24
Peak memory 233580 kb
Host smart-74f59ac7-b012-4110-a9ed-991015fd9caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937894459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1937894459
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4074193033
Short name T1405
Test name
Test status
Simulation time 2666093200 ps
CPU time 5.97 seconds
Started Mar 07 02:43:27 PM PST 24
Finished Mar 07 02:43:33 PM PST 24
Peak memory 223932 kb
Host smart-6d12f348-960a-4916-9359-5d262c3fc7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074193033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4074193033
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.64681018
Short name T1328
Test name
Test status
Simulation time 1418787960 ps
CPU time 5.08 seconds
Started Mar 07 12:41:49 PM PST 24
Finished Mar 07 12:41:55 PM PST 24
Peak memory 233624 kb
Host smart-9ce7413f-66e1-4cbf-9c94-fc6972ccb533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64681018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.64681018
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1935837957
Short name T64
Test name
Test status
Simulation time 30619445 ps
CPU time 0.75 seconds
Started Mar 07 12:41:40 PM PST 24
Finished Mar 07 12:41:41 PM PST 24
Peak memory 216116 kb
Host smart-8a631bf3-0509-4765-9f21-1d7b7d3758b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935837957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1935837957
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2789030998
Short name T775
Test name
Test status
Simulation time 16786645 ps
CPU time 0.81 seconds
Started Mar 07 02:43:26 PM PST 24
Finished Mar 07 02:43:27 PM PST 24
Peak memory 215620 kb
Host smart-164e34ca-3e0e-41a4-8673-fffe843069f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789030998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2789030998
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2954212457
Short name T1891
Test name
Test status
Simulation time 487215249 ps
CPU time 3.98 seconds
Started Mar 07 02:43:34 PM PST 24
Finished Mar 07 02:43:38 PM PST 24
Peak memory 219832 kb
Host smart-2bef419a-874d-4a7f-86c7-cf832ac30fcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2954212457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2954212457
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.503900553
Short name T1009
Test name
Test status
Simulation time 1368889726 ps
CPU time 6.4 seconds
Started Mar 07 12:41:50 PM PST 24
Finished Mar 07 12:41:56 PM PST 24
Peak memory 221584 kb
Host smart-2ef28326-90ec-4266-965c-58c064b35020
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=503900553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.503900553
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3023809533
Short name T627
Test name
Test status
Simulation time 6671494098 ps
CPU time 36.81 seconds
Started Mar 07 12:41:50 PM PST 24
Finished Mar 07 12:42:27 PM PST 24
Peak memory 216320 kb
Host smart-3ac7f13e-75e7-41d9-a66d-8056760a1960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023809533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3023809533
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4194822673
Short name T607
Test name
Test status
Simulation time 7635283515 ps
CPU time 19.14 seconds
Started Mar 07 02:43:28 PM PST 24
Finished Mar 07 02:43:47 PM PST 24
Peak memory 215816 kb
Host smart-d4f8cf1c-e77f-4e6f-8cae-52814aa7ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194822673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4194822673
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3343269692
Short name T1670
Test name
Test status
Simulation time 1692087238 ps
CPU time 10.69 seconds
Started Mar 07 12:41:40 PM PST 24
Finished Mar 07 12:41:51 PM PST 24
Peak memory 216108 kb
Host smart-e3e6e86f-aac0-4ec3-bcd6-4604d414e7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343269692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3343269692
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.442117372
Short name T522
Test name
Test status
Simulation time 1191523862 ps
CPU time 8.47 seconds
Started Mar 07 02:43:28 PM PST 24
Finished Mar 07 02:43:36 PM PST 24
Peak memory 215736 kb
Host smart-b4bf3cdd-d797-40c4-8210-d86dc672f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442117372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.442117372
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1425471161
Short name T1241
Test name
Test status
Simulation time 86005726 ps
CPU time 0.99 seconds
Started Mar 07 12:41:51 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 207864 kb
Host smart-6b00df00-1401-4c57-869e-2d4e289249cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425471161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1425471161
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2580459287
Short name T380
Test name
Test status
Simulation time 296536927 ps
CPU time 3.28 seconds
Started Mar 07 02:43:26 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 215712 kb
Host smart-fec102de-5951-451e-b02a-4e9ef197c1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580459287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2580459287
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.205438334
Short name T1233
Test name
Test status
Simulation time 102119865 ps
CPU time 0.77 seconds
Started Mar 07 02:43:26 PM PST 24
Finished Mar 07 02:43:27 PM PST 24
Peak memory 204852 kb
Host smart-232f4173-86bd-435d-9894-b67f76e3b630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205438334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.205438334
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4280054902
Short name T6
Test name
Test status
Simulation time 52340305 ps
CPU time 0.83 seconds
Started Mar 07 12:41:50 PM PST 24
Finished Mar 07 12:41:51 PM PST 24
Peak memory 205428 kb
Host smart-4ce7b7cc-ce67-4d2c-8651-dc2b902c6da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280054902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4280054902
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.228275128
Short name T905
Test name
Test status
Simulation time 31865566712 ps
CPU time 24 seconds
Started Mar 07 02:43:31 PM PST 24
Finished Mar 07 02:43:56 PM PST 24
Peak memory 237368 kb
Host smart-56128d23-6284-41ca-908c-ea3ae90d195b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228275128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.228275128
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_upload.2481728274
Short name T764
Test name
Test status
Simulation time 57895724398 ps
CPU time 33.15 seconds
Started Mar 07 12:41:49 PM PST 24
Finished Mar 07 12:42:23 PM PST 24
Peak memory 238844 kb
Host smart-f88c4ca2-baf5-49c9-a882-945ae433a98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481728274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2481728274
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1345051947
Short name T418
Test name
Test status
Simulation time 61163854 ps
CPU time 0.75 seconds
Started Mar 07 12:41:56 PM PST 24
Finished Mar 07 12:41:57 PM PST 24
Peak memory 204528 kb
Host smart-54b1387b-a859-4cb0-b387-30f0c718fb46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345051947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1345051947
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2844845140
Short name T741
Test name
Test status
Simulation time 12254414 ps
CPU time 0.73 seconds
Started Mar 07 02:43:44 PM PST 24
Finished Mar 07 02:43:45 PM PST 24
Peak memory 204356 kb
Host smart-a331171f-b4c1-4d79-9145-574ca11ae4d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844845140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2844845140
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3066099297
Short name T1551
Test name
Test status
Simulation time 4039925032 ps
CPU time 13.7 seconds
Started Mar 07 12:41:56 PM PST 24
Finished Mar 07 12:42:10 PM PST 24
Peak memory 233820 kb
Host smart-2e432397-c19c-451c-9e7b-a5f4a3e4aa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066099297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3066099297
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.477834563
Short name T125
Test name
Test status
Simulation time 528326686 ps
CPU time 4.47 seconds
Started Mar 07 02:43:44 PM PST 24
Finished Mar 07 02:43:49 PM PST 24
Peak memory 232968 kb
Host smart-8dc88ee2-a9b2-430e-8470-0189aad01cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477834563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.477834563
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1209257865
Short name T575
Test name
Test status
Simulation time 44270745 ps
CPU time 0.8 seconds
Started Mar 07 02:43:35 PM PST 24
Finished Mar 07 02:43:36 PM PST 24
Peak memory 204496 kb
Host smart-df98b390-a585-4a9b-93ba-826620570ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209257865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1209257865
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3143623876
Short name T1081
Test name
Test status
Simulation time 49171447 ps
CPU time 0.72 seconds
Started Mar 07 12:41:48 PM PST 24
Finished Mar 07 12:41:49 PM PST 24
Peak memory 205284 kb
Host smart-5e778a2a-0a81-4854-b6f5-b039811fcab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143623876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3143623876
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1640992663
Short name T927
Test name
Test status
Simulation time 37156610894 ps
CPU time 177.73 seconds
Started Mar 07 12:41:48 PM PST 24
Finished Mar 07 12:44:46 PM PST 24
Peak memory 256376 kb
Host smart-22e372eb-7b4c-4efa-a79b-88bc7de72feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640992663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1640992663
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2343892284
Short name T301
Test name
Test status
Simulation time 4395539913 ps
CPU time 57.38 seconds
Started Mar 07 02:43:42 PM PST 24
Finished Mar 07 02:44:39 PM PST 24
Peak memory 256144 kb
Host smart-183d437b-f84e-4dac-b931-c05745056883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343892284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2343892284
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2155545766
Short name T910
Test name
Test status
Simulation time 9683699081 ps
CPU time 87.81 seconds
Started Mar 07 02:43:43 PM PST 24
Finished Mar 07 02:45:12 PM PST 24
Peak memory 250692 kb
Host smart-846543f6-2312-47e8-abe6-e9148d7ae426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155545766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2155545766
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.714365900
Short name T1735
Test name
Test status
Simulation time 688356293990 ps
CPU time 368.53 seconds
Started Mar 07 12:41:50 PM PST 24
Finished Mar 07 12:47:59 PM PST 24
Peak memory 269688 kb
Host smart-eceb75bf-b2f9-4a73-a438-ed9f1951fb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714365900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.714365900
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1909774785
Short name T1625
Test name
Test status
Simulation time 733838794691 ps
CPU time 348.73 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:47:42 PM PST 24
Peak memory 249256 kb
Host smart-9fdae8da-25d6-4497-afd2-5de29530ce59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909774785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1909774785
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3236328779
Short name T1299
Test name
Test status
Simulation time 43826690464 ps
CPU time 93.49 seconds
Started Mar 07 02:43:41 PM PST 24
Finished Mar 07 02:45:14 PM PST 24
Peak memory 262616 kb
Host smart-4eaee189-b700-4778-b526-ec6cf86c29bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236328779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3236328779
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1665762701
Short name T1661
Test name
Test status
Simulation time 5034933241 ps
CPU time 29.37 seconds
Started Mar 07 12:41:51 PM PST 24
Finished Mar 07 12:42:21 PM PST 24
Peak memory 233684 kb
Host smart-437d5be6-7cec-43a5-b043-5f81ae9408d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665762701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1665762701
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2570514360
Short name T1304
Test name
Test status
Simulation time 12167843862 ps
CPU time 38.04 seconds
Started Mar 07 02:43:39 PM PST 24
Finished Mar 07 02:44:17 PM PST 24
Peak memory 246260 kb
Host smart-9018ba2b-5c08-460c-9330-01bba3e9cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570514360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2570514360
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.212143974
Short name T490
Test name
Test status
Simulation time 224901811 ps
CPU time 3.4 seconds
Started Mar 07 02:43:40 PM PST 24
Finished Mar 07 02:43:44 PM PST 24
Peak memory 232784 kb
Host smart-282286dd-f7af-45ea-a02e-8ed5a5c9f195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212143974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.212143974
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3955829731
Short name T1838
Test name
Test status
Simulation time 1169728670 ps
CPU time 3.73 seconds
Started Mar 07 12:41:49 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 216772 kb
Host smart-948ef19c-ad7d-4aa6-8e44-e4a4e5730038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955829731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3955829731
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3949561508
Short name T1805
Test name
Test status
Simulation time 4411149141 ps
CPU time 22.43 seconds
Started Mar 07 02:43:41 PM PST 24
Finished Mar 07 02:44:04 PM PST 24
Peak memory 250892 kb
Host smart-5b2b52ec-e133-4bd7-a63a-0efa02862cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949561508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3949561508
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.53285031
Short name T1875
Test name
Test status
Simulation time 69984948493 ps
CPU time 48.13 seconds
Started Mar 07 12:41:51 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 239768 kb
Host smart-565adfb6-fa97-4c21-86cf-b2423d090d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53285031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.53285031
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.623584849
Short name T24
Test name
Test status
Simulation time 66023472 ps
CPU time 1.07 seconds
Started Mar 07 02:43:33 PM PST 24
Finished Mar 07 02:43:34 PM PST 24
Peak memory 216084 kb
Host smart-3ff3cb55-2060-466c-8eea-505fbc80cab6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623584849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.623584849
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2728635538
Short name T1430
Test name
Test status
Simulation time 1528755142 ps
CPU time 3.43 seconds
Started Mar 07 02:43:39 PM PST 24
Finished Mar 07 02:43:42 PM PST 24
Peak memory 235132 kb
Host smart-788fe116-7dbd-484a-81cf-9f0f1b5bc7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728635538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2728635538
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3660367618
Short name T1056
Test name
Test status
Simulation time 11247455519 ps
CPU time 11.18 seconds
Started Mar 07 12:41:48 PM PST 24
Finished Mar 07 12:42:00 PM PST 24
Peak memory 235592 kb
Host smart-16ab60d7-70b5-409c-a94f-756507200cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660367618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3660367618
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.112624030
Short name T1854
Test name
Test status
Simulation time 2273614309 ps
CPU time 16.63 seconds
Started Mar 07 12:41:48 PM PST 24
Finished Mar 07 12:42:05 PM PST 24
Peak memory 234968 kb
Host smart-d8840408-93e9-4271-b2fa-9d0eb6bd7434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112624030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.112624030
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3746543619
Short name T751
Test name
Test status
Simulation time 30237188280 ps
CPU time 37.54 seconds
Started Mar 07 02:43:43 PM PST 24
Finished Mar 07 02:44:21 PM PST 24
Peak memory 228828 kb
Host smart-e7f1ba02-2240-448e-a2f4-21132336c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746543619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3746543619
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3782194464
Short name T660
Test name
Test status
Simulation time 35150450 ps
CPU time 0.73 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 216148 kb
Host smart-2b540bf5-6b50-4f9e-a2b1-56415f1304ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782194464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3782194464
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.4134613869
Short name T1150
Test name
Test status
Simulation time 45868936 ps
CPU time 0.71 seconds
Started Mar 07 02:43:43 PM PST 24
Finished Mar 07 02:43:44 PM PST 24
Peak memory 215644 kb
Host smart-f9ac15c7-dbf4-4202-84ab-c43d2538b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134613869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.4134613869
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1865103874
Short name T1124
Test name
Test status
Simulation time 19332863159 ps
CPU time 5.83 seconds
Started Mar 07 02:43:49 PM PST 24
Finished Mar 07 02:43:55 PM PST 24
Peak memory 217732 kb
Host smart-4160c1ed-f1b2-48c6-939d-bb353177cf83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1865103874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1865103874
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2050297226
Short name T52
Test name
Test status
Simulation time 222462112 ps
CPU time 3.42 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:41:55 PM PST 24
Peak memory 218640 kb
Host smart-74572026-cb59-460e-a836-c22611d1c952
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2050297226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2050297226
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2808190274
Short name T1221
Test name
Test status
Simulation time 138747577 ps
CPU time 1 seconds
Started Mar 07 02:43:40 PM PST 24
Finished Mar 07 02:43:41 PM PST 24
Peak memory 205892 kb
Host smart-377f2e61-dbf1-482b-8277-1394553d4e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808190274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2808190274
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2999452340
Short name T157
Test name
Test status
Simulation time 3241319926 ps
CPU time 36.51 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:42:28 PM PST 24
Peak memory 236204 kb
Host smart-956f7af2-3180-469d-ab08-faea7f49586d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999452340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2999452340
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.272970238
Short name T813
Test name
Test status
Simulation time 78397502449 ps
CPU time 29.35 seconds
Started Mar 07 12:41:50 PM PST 24
Finished Mar 07 12:42:19 PM PST 24
Peak memory 216200 kb
Host smart-233084ee-8d8c-48fb-8031-d17dac0efb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272970238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.272970238
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3241252577
Short name T731
Test name
Test status
Simulation time 29444550546 ps
CPU time 46.84 seconds
Started Mar 07 02:43:41 PM PST 24
Finished Mar 07 02:44:28 PM PST 24
Peak memory 215820 kb
Host smart-a97b3629-88c2-4d35-858d-c6026b846a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241252577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3241252577
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2436458299
Short name T353
Test name
Test status
Simulation time 6427011796 ps
CPU time 16.21 seconds
Started Mar 07 12:41:50 PM PST 24
Finished Mar 07 12:42:06 PM PST 24
Peak memory 216172 kb
Host smart-e10afa93-5a36-4999-872d-1d08b7161511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436458299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2436458299
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3479754496
Short name T409
Test name
Test status
Simulation time 3690435883 ps
CPU time 5 seconds
Started Mar 07 02:43:40 PM PST 24
Finished Mar 07 02:43:45 PM PST 24
Peak memory 215784 kb
Host smart-9a7d1116-2d75-4e21-8e16-9851a5d2566d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479754496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3479754496
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4196350571
Short name T1253
Test name
Test status
Simulation time 57729296 ps
CPU time 0.99 seconds
Started Mar 07 02:43:41 PM PST 24
Finished Mar 07 02:43:43 PM PST 24
Peak memory 205912 kb
Host smart-8ef2be39-c106-4d08-a72f-a7c2a4f529d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196350571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4196350571
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4288185439
Short name T372
Test name
Test status
Simulation time 1350326472 ps
CPU time 2.5 seconds
Started Mar 07 12:41:51 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 216324 kb
Host smart-d3b55463-3217-4a9f-a2da-b23ed7ac4d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288185439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4288185439
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1373238985
Short name T862
Test name
Test status
Simulation time 13383517 ps
CPU time 0.71 seconds
Started Mar 07 02:43:39 PM PST 24
Finished Mar 07 02:43:40 PM PST 24
Peak memory 204848 kb
Host smart-a3d89b0e-277b-46aa-bbb4-3c384d63c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373238985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1373238985
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3129900934
Short name T1510
Test name
Test status
Simulation time 478697594 ps
CPU time 0.93 seconds
Started Mar 07 12:41:51 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 206532 kb
Host smart-a8058bca-6538-4127-9c59-ba974812900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129900934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3129900934
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1419547745
Short name T1210
Test name
Test status
Simulation time 1421917634 ps
CPU time 6.89 seconds
Started Mar 07 02:43:44 PM PST 24
Finished Mar 07 02:43:51 PM PST 24
Peak memory 218068 kb
Host smart-63aae824-ffce-4358-b71f-70531d450003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419547745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1419547745
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_upload.2504344549
Short name T1214
Test name
Test status
Simulation time 4155094696 ps
CPU time 5.09 seconds
Started Mar 07 12:41:50 PM PST 24
Finished Mar 07 12:41:56 PM PST 24
Peak memory 217556 kb
Host smart-281bdcbb-541c-4fe9-b426-1fa884103220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504344549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2504344549
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1698579233
Short name T718
Test name
Test status
Simulation time 91591169 ps
CPU time 0.72 seconds
Started Mar 07 12:41:56 PM PST 24
Finished Mar 07 12:41:57 PM PST 24
Peak memory 205092 kb
Host smart-522247b8-d9bf-4eff-baed-7f5189d5e100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698579233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1698579233
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2027383326
Short name T398
Test name
Test status
Simulation time 19274449 ps
CPU time 0.68 seconds
Started Mar 07 02:43:50 PM PST 24
Finished Mar 07 02:43:50 PM PST 24
Peak memory 204432 kb
Host smart-82323da1-e29a-4e0c-bf1b-d6eb218e3af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027383326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2027383326
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2042201001
Short name T80
Test name
Test status
Simulation time 1128514271 ps
CPU time 3.74 seconds
Started Mar 07 02:43:51 PM PST 24
Finished Mar 07 02:43:55 PM PST 24
Peak memory 232840 kb
Host smart-55a1338b-def5-40fc-a093-6e8153fe10fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042201001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2042201001
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.610174287
Short name T258
Test name
Test status
Simulation time 1684442486 ps
CPU time 4.72 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:41:58 PM PST 24
Peak memory 233824 kb
Host smart-884baaf1-9ec7-4407-b459-b6719c90509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610174287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.610174287
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2689418171
Short name T1367
Test name
Test status
Simulation time 31523921 ps
CPU time 0.82 seconds
Started Mar 07 02:43:40 PM PST 24
Finished Mar 07 02:43:42 PM PST 24
Peak memory 205844 kb
Host smart-536d3463-7a68-4040-a55b-005507558230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689418171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2689418171
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.367670783
Short name T1832
Test name
Test status
Simulation time 59576640 ps
CPU time 0.79 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 206200 kb
Host smart-35f0cb90-05be-4b05-8ede-9e63bda4a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367670783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.367670783
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1597302817
Short name T1235
Test name
Test status
Simulation time 138925595829 ps
CPU time 142.44 seconds
Started Mar 07 02:43:52 PM PST 24
Finished Mar 07 02:46:15 PM PST 24
Peak memory 272996 kb
Host smart-7e4a3b0c-0be5-43ae-bffd-5c9647b2fa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597302817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1597302817
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3370176831
Short name T1907
Test name
Test status
Simulation time 36433110503 ps
CPU time 131.24 seconds
Started Mar 07 12:41:51 PM PST 24
Finished Mar 07 12:44:03 PM PST 24
Peak memory 249096 kb
Host smart-bfd1badd-3f1a-4ac1-a7db-5ed2eeae565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370176831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3370176831
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3494044127
Short name T1352
Test name
Test status
Simulation time 3679818857 ps
CPU time 70.36 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:43:02 PM PST 24
Peak memory 250060 kb
Host smart-852fe6ff-6783-49c0-837a-2bbbf70ff389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494044127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3494044127
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3546102934
Short name T193
Test name
Test status
Simulation time 167710774845 ps
CPU time 593.67 seconds
Started Mar 07 02:43:53 PM PST 24
Finished Mar 07 02:53:47 PM PST 24
Peak memory 265228 kb
Host smart-b27415d5-84c9-414e-a07a-1add3a650183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546102934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3546102934
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2430357284
Short name T1659
Test name
Test status
Simulation time 4661010938 ps
CPU time 30.03 seconds
Started Mar 07 02:43:49 PM PST 24
Finished Mar 07 02:44:20 PM PST 24
Peak memory 234376 kb
Host smart-2a77aa2c-39a3-494a-b9e0-35f54f347807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430357284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2430357284
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2657907398
Short name T304
Test name
Test status
Simulation time 8335949514 ps
CPU time 102.16 seconds
Started Mar 07 12:41:56 PM PST 24
Finished Mar 07 12:43:38 PM PST 24
Peak memory 266704 kb
Host smart-620e06c4-1a9f-4bc7-9efe-818da20ca11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657907398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2657907398
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1587252377
Short name T428
Test name
Test status
Simulation time 3657503670 ps
CPU time 26.95 seconds
Started Mar 07 02:43:49 PM PST 24
Finished Mar 07 02:44:16 PM PST 24
Peak memory 256356 kb
Host smart-9b93c44b-8242-482d-9d6e-a9564d24f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587252377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1587252377
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3270911874
Short name T820
Test name
Test status
Simulation time 1100422857 ps
CPU time 7.86 seconds
Started Mar 07 12:41:54 PM PST 24
Finished Mar 07 12:42:02 PM PST 24
Peak memory 234764 kb
Host smart-ddd0b475-c5a7-4812-8962-70bb28c89d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270911874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3270911874
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3248693152
Short name T735
Test name
Test status
Simulation time 5477437913 ps
CPU time 3.95 seconds
Started Mar 07 02:43:49 PM PST 24
Finished Mar 07 02:43:53 PM PST 24
Peak memory 217280 kb
Host smart-20755805-15b6-41a3-abcc-7e89e4611644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248693152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3248693152
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intercept.403132565
Short name T709
Test name
Test status
Simulation time 10958726029 ps
CPU time 10.78 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:42:04 PM PST 24
Peak memory 233688 kb
Host smart-3f4ffe73-9cc3-4b03-a52c-0013574c1fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403132565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.403132565
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2414326614
Short name T906
Test name
Test status
Simulation time 6065146098 ps
CPU time 19.13 seconds
Started Mar 07 12:41:49 PM PST 24
Finished Mar 07 12:42:08 PM PST 24
Peak memory 240872 kb
Host smart-bbcc25e4-54f4-4a12-a6f0-f0f5d9f4558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414326614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2414326614
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3260800930
Short name T695
Test name
Test status
Simulation time 2220448573 ps
CPU time 16.04 seconds
Started Mar 07 02:43:50 PM PST 24
Finished Mar 07 02:44:06 PM PST 24
Peak memory 248424 kb
Host smart-8aec2842-4942-4d4b-bd59-18ad8695ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260800930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3260800930
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.550612673
Short name T595
Test name
Test status
Simulation time 28135329 ps
CPU time 0.99 seconds
Started Mar 07 02:43:45 PM PST 24
Finished Mar 07 02:43:47 PM PST 24
Peak memory 217292 kb
Host smart-6f83f6f9-9ea0-4ca7-88b4-01c84fe18312
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550612673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.550612673
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1227115674
Short name T1756
Test name
Test status
Simulation time 106343025 ps
CPU time 2.8 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:41:56 PM PST 24
Peak memory 233456 kb
Host smart-a333fc06-82fa-414d-a6a4-a9e30c8747c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227115674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1227115674
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1632135067
Short name T1031
Test name
Test status
Simulation time 5223889190 ps
CPU time 7.76 seconds
Started Mar 07 02:43:42 PM PST 24
Finished Mar 07 02:43:50 PM PST 24
Peak memory 217880 kb
Host smart-9dcc60c5-1d02-4235-93bc-14c6d4d5ccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632135067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1632135067
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1603711217
Short name T1313
Test name
Test status
Simulation time 105514248823 ps
CPU time 26.85 seconds
Started Mar 07 02:43:40 PM PST 24
Finished Mar 07 02:44:07 PM PST 24
Peak memory 234584 kb
Host smart-5692930d-8bc8-46a8-83b2-f504effb014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603711217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1603711217
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2471928526
Short name T654
Test name
Test status
Simulation time 17826483033 ps
CPU time 13.12 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:42:05 PM PST 24
Peak memory 216704 kb
Host smart-cc0811f4-96ca-453c-94c6-74f526d87218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471928526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2471928526
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.26286457
Short name T826
Test name
Test status
Simulation time 18252560 ps
CPU time 0.81 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:41:54 PM PST 24
Peak memory 216128 kb
Host smart-43cb7e68-5d6a-4a02-8537-573803c47754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26286457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.26286457
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.2880558440
Short name T1741
Test name
Test status
Simulation time 24143613 ps
CPU time 0.78 seconds
Started Mar 07 02:43:43 PM PST 24
Finished Mar 07 02:43:44 PM PST 24
Peak memory 215576 kb
Host smart-42922a37-14fd-4401-b5fa-ac8c8cabec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880558440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.2880558440
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1869835841
Short name T12
Test name
Test status
Simulation time 1298362316 ps
CPU time 6.23 seconds
Started Mar 07 02:43:48 PM PST 24
Finished Mar 07 02:43:54 PM PST 24
Peak memory 221520 kb
Host smart-3ca8cb28-0917-4a52-8656-64b7890d09ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1869835841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1869835841
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4141941286
Short name T587
Test name
Test status
Simulation time 557848900 ps
CPU time 4.52 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:41:57 PM PST 24
Peak memory 220352 kb
Host smart-311d8635-a122-4431-9911-b3ba599dcb9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4141941286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4141941286
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1090178833
Short name T1452
Test name
Test status
Simulation time 49040974919 ps
CPU time 321.47 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:47:13 PM PST 24
Peak memory 261972 kb
Host smart-d601d42b-8f34-43b0-82d6-1eb67d446135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090178833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1090178833
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2100426091
Short name T790
Test name
Test status
Simulation time 22938784902 ps
CPU time 104.02 seconds
Started Mar 07 02:43:50 PM PST 24
Finished Mar 07 02:45:34 PM PST 24
Peak memory 254360 kb
Host smart-dc97baff-ce71-4902-912d-bc2c74c939dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100426091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2100426091
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2526832059
Short name T1021
Test name
Test status
Simulation time 3746892134 ps
CPU time 17.42 seconds
Started Mar 07 02:43:39 PM PST 24
Finished Mar 07 02:43:57 PM PST 24
Peak memory 215776 kb
Host smart-34015977-2d6d-4e9a-a227-768a05983d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526832059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2526832059
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.395971409
Short name T1190
Test name
Test status
Simulation time 8315568708 ps
CPU time 11.67 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:42:05 PM PST 24
Peak memory 216284 kb
Host smart-b35cb39b-6c2c-4bd6-8d5c-f236f3b32e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395971409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.395971409
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1048429859
Short name T376
Test name
Test status
Simulation time 34502091007 ps
CPU time 27.79 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:42:21 PM PST 24
Peak memory 216212 kb
Host smart-894dcdab-9f5c-48ff-acf9-7982d6d6ec14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048429859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1048429859
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2543788490
Short name T1699
Test name
Test status
Simulation time 60049197005 ps
CPU time 21.58 seconds
Started Mar 07 02:43:41 PM PST 24
Finished Mar 07 02:44:03 PM PST 24
Peak memory 215788 kb
Host smart-922a08c3-462a-4e07-9400-7fd594b7911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543788490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2543788490
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3796960151
Short name T526
Test name
Test status
Simulation time 237141493 ps
CPU time 3.52 seconds
Started Mar 07 02:43:40 PM PST 24
Finished Mar 07 02:43:43 PM PST 24
Peak memory 215728 kb
Host smart-9043486a-20e9-4d0d-bfca-ad1c5437f7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796960151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3796960151
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3911292472
Short name T517
Test name
Test status
Simulation time 1176942704 ps
CPU time 11.21 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:42:04 PM PST 24
Peak memory 216096 kb
Host smart-0d23a096-33ae-4431-bbae-239aeae8d677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911292472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3911292472
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1573360221
Short name T1703
Test name
Test status
Simulation time 44913194 ps
CPU time 0.79 seconds
Started Mar 07 12:41:54 PM PST 24
Finished Mar 07 12:41:55 PM PST 24
Peak memory 205340 kb
Host smart-4861a8be-fde3-451d-a286-b62bc06a8e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573360221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1573360221
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.23741597
Short name T616
Test name
Test status
Simulation time 30565538 ps
CPU time 0.79 seconds
Started Mar 07 02:43:41 PM PST 24
Finished Mar 07 02:43:42 PM PST 24
Peak memory 204876 kb
Host smart-4b307481-1561-4242-bc39-287f9c21943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23741597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.23741597
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2462074141
Short name T1511
Test name
Test status
Simulation time 23948100151 ps
CPU time 31.63 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 230252 kb
Host smart-51ce4273-f269-4d4e-b9ec-24661da8be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462074141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2462074141
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_upload.2814281366
Short name T919
Test name
Test status
Simulation time 241349862 ps
CPU time 3.47 seconds
Started Mar 07 02:43:49 PM PST 24
Finished Mar 07 02:43:53 PM PST 24
Peak memory 218172 kb
Host smart-2337e597-3ec0-48d5-bba3-33c74b4c1807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814281366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2814281366
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2536429801
Short name T51
Test name
Test status
Simulation time 63030720 ps
CPU time 0.69 seconds
Started Mar 07 12:42:08 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 205200 kb
Host smart-7610a4c7-0e91-4182-b324-68ee2d6bee69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536429801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2536429801
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2776979842
Short name T1271
Test name
Test status
Simulation time 42651119 ps
CPU time 0.71 seconds
Started Mar 07 02:43:51 PM PST 24
Finished Mar 07 02:43:52 PM PST 24
Peak memory 204376 kb
Host smart-d0c8701b-b4e6-43b6-817d-22d9e827d736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776979842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2776979842
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2508116362
Short name T224
Test name
Test status
Simulation time 1653076838 ps
CPU time 4.29 seconds
Started Mar 07 12:41:57 PM PST 24
Finished Mar 07 12:42:01 PM PST 24
Peak memory 224460 kb
Host smart-4a6d6e9d-79d8-4abf-8fba-5b7d6a1b2d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508116362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2508116362
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3940145015
Short name T783
Test name
Test status
Simulation time 224680115 ps
CPU time 3.35 seconds
Started Mar 07 02:43:50 PM PST 24
Finished Mar 07 02:43:54 PM PST 24
Peak memory 233108 kb
Host smart-8d8018be-1e16-491f-969c-1da4b45ed43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940145015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3940145015
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.736957754
Short name T491
Test name
Test status
Simulation time 46654174 ps
CPU time 0.7 seconds
Started Mar 07 02:43:47 PM PST 24
Finished Mar 07 02:43:48 PM PST 24
Peak memory 205864 kb
Host smart-3ec081a0-5d9c-463d-82b2-878b6c0944e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736957754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.736957754
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.920409488
Short name T19
Test name
Test status
Simulation time 52778558 ps
CPU time 0.77 seconds
Started Mar 07 12:41:54 PM PST 24
Finished Mar 07 12:41:55 PM PST 24
Peak memory 206604 kb
Host smart-d9ef3bb2-b890-420a-ac18-7f708610f17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920409488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.920409488
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.78468389
Short name T1428
Test name
Test status
Simulation time 14089485691 ps
CPU time 56.97 seconds
Started Mar 07 12:41:55 PM PST 24
Finished Mar 07 12:42:53 PM PST 24
Peak memory 257276 kb
Host smart-126f21ca-eced-4ba2-b315-8142c717fd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78468389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.78468389
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.858652174
Short name T1187
Test name
Test status
Simulation time 357883617556 ps
CPU time 397.02 seconds
Started Mar 07 02:43:50 PM PST 24
Finished Mar 07 02:50:27 PM PST 24
Peak memory 256716 kb
Host smart-36ff4a57-2ba1-4d2f-aed0-770185ff84b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858652174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.858652174
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3996099050
Short name T1249
Test name
Test status
Simulation time 180124033574 ps
CPU time 146.31 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:44:19 PM PST 24
Peak memory 235752 kb
Host smart-3127757a-88b7-4e14-abe3-d181c4fdca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996099050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3996099050
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.514192081
Short name T44
Test name
Test status
Simulation time 21468854352 ps
CPU time 86.08 seconds
Started Mar 07 02:43:49 PM PST 24
Finished Mar 07 02:45:15 PM PST 24
Peak memory 248624 kb
Host smart-3706d071-d041-40a0-b7c0-6bb284a8f170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514192081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.514192081
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3513001455
Short name T1605
Test name
Test status
Simulation time 195940297369 ps
CPU time 318.06 seconds
Started Mar 07 02:43:50 PM PST 24
Finished Mar 07 02:49:08 PM PST 24
Peak memory 249696 kb
Host smart-67947988-29b4-44f5-9537-a357d863f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513001455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3513001455
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3519107622
Short name T1041
Test name
Test status
Simulation time 5286308986 ps
CPU time 93.27 seconds
Started Mar 07 12:42:05 PM PST 24
Finished Mar 07 12:43:39 PM PST 24
Peak memory 251620 kb
Host smart-f2204b7f-785a-4dd9-974a-cc24e5775adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519107622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3519107622
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1892036016
Short name T1351
Test name
Test status
Simulation time 39813445773 ps
CPU time 53.62 seconds
Started Mar 07 12:41:54 PM PST 24
Finished Mar 07 12:42:47 PM PST 24
Peak memory 240280 kb
Host smart-35006315-3c5a-44b9-a4be-9e4a3860934b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892036016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1892036016
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.303414685
Short name T697
Test name
Test status
Simulation time 20191350568 ps
CPU time 36.45 seconds
Started Mar 07 02:43:51 PM PST 24
Finished Mar 07 02:44:27 PM PST 24
Peak memory 239204 kb
Host smart-20dd5538-c102-458c-98a7-7952c4aa077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303414685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.303414685
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3173263442
Short name T200
Test name
Test status
Simulation time 11297201354 ps
CPU time 10.35 seconds
Started Mar 07 02:43:52 PM PST 24
Finished Mar 07 02:44:03 PM PST 24
Peak memory 233988 kb
Host smart-566b0360-f231-418f-a343-40933c6e079e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173263442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3173263442
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3216147147
Short name T217
Test name
Test status
Simulation time 396027251 ps
CPU time 4.2 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:41:58 PM PST 24
Peak memory 218524 kb
Host smart-6ae92eaf-18a9-4f8a-a7c1-4567016ae302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216147147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3216147147
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1615958548
Short name T999
Test name
Test status
Simulation time 6416493247 ps
CPU time 12.12 seconds
Started Mar 07 02:43:50 PM PST 24
Finished Mar 07 02:44:02 PM PST 24
Peak memory 240288 kb
Host smart-e6c74948-9dff-44b8-a57c-ef3b0f940958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615958548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1615958548
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3518004835
Short name T1019
Test name
Test status
Simulation time 14096149851 ps
CPU time 14.94 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:42:07 PM PST 24
Peak memory 235080 kb
Host smart-e59b2683-a5a2-487d-a5f1-aa098cccc94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518004835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3518004835
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1517925977
Short name T1868
Test name
Test status
Simulation time 36235259 ps
CPU time 1.11 seconds
Started Mar 07 02:43:50 PM PST 24
Finished Mar 07 02:43:51 PM PST 24
Peak memory 216036 kb
Host smart-320c473b-9a31-48e3-aab9-d8c44977575c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517925977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1517925977
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.180805574
Short name T1693
Test name
Test status
Simulation time 6780422156 ps
CPU time 23.58 seconds
Started Mar 07 12:41:54 PM PST 24
Finished Mar 07 12:42:17 PM PST 24
Peak memory 240760 kb
Host smart-f9f17004-a07c-42c9-8065-7d41ea635030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180805574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.180805574
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4249528857
Short name T687
Test name
Test status
Simulation time 2328854096 ps
CPU time 5.47 seconds
Started Mar 07 02:43:51 PM PST 24
Finished Mar 07 02:43:56 PM PST 24
Peak memory 232148 kb
Host smart-10eaf04b-e5cf-46c4-8137-e8f804a02c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249528857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4249528857
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1064332474
Short name T685
Test name
Test status
Simulation time 659293549 ps
CPU time 6.16 seconds
Started Mar 07 12:41:56 PM PST 24
Finished Mar 07 12:42:02 PM PST 24
Peak memory 233568 kb
Host smart-2a3b5d14-491f-4621-b3c9-3024cda4f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064332474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1064332474
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2826288348
Short name T981
Test name
Test status
Simulation time 10133265265 ps
CPU time 29.1 seconds
Started Mar 07 02:43:48 PM PST 24
Finished Mar 07 02:44:18 PM PST 24
Peak memory 232044 kb
Host smart-55a95f61-01e5-46de-ae9c-88e70705c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826288348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2826288348
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2722741438
Short name T1507
Test name
Test status
Simulation time 19708021 ps
CPU time 0.78 seconds
Started Mar 07 12:41:55 PM PST 24
Finished Mar 07 12:41:56 PM PST 24
Peak memory 216124 kb
Host smart-0132e247-5fc8-448f-8285-879ce1094b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722741438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2722741438
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2885239443
Short name T391
Test name
Test status
Simulation time 262167987 ps
CPU time 3.36 seconds
Started Mar 07 12:41:57 PM PST 24
Finished Mar 07 12:42:00 PM PST 24
Peak memory 218520 kb
Host smart-a18ece88-80df-44d7-aa1f-ed02cf54f940
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2885239443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2885239443
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4283979201
Short name T1024
Test name
Test status
Simulation time 5962434824 ps
CPU time 6.57 seconds
Started Mar 07 02:43:51 PM PST 24
Finished Mar 07 02:43:58 PM PST 24
Peak memory 222260 kb
Host smart-b72ccd49-50bb-46de-bb70-7909f8d3a573
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4283979201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4283979201
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2024567889
Short name T1758
Test name
Test status
Simulation time 3603017450 ps
CPU time 69.45 seconds
Started Mar 07 02:43:52 PM PST 24
Finished Mar 07 02:45:01 PM PST 24
Peak memory 249124 kb
Host smart-ceae5b63-3780-409b-afb2-19d5eaaf9493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024567889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2024567889
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3297963822
Short name T1449
Test name
Test status
Simulation time 2467043432 ps
CPU time 14.68 seconds
Started Mar 07 12:41:53 PM PST 24
Finished Mar 07 12:42:08 PM PST 24
Peak memory 216276 kb
Host smart-6755f093-1093-4255-b20c-66070223f022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297963822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3297963822
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4139914984
Short name T1841
Test name
Test status
Simulation time 6861626979 ps
CPU time 7.8 seconds
Started Mar 07 02:43:51 PM PST 24
Finished Mar 07 02:43:58 PM PST 24
Peak memory 215828 kb
Host smart-fb3afd22-0191-4118-a629-d0c543117245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139914984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4139914984
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2988097889
Short name T1456
Test name
Test status
Simulation time 23730795845 ps
CPU time 24.58 seconds
Started Mar 07 02:43:51 PM PST 24
Finished Mar 07 02:44:15 PM PST 24
Peak memory 215812 kb
Host smart-15a14f72-8307-42b5-97ca-d9e236ea5b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988097889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2988097889
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.785124902
Short name T1656
Test name
Test status
Simulation time 1304843040 ps
CPU time 8.81 seconds
Started Mar 07 12:41:54 PM PST 24
Finished Mar 07 12:42:03 PM PST 24
Peak memory 216084 kb
Host smart-4ae6af0f-a8a5-4f70-bf3a-44bcea83f4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785124902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.785124902
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1100481828
Short name T1349
Test name
Test status
Simulation time 52837306 ps
CPU time 1.13 seconds
Started Mar 07 12:41:54 PM PST 24
Finished Mar 07 12:41:56 PM PST 24
Peak memory 207688 kb
Host smart-4c10b570-441e-400f-910e-5690c2dde3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100481828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1100481828
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.223042333
Short name T1205
Test name
Test status
Simulation time 238493352 ps
CPU time 3.56 seconds
Started Mar 07 02:43:48 PM PST 24
Finished Mar 07 02:43:52 PM PST 24
Peak memory 215732 kb
Host smart-20ea5aab-9f27-428d-a223-0aeac1fd9247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223042333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.223042333
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1165522384
Short name T342
Test name
Test status
Simulation time 24559332 ps
CPU time 0.77 seconds
Started Mar 07 02:43:49 PM PST 24
Finished Mar 07 02:43:50 PM PST 24
Peak memory 204892 kb
Host smart-58219cc1-a092-4ce6-93ce-0ce00d5b86be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165522384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1165522384
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3166034070
Short name T863
Test name
Test status
Simulation time 74583045 ps
CPU time 0.75 seconds
Started Mar 07 12:41:52 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 205488 kb
Host smart-17a1d9ab-ffaa-485f-9e7a-c43a40f53fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166034070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3166034070
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1293034264
Short name T197
Test name
Test status
Simulation time 8432342779 ps
CPU time 14.04 seconds
Started Mar 07 02:43:51 PM PST 24
Finished Mar 07 02:44:06 PM PST 24
Peak memory 233500 kb
Host smart-ec6d5314-3a17-42e2-a7fb-a4140347bcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293034264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1293034264
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_upload.4184723678
Short name T222
Test name
Test status
Simulation time 49880355278 ps
CPU time 34.78 seconds
Started Mar 07 12:41:54 PM PST 24
Finished Mar 07 12:42:29 PM PST 24
Peak memory 233036 kb
Host smart-16bb5576-beca-49b2-a9b4-53423f697026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184723678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4184723678
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2704823724
Short name T657
Test name
Test status
Simulation time 40674473 ps
CPU time 0.7 seconds
Started Mar 07 12:42:04 PM PST 24
Finished Mar 07 12:42:05 PM PST 24
Peak memory 205096 kb
Host smart-d5068141-551f-4886-8fd9-3dd39313579b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704823724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2704823724
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.47391617
Short name T480
Test name
Test status
Simulation time 15095602 ps
CPU time 0.74 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:01 PM PST 24
Peak memory 204456 kb
Host smart-ec176fb2-abcb-4f82-9fb8-061f7f65cd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47391617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.47391617
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1100642196
Short name T1783
Test name
Test status
Simulation time 512579303 ps
CPU time 5.73 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:06 PM PST 24
Peak memory 220112 kb
Host smart-687a07f9-3777-45cb-a1ff-f5e12fcf370e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100642196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1100642196
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2358149402
Short name T538
Test name
Test status
Simulation time 3887160497 ps
CPU time 5.74 seconds
Started Mar 07 12:42:05 PM PST 24
Finished Mar 07 12:42:11 PM PST 24
Peak memory 233488 kb
Host smart-33c467fa-d0bf-4fc1-b255-5929e37b1f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358149402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2358149402
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1702899165
Short name T422
Test name
Test status
Simulation time 50564085 ps
CPU time 0.84 seconds
Started Mar 07 02:43:58 PM PST 24
Finished Mar 07 02:43:58 PM PST 24
Peak memory 205532 kb
Host smart-b2f66b5a-b9a9-46b2-a95a-d8aa68b5fb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702899165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1702899165
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1777629419
Short name T1470
Test name
Test status
Simulation time 52104396 ps
CPU time 0.8 seconds
Started Mar 07 12:42:05 PM PST 24
Finished Mar 07 12:42:06 PM PST 24
Peak memory 206152 kb
Host smart-0acaff13-d1ea-4107-96d7-45c67908dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777629419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1777629419
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2857768985
Short name T1108
Test name
Test status
Simulation time 499111534752 ps
CPU time 327.93 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:49:28 PM PST 24
Peak memory 273104 kb
Host smart-0817219d-ea86-4367-be45-bb20a79534da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857768985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2857768985
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.568754136
Short name T789
Test name
Test status
Simulation time 10884847359 ps
CPU time 58.31 seconds
Started Mar 07 12:42:05 PM PST 24
Finished Mar 07 12:43:04 PM PST 24
Peak memory 264728 kb
Host smart-94ef40c4-da45-426c-b672-bc570cf9e2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568754136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.568754136
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1133100879
Short name T1702
Test name
Test status
Simulation time 11882079488 ps
CPU time 131.21 seconds
Started Mar 07 02:44:01 PM PST 24
Finished Mar 07 02:46:13 PM PST 24
Peak memory 264172 kb
Host smart-de5fde97-0d29-4e9b-abf1-75cb28828409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133100879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1133100879
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3732348948
Short name T49
Test name
Test status
Simulation time 288753071138 ps
CPU time 531.18 seconds
Started Mar 07 12:42:10 PM PST 24
Finished Mar 07 12:51:02 PM PST 24
Peak memory 267432 kb
Host smart-889a40da-7b46-4eaf-9b1f-4285abb4cf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732348948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3732348948
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2273660925
Short name T725
Test name
Test status
Simulation time 22951425408 ps
CPU time 85.35 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 249256 kb
Host smart-30bc78fc-0a9f-44ee-894d-bcf55e50fe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273660925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2273660925
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2899765679
Short name T1615
Test name
Test status
Simulation time 7414608894 ps
CPU time 143.43 seconds
Started Mar 07 02:43:58 PM PST 24
Finished Mar 07 02:46:21 PM PST 24
Peak memory 272584 kb
Host smart-f1f5cdda-d964-40dc-a058-ad71e59c71c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899765679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2899765679
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2466494332
Short name T839
Test name
Test status
Simulation time 19070307624 ps
CPU time 22 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:30 PM PST 24
Peak memory 232708 kb
Host smart-af88f502-4880-483f-b320-338aa8826315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466494332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2466494332
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3475965077
Short name T1760
Test name
Test status
Simulation time 2142918469 ps
CPU time 6.98 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:07 PM PST 24
Peak memory 222964 kb
Host smart-4c35b0b2-919f-4e79-8867-844e65897c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475965077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3475965077
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1653410235
Short name T758
Test name
Test status
Simulation time 937992426 ps
CPU time 3.72 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:11 PM PST 24
Peak memory 233460 kb
Host smart-8b719d5a-29c4-4770-a686-2f780f303786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653410235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1653410235
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2902372789
Short name T1825
Test name
Test status
Simulation time 254095432 ps
CPU time 2.55 seconds
Started Mar 07 02:43:58 PM PST 24
Finished Mar 07 02:44:01 PM PST 24
Peak memory 232096 kb
Host smart-7630b240-79b0-4e44-9573-23b179545fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902372789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2902372789
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1542570634
Short name T1325
Test name
Test status
Simulation time 2162999131 ps
CPU time 6.65 seconds
Started Mar 07 02:43:59 PM PST 24
Finished Mar 07 02:44:06 PM PST 24
Peak memory 232052 kb
Host smart-2e51d6e8-0c28-4415-9cfd-9b87df787b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542570634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1542570634
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2544652754
Short name T896
Test name
Test status
Simulation time 9191477579 ps
CPU time 8.35 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:16 PM PST 24
Peak memory 217408 kb
Host smart-728d6b7c-797c-4c55-ba2c-1dfe505c74e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544652754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2544652754
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2786453859
Short name T973
Test name
Test status
Simulation time 27166286 ps
CPU time 1.05 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:01 PM PST 24
Peak memory 217260 kb
Host smart-f9908ddd-3004-4230-9325-952236568a46
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786453859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2786453859
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2937658186
Short name T1127
Test name
Test status
Simulation time 1334444269 ps
CPU time 9.84 seconds
Started Mar 07 02:44:03 PM PST 24
Finished Mar 07 02:44:13 PM PST 24
Peak memory 233044 kb
Host smart-a9ac9901-affb-4be1-a0dd-4e50b58766a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937658186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2937658186
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3976539973
Short name T207
Test name
Test status
Simulation time 244607189 ps
CPU time 3.92 seconds
Started Mar 07 12:42:10 PM PST 24
Finished Mar 07 12:42:14 PM PST 24
Peak memory 224428 kb
Host smart-be2b8d65-1781-46b9-8bba-1e4950baff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976539973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3976539973
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.165844399
Short name T661
Test name
Test status
Simulation time 331379608 ps
CPU time 3.5 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:03 PM PST 24
Peak memory 232732 kb
Host smart-801a0498-6ef8-47dc-849c-1852075172f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165844399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.165844399
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.852367488
Short name T983
Test name
Test status
Simulation time 16440891416 ps
CPU time 14.8 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:23 PM PST 24
Peak memory 240700 kb
Host smart-58277341-d242-4941-aa5f-331f2f92952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852367488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.852367488
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.3070243882
Short name T1835
Test name
Test status
Simulation time 27452388 ps
CPU time 0.76 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:00 PM PST 24
Peak memory 215544 kb
Host smart-548d2ea0-eec2-4d78-b598-f7e0435a44f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070243882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.3070243882
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.3486103252
Short name T1434
Test name
Test status
Simulation time 36592398 ps
CPU time 0.73 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:42:10 PM PST 24
Peak memory 216172 kb
Host smart-87cdbd9a-647e-4c41-9646-676c88f2b8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486103252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.3486103252
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2608368077
Short name T1348
Test name
Test status
Simulation time 240755788 ps
CPU time 3.29 seconds
Started Mar 07 12:42:05 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 221176 kb
Host smart-e772412e-70aa-48e7-ad0f-862167869733
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2608368077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2608368077
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3608573278
Short name T1771
Test name
Test status
Simulation time 1712558622 ps
CPU time 4.18 seconds
Started Mar 07 02:43:59 PM PST 24
Finished Mar 07 02:44:04 PM PST 24
Peak memory 218936 kb
Host smart-cf602c18-7fb0-48b6-b983-3cb54549ca0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3608573278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3608573278
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2512560540
Short name T1851
Test name
Test status
Simulation time 105953290055 ps
CPU time 354.78 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:48:04 PM PST 24
Peak memory 254564 kb
Host smart-aebe77c2-6660-4ba6-9ddf-8698c12cd6f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512560540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2512560540
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.293907351
Short name T309
Test name
Test status
Simulation time 175488509333 ps
CPU time 597.27 seconds
Started Mar 07 02:43:59 PM PST 24
Finished Mar 07 02:53:57 PM PST 24
Peak memory 265212 kb
Host smart-f0cb1cee-023d-4ea9-b682-2f1f2216d463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293907351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.293907351
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1150941803
Short name T1368
Test name
Test status
Simulation time 1493968145 ps
CPU time 13.19 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:21 PM PST 24
Peak memory 216180 kb
Host smart-c93ccc86-0ec1-4f0b-9deb-0182edb646c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150941803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1150941803
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4028754356
Short name T831
Test name
Test status
Simulation time 7790939279 ps
CPU time 28.13 seconds
Started Mar 07 02:43:58 PM PST 24
Finished Mar 07 02:44:26 PM PST 24
Peak memory 215800 kb
Host smart-fdae65a6-805b-4682-b348-6bb9c5f7ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028754356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4028754356
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1317276257
Short name T1521
Test name
Test status
Simulation time 1121622740 ps
CPU time 5.66 seconds
Started Mar 07 12:42:04 PM PST 24
Finished Mar 07 12:42:10 PM PST 24
Peak memory 215956 kb
Host smart-3aef06c3-8de5-4264-9a93-f654f41c011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317276257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1317276257
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1699167760
Short name T1712
Test name
Test status
Simulation time 919657140 ps
CPU time 4.19 seconds
Started Mar 07 02:43:59 PM PST 24
Finished Mar 07 02:44:03 PM PST 24
Peak memory 207488 kb
Host smart-1f9d2179-4cfb-4597-8418-900e33ff7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699167760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1699167760
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2746587806
Short name T335
Test name
Test status
Simulation time 158738267 ps
CPU time 0.96 seconds
Started Mar 07 12:42:08 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 206548 kb
Host smart-3ac2c271-c4bd-4cd2-9cbd-1529143dbcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746587806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2746587806
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4225753581
Short name T1583
Test name
Test status
Simulation time 248491793 ps
CPU time 1.73 seconds
Started Mar 07 02:44:07 PM PST 24
Finished Mar 07 02:44:10 PM PST 24
Peak memory 217024 kb
Host smart-96d7a38b-ce50-4ec5-beca-bf24e18047c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225753581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4225753581
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1722110567
Short name T1472
Test name
Test status
Simulation time 104639424 ps
CPU time 1.04 seconds
Started Mar 07 02:43:59 PM PST 24
Finished Mar 07 02:44:00 PM PST 24
Peak memory 205928 kb
Host smart-fe4a5afa-8786-48c4-9efa-90656952e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722110567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1722110567
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.451156656
Short name T357
Test name
Test status
Simulation time 709464348 ps
CPU time 0.97 seconds
Started Mar 07 12:42:10 PM PST 24
Finished Mar 07 12:42:11 PM PST 24
Peak memory 206436 kb
Host smart-757ce292-6e4a-4021-8425-e136535b67a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451156656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.451156656
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1679362221
Short name T169
Test name
Test status
Simulation time 4136300798 ps
CPU time 14.95 seconds
Started Mar 07 02:43:59 PM PST 24
Finished Mar 07 02:44:14 PM PST 24
Peak memory 216820 kb
Host smart-7a3ce1ff-9bdc-4d07-8a4a-885c10f8c558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679362221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1679362221
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_upload.4161274671
Short name T1045
Test name
Test status
Simulation time 42222960 ps
CPU time 2.61 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:42:12 PM PST 24
Peak memory 224472 kb
Host smart-fede1e92-cece-4c69-9e5e-2df2308c2286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161274671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4161274671
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1553614048
Short name T727
Test name
Test status
Simulation time 36254543 ps
CPU time 0.72 seconds
Started Mar 07 02:44:10 PM PST 24
Finished Mar 07 02:44:11 PM PST 24
Peak memory 204372 kb
Host smart-496f6507-d059-4489-ac08-2185de53f8ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553614048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1553614048
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.423138386
Short name T690
Test name
Test status
Simulation time 17170183 ps
CPU time 0.68 seconds
Started Mar 07 12:42:10 PM PST 24
Finished Mar 07 12:42:11 PM PST 24
Peak memory 205036 kb
Host smart-4940907f-1f63-47ab-b36c-42b49f444c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423138386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.423138386
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.116710379
Short name T420
Test name
Test status
Simulation time 173716262 ps
CPU time 4 seconds
Started Mar 07 02:43:57 PM PST 24
Finished Mar 07 02:44:01 PM PST 24
Peak memory 233016 kb
Host smart-62499ed2-2222-4c27-a7f6-3a447a72a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116710379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.116710379
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4043154365
Short name T1646
Test name
Test status
Simulation time 662342720 ps
CPU time 4.86 seconds
Started Mar 07 12:42:06 PM PST 24
Finished Mar 07 12:42:12 PM PST 24
Peak memory 234244 kb
Host smart-b0c763c7-4e57-4950-8bb3-d6b8bacac3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043154365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4043154365
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3710815759
Short name T1354
Test name
Test status
Simulation time 29552463 ps
CPU time 0.74 seconds
Started Mar 07 12:42:08 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 206596 kb
Host smart-dd015417-27e7-4fd9-a45d-7b23ab0c5572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710815759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3710815759
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.644006092
Short name T640
Test name
Test status
Simulation time 13680883 ps
CPU time 0.77 seconds
Started Mar 07 02:44:02 PM PST 24
Finished Mar 07 02:44:03 PM PST 24
Peak memory 205864 kb
Host smart-cc4c7995-e594-4809-a125-e00da5d816a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644006092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.644006092
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.151879701
Short name T1475
Test name
Test status
Simulation time 12415896050 ps
CPU time 14.95 seconds
Started Mar 07 12:42:02 PM PST 24
Finished Mar 07 12:42:17 PM PST 24
Peak memory 234672 kb
Host smart-7bc4235a-a029-48b0-aa83-f1f3a73822eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151879701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.151879701
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2800722536
Short name T875
Test name
Test status
Simulation time 1153674785 ps
CPU time 16.8 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:16 PM PST 24
Peak memory 238568 kb
Host smart-4dcdf8c8-aa0b-4a8e-9d97-fe3925e7fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800722536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2800722536
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2780675864
Short name T858
Test name
Test status
Simulation time 3896843866 ps
CPU time 61.34 seconds
Started Mar 07 02:44:03 PM PST 24
Finished Mar 07 02:45:05 PM PST 24
Peak memory 249744 kb
Host smart-1c70c0e8-a985-44b1-8ce2-634ad088217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780675864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2780675864
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.720849569
Short name T1468
Test name
Test status
Simulation time 23712664737 ps
CPU time 177.45 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:45:06 PM PST 24
Peak memory 257196 kb
Host smart-4f0a843c-d856-4594-8731-3e90b9516623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720849569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.720849569
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1273991910
Short name T503
Test name
Test status
Simulation time 64153200344 ps
CPU time 60.89 seconds
Started Mar 07 02:44:09 PM PST 24
Finished Mar 07 02:45:10 PM PST 24
Peak memory 260680 kb
Host smart-3c70b63e-1f36-4d45-819a-95a925a7db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273991910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1273991910
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3301823184
Short name T1739
Test name
Test status
Simulation time 2407027776 ps
CPU time 24.79 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:33 PM PST 24
Peak memory 232812 kb
Host smart-ae697651-2548-47e0-b714-9ad011bd6be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301823184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3301823184
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2412131313
Short name T1704
Test name
Test status
Simulation time 4949691339 ps
CPU time 24.4 seconds
Started Mar 07 12:42:10 PM PST 24
Finished Mar 07 12:42:34 PM PST 24
Peak memory 231432 kb
Host smart-07077b66-d45b-4f45-a9cf-2f7b8c7bc3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412131313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2412131313
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.781264371
Short name T776
Test name
Test status
Simulation time 541172255 ps
CPU time 14.8 seconds
Started Mar 07 02:44:01 PM PST 24
Finished Mar 07 02:44:16 PM PST 24
Peak memory 243072 kb
Host smart-17910ced-c829-4944-b292-bcd63b9b34dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781264371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.781264371
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1669289421
Short name T257
Test name
Test status
Simulation time 1606285428 ps
CPU time 2.89 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:42:12 PM PST 24
Peak memory 224476 kb
Host smart-5b121da8-3044-4320-b63c-f6e3da7deff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669289421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1669289421
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3057316175
Short name T1433
Test name
Test status
Simulation time 339251486 ps
CPU time 4.79 seconds
Started Mar 07 02:43:58 PM PST 24
Finished Mar 07 02:44:02 PM PST 24
Peak memory 232916 kb
Host smart-d042228d-756f-4085-8ad2-41b46e4b2172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057316175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3057316175
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1909226572
Short name T1197
Test name
Test status
Simulation time 2948256922 ps
CPU time 16.8 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:42:26 PM PST 24
Peak memory 240884 kb
Host smart-2f6b5a8a-90f3-44d8-894d-8174d66e66d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909226572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1909226572
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3305724353
Short name T712
Test name
Test status
Simulation time 1318890304 ps
CPU time 3.9 seconds
Started Mar 07 02:43:57 PM PST 24
Finished Mar 07 02:44:01 PM PST 24
Peak memory 223752 kb
Host smart-5199bd85-6dd3-4390-b892-6f37be97a04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305724353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3305724353
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2274403234
Short name T762
Test name
Test status
Simulation time 61457844 ps
CPU time 0.99 seconds
Started Mar 07 02:44:01 PM PST 24
Finished Mar 07 02:44:02 PM PST 24
Peak memory 217080 kb
Host smart-7b2c0c6b-1749-40b1-bab0-0378af965d24
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274403234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2274403234
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1437152860
Short name T920
Test name
Test status
Simulation time 20393862990 ps
CPU time 28.22 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:28 PM PST 24
Peak memory 232960 kb
Host smart-3614a1b6-4ef1-4285-860d-ecb622c51290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437152860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1437152860
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2119569700
Short name T546
Test name
Test status
Simulation time 25290543894 ps
CPU time 15.89 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:42:25 PM PST 24
Peak memory 245552 kb
Host smart-fa506a97-44ef-4a42-bea4-f429d0c52417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119569700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2119569700
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2250010216
Short name T1778
Test name
Test status
Simulation time 1845464042 ps
CPU time 13.07 seconds
Started Mar 07 02:43:57 PM PST 24
Finished Mar 07 02:44:11 PM PST 24
Peak memory 235536 kb
Host smart-bd3636df-4c31-4ae2-8bbd-8766e73c2032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250010216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2250010216
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2527393350
Short name T908
Test name
Test status
Simulation time 30092957252 ps
CPU time 39.92 seconds
Started Mar 07 12:42:06 PM PST 24
Finished Mar 07 12:42:47 PM PST 24
Peak memory 226816 kb
Host smart-9fe66e16-c686-4279-9d92-970b38afeab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527393350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2527393350
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2648887960
Short name T1278
Test name
Test status
Simulation time 18353762 ps
CPU time 0.73 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:01 PM PST 24
Peak memory 215408 kb
Host smart-3d697945-8f77-4b1b-9efe-b77f060c6b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648887960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2648887960
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2718137195
Short name T642
Test name
Test status
Simulation time 38737535 ps
CPU time 0.73 seconds
Started Mar 07 12:42:08 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 216120 kb
Host smart-a7dc4cf4-0b11-49fa-98fb-9b51dcb96fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718137195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2718137195
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3910716379
Short name T1330
Test name
Test status
Simulation time 280153472 ps
CPU time 3.68 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:42:13 PM PST 24
Peak memory 220152 kb
Host smart-97092bde-31fd-47d8-8250-971a9589e734
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3910716379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3910716379
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.599848297
Short name T865
Test name
Test status
Simulation time 399636236 ps
CPU time 3.79 seconds
Started Mar 07 02:43:58 PM PST 24
Finished Mar 07 02:44:02 PM PST 24
Peak memory 219452 kb
Host smart-1add3fcf-0096-4f0e-978c-24f9ab611872
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=599848297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.599848297
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2979399639
Short name T1749
Test name
Test status
Simulation time 30631412667 ps
CPU time 207.75 seconds
Started Mar 07 02:44:10 PM PST 24
Finished Mar 07 02:47:37 PM PST 24
Peak memory 273248 kb
Host smart-6ca94dc2-b612-4f43-9e14-681bba23892d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979399639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2979399639
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2980981890
Short name T1454
Test name
Test status
Simulation time 7768817228 ps
CPU time 40.67 seconds
Started Mar 07 02:44:00 PM PST 24
Finished Mar 07 02:44:41 PM PST 24
Peak memory 215800 kb
Host smart-3cebb682-056a-4788-83ba-4577180b1950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980981890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2980981890
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4239341097
Short name T1066
Test name
Test status
Simulation time 1887263639 ps
CPU time 10.61 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:18 PM PST 24
Peak memory 216264 kb
Host smart-8b3aef63-bf7d-4610-bcbe-d7191e5caee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239341097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4239341097
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1487520221
Short name T1193
Test name
Test status
Simulation time 1348021770 ps
CPU time 7.83 seconds
Started Mar 07 02:44:02 PM PST 24
Finished Mar 07 02:44:10 PM PST 24
Peak memory 215768 kb
Host smart-16f16142-713f-44a8-aaef-6f0f89af6362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487520221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1487520221
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1634236283
Short name T947
Test name
Test status
Simulation time 17150112 ps
CPU time 1.1 seconds
Started Mar 07 12:42:06 PM PST 24
Finished Mar 07 12:42:07 PM PST 24
Peak memory 207752 kb
Host smart-fa0b294c-8a27-48d4-9cb0-4e32f9eabc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634236283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1634236283
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2318756891
Short name T1023
Test name
Test status
Simulation time 90086325 ps
CPU time 0.89 seconds
Started Mar 07 02:43:58 PM PST 24
Finished Mar 07 02:43:59 PM PST 24
Peak memory 205804 kb
Host smart-1cc99f99-7ede-4eb8-9fa5-9dde3bd65cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318756891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2318756891
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1096265508
Short name T960
Test name
Test status
Simulation time 39920776 ps
CPU time 0.75 seconds
Started Mar 07 02:44:01 PM PST 24
Finished Mar 07 02:44:02 PM PST 24
Peak memory 204872 kb
Host smart-8853140a-c0d4-4daf-af98-682fece5989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096265508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1096265508
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.985905597
Short name T446
Test name
Test status
Simulation time 42372486 ps
CPU time 0.84 seconds
Started Mar 07 12:42:08 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 205468 kb
Host smart-95e61caa-2e99-4dbe-8845-433e3d6f48db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985905597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.985905597
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1106333567
Short name T560
Test name
Test status
Simulation time 2548931272 ps
CPU time 16.19 seconds
Started Mar 07 12:42:06 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 230788 kb
Host smart-93acd97d-578e-488a-ad1e-fca8ce26c617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106333567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1106333567
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_upload.353853141
Short name T925
Test name
Test status
Simulation time 7947939801 ps
CPU time 7.58 seconds
Started Mar 07 02:43:59 PM PST 24
Finished Mar 07 02:44:07 PM PST 24
Peak memory 232120 kb
Host smart-8d83080e-28e5-4019-a5ee-c6a2adcbb123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353853141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.353853141
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1536555509
Short name T1707
Test name
Test status
Simulation time 12596353 ps
CPU time 0.7 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 204580 kb
Host smart-ec8cbc27-9d57-4bf5-9fa7-c8a93d06de41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536555509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1536555509
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2651949836
Short name T1431
Test name
Test status
Simulation time 5547371730 ps
CPU time 4.33 seconds
Started Mar 07 12:42:28 PM PST 24
Finished Mar 07 12:42:33 PM PST 24
Peak memory 234308 kb
Host smart-3224e639-4a03-4ac1-b542-52b8d26452c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651949836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2651949836
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3195969864
Short name T923
Test name
Test status
Simulation time 69334341 ps
CPU time 2.58 seconds
Started Mar 07 02:44:13 PM PST 24
Finished Mar 07 02:44:16 PM PST 24
Peak memory 232016 kb
Host smart-bc7087a4-249c-422e-8b1e-030a9f364ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195969864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3195969864
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1650702235
Short name T1267
Test name
Test status
Simulation time 52618870 ps
CPU time 0.78 seconds
Started Mar 07 12:42:08 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 205348 kb
Host smart-238dd25e-3d13-4c1d-bc18-330523bdd992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650702235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1650702235
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3895495213
Short name T1396
Test name
Test status
Simulation time 57857240 ps
CPU time 0.8 seconds
Started Mar 07 02:44:12 PM PST 24
Finished Mar 07 02:44:13 PM PST 24
Peak memory 204476 kb
Host smart-fd06c8cd-9058-4f14-abb5-bfc05938171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895495213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3895495213
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3492745326
Short name T576
Test name
Test status
Simulation time 3596335040 ps
CPU time 17.42 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:42:43 PM PST 24
Peak memory 240748 kb
Host smart-de9c564d-b693-4dc2-9208-50af6cb44968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492745326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3492745326
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.45791932
Short name T1815
Test name
Test status
Simulation time 23927716377 ps
CPU time 49.49 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:43:15 PM PST 24
Peak memory 222768 kb
Host smart-45e7a761-8633-42a8-8928-2a10472be776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45791932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.45791932
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1456031234
Short name T1418
Test name
Test status
Simulation time 357111674586 ps
CPU time 307.73 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:47:32 PM PST 24
Peak memory 254812 kb
Host smart-a755ccc3-0066-467a-8d78-daad8a9bae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456031234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1456031234
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3749521235
Short name T140
Test name
Test status
Simulation time 41232510355 ps
CPU time 205.87 seconds
Started Mar 07 02:44:12 PM PST 24
Finished Mar 07 02:47:38 PM PST 24
Peak memory 238696 kb
Host smart-3af97251-63ed-43d5-b65f-7636e4dc9656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749521235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3749521235
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3446172814
Short name T1269
Test name
Test status
Simulation time 431064945 ps
CPU time 10.64 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:34 PM PST 24
Peak memory 246068 kb
Host smart-3a99ebab-f892-4fb2-a28b-b24f6e3b704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446172814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3446172814
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1093154611
Short name T1079
Test name
Test status
Simulation time 101504096 ps
CPU time 2.89 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:26 PM PST 24
Peak memory 218732 kb
Host smart-daaf113c-3939-4fab-8fa1-e0df4b3fb700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093154611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1093154611
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2202548355
Short name T1705
Test name
Test status
Simulation time 11013362597 ps
CPU time 8.72 seconds
Started Mar 07 02:44:08 PM PST 24
Finished Mar 07 02:44:17 PM PST 24
Peak memory 224024 kb
Host smart-5f016490-5f0c-4e9c-862d-e01ef8a34723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202548355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2202548355
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3754769284
Short name T1169
Test name
Test status
Simulation time 353665255 ps
CPU time 5.13 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:42:30 PM PST 24
Peak memory 235352 kb
Host smart-6d0cdad6-d8df-453f-b1b9-85675743b84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754769284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3754769284
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.919796681
Short name T234
Test name
Test status
Simulation time 116491101113 ps
CPU time 48.65 seconds
Started Mar 07 02:44:08 PM PST 24
Finished Mar 07 02:44:57 PM PST 24
Peak memory 248616 kb
Host smart-ebf390d9-2146-4c66-aa3d-70e4bd577d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919796681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.919796681
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2138980213
Short name T1514
Test name
Test status
Simulation time 75397039 ps
CPU time 1.01 seconds
Started Mar 07 02:44:08 PM PST 24
Finished Mar 07 02:44:09 PM PST 24
Peak memory 216008 kb
Host smart-adb3e193-1d65-45f8-acfa-b29e8e92ccc1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138980213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2138980213
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2144369925
Short name T1236
Test name
Test status
Simulation time 284258819 ps
CPU time 2.73 seconds
Started Mar 07 12:42:21 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 218508 kb
Host smart-6d28bded-8f06-4ec3-a948-45e9395ceca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144369925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2144369925
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.498471579
Short name T823
Test name
Test status
Simulation time 1687328399 ps
CPU time 5.88 seconds
Started Mar 07 02:44:12 PM PST 24
Finished Mar 07 02:44:18 PM PST 24
Peak memory 223692 kb
Host smart-ad2152f4-ca0b-4fda-9e2b-ba01a4e747e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498471579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.498471579
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1089737755
Short name T1296
Test name
Test status
Simulation time 35557565639 ps
CPU time 29.41 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:44:40 PM PST 24
Peak memory 232048 kb
Host smart-14b6267f-6b4f-4905-8f5c-de0020cb4878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089737755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1089737755
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1289233488
Short name T359
Test name
Test status
Simulation time 2474032829 ps
CPU time 6.25 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:42:31 PM PST 24
Peak memory 233136 kb
Host smart-6218677a-e4cd-4d81-8595-314e6c71f21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289233488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1289233488
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2193859345
Short name T1850
Test name
Test status
Simulation time 29597005 ps
CPU time 0.74 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 216220 kb
Host smart-7996e34a-093e-49c8-b6c5-0ebaee6bb48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193859345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2193859345
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2512153470
Short name T855
Test name
Test status
Simulation time 31619670 ps
CPU time 0.71 seconds
Started Mar 07 02:44:08 PM PST 24
Finished Mar 07 02:44:09 PM PST 24
Peak memory 215640 kb
Host smart-6fe92170-ba5f-46d1-835c-dee4c6ac60e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512153470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2512153470
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3371079545
Short name T870
Test name
Test status
Simulation time 1831113879 ps
CPU time 5.78 seconds
Started Mar 07 02:44:12 PM PST 24
Finished Mar 07 02:44:18 PM PST 24
Peak memory 222104 kb
Host smart-a7b1036f-1c1e-4a50-8a0b-015674b76ac6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3371079545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3371079545
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3771286957
Short name T337
Test name
Test status
Simulation time 269816518 ps
CPU time 3.27 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:42:27 PM PST 24
Peak memory 219928 kb
Host smart-569103b7-66e2-4f56-a0e5-a6a60f1ddc53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3771286957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3771286957
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3498154086
Short name T48
Test name
Test status
Simulation time 614256001655 ps
CPU time 357.55 seconds
Started Mar 07 12:42:21 PM PST 24
Finished Mar 07 12:48:19 PM PST 24
Peak memory 273196 kb
Host smart-0846ff49-4cb9-4816-a975-3399500e75c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498154086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3498154086
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4152486283
Short name T975
Test name
Test status
Simulation time 341785171032 ps
CPU time 168.72 seconds
Started Mar 07 02:44:13 PM PST 24
Finished Mar 07 02:47:01 PM PST 24
Peak memory 249388 kb
Host smart-d48d300b-39a1-4a44-aa4b-bd9d94cb9ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152486283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4152486283
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1629052501
Short name T1104
Test name
Test status
Simulation time 10927628740 ps
CPU time 41.55 seconds
Started Mar 07 12:42:09 PM PST 24
Finished Mar 07 12:42:50 PM PST 24
Peak memory 216416 kb
Host smart-4dcc073f-e1c9-41dc-99f4-c57e9d7639e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629052501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1629052501
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.19353780
Short name T1894
Test name
Test status
Simulation time 106074504608 ps
CPU time 73.84 seconds
Started Mar 07 02:44:09 PM PST 24
Finished Mar 07 02:45:23 PM PST 24
Peak memory 215800 kb
Host smart-04642651-2555-45b5-a718-417d04b98eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19353780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.19353780
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2743544660
Short name T99
Test name
Test status
Simulation time 263151361 ps
CPU time 1.84 seconds
Started Mar 07 12:42:07 PM PST 24
Finished Mar 07 12:42:10 PM PST 24
Peak memory 207728 kb
Host smart-c7511472-09f7-4204-bfbd-9bc2e5d1b6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743544660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2743544660
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3693197958
Short name T1764
Test name
Test status
Simulation time 4206571393 ps
CPU time 5.54 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:44:16 PM PST 24
Peak memory 215796 kb
Host smart-790a4858-a3a2-47e7-946b-f1bb5db39749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693197958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3693197958
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1391190603
Short name T1113
Test name
Test status
Simulation time 1323342667 ps
CPU time 3.95 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:42:29 PM PST 24
Peak memory 216140 kb
Host smart-52c8f03f-3ff5-4cf7-b531-9adad44308f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391190603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1391190603
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4169311735
Short name T1518
Test name
Test status
Simulation time 81049348 ps
CPU time 2.3 seconds
Started Mar 07 02:44:10 PM PST 24
Finished Mar 07 02:44:12 PM PST 24
Peak memory 207508 kb
Host smart-efa90594-0862-4b79-8474-678c53e5b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169311735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4169311735
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2449001396
Short name T443
Test name
Test status
Simulation time 44719431 ps
CPU time 0.75 seconds
Started Mar 07 12:42:27 PM PST 24
Finished Mar 07 12:42:28 PM PST 24
Peak memory 205468 kb
Host smart-61539c72-e498-40d7-92c6-dd2cd73805ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449001396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2449001396
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2492300921
Short name T1252
Test name
Test status
Simulation time 14652259 ps
CPU time 0.72 seconds
Started Mar 07 02:44:10 PM PST 24
Finished Mar 07 02:44:10 PM PST 24
Peak memory 204960 kb
Host smart-4e02e49d-9b31-4774-b03b-89a1e0f73398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492300921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2492300921
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1786093105
Short name T1657
Test name
Test status
Simulation time 898918154 ps
CPU time 7.12 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:44:18 PM PST 24
Peak memory 227912 kb
Host smart-76269b69-a1a7-46bf-af50-89f9e6978568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786093105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1786093105
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_upload.3186753908
Short name T1647
Test name
Test status
Simulation time 2013180767 ps
CPU time 16.25 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:42:40 PM PST 24
Peak memory 232584 kb
Host smart-5182e29c-4d93-4961-a0e1-53a72b056c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186753908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3186753908
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.119769934
Short name T1677
Test name
Test status
Simulation time 15608434 ps
CPU time 0.75 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:25 PM PST 24
Peak memory 205140 kb
Host smart-80f0e8cd-24a1-4027-bf56-2d38b8687f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119769934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.119769934
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.621749963
Short name T60
Test name
Test status
Simulation time 51670001 ps
CPU time 0.75 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:20 PM PST 24
Peak memory 204408 kb
Host smart-b9ae0098-d9a1-47b5-9136-f03def5177e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621749963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.621749963
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2279784982
Short name T1630
Test name
Test status
Simulation time 700320864 ps
CPU time 3.93 seconds
Started Mar 07 02:44:16 PM PST 24
Finished Mar 07 02:44:20 PM PST 24
Peak memory 223812 kb
Host smart-1c81fede-f245-4aa8-8326-135bb2bf2792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279784982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2279784982
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.283811708
Short name T1768
Test name
Test status
Simulation time 31313521032 ps
CPU time 10 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:42:35 PM PST 24
Peak memory 219424 kb
Host smart-839c2dcd-e6ff-44d5-8621-2799db8be33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283811708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.283811708
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3116915878
Short name T405
Test name
Test status
Simulation time 18162073 ps
CPU time 0.76 seconds
Started Mar 07 12:42:26 PM PST 24
Finished Mar 07 12:42:27 PM PST 24
Peak memory 205348 kb
Host smart-1ab52316-b3f7-4159-bf30-395be020040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116915878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3116915878
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4259026660
Short name T676
Test name
Test status
Simulation time 16509870 ps
CPU time 0.74 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:44:12 PM PST 24
Peak memory 204828 kb
Host smart-5526d8d3-7500-4d0d-917a-134b3dc9a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259026660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4259026660
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1155875807
Short name T584
Test name
Test status
Simulation time 14247799547 ps
CPU time 15.94 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:35 PM PST 24
Peak memory 234224 kb
Host smart-09ee3638-f90d-40ba-8ce1-26fe5ffd3dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155875807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1155875807
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2546005092
Short name T1641
Test name
Test status
Simulation time 1435304256 ps
CPU time 13.9 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:42:38 PM PST 24
Peak memory 224484 kb
Host smart-423c3a2f-9f75-40d1-8bf9-33250703b6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546005092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2546005092
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1761925026
Short name T828
Test name
Test status
Simulation time 17489216990 ps
CPU time 119.25 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:44:25 PM PST 24
Peak memory 236952 kb
Host smart-2953021e-36c7-486e-9ee2-c1e1094ec9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761925026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1761925026
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2052679994
Short name T1686
Test name
Test status
Simulation time 32439284672 ps
CPU time 240.71 seconds
Started Mar 07 02:44:22 PM PST 24
Finished Mar 07 02:48:23 PM PST 24
Peak memory 253224 kb
Host smart-29508e51-8785-4def-95cf-673948218157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052679994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2052679994
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2562440192
Short name T1618
Test name
Test status
Simulation time 33981348127 ps
CPU time 212.12 seconds
Started Mar 07 02:44:18 PM PST 24
Finished Mar 07 02:47:50 PM PST 24
Peak memory 249984 kb
Host smart-b3441fc9-8346-4f7c-9fae-6e141dd81317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562440192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2562440192
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3899005469
Short name T530
Test name
Test status
Simulation time 13650129723 ps
CPU time 33.86 seconds
Started Mar 07 12:42:22 PM PST 24
Finished Mar 07 12:42:56 PM PST 24
Peak memory 249620 kb
Host smart-56ef4876-e873-4c18-93d5-a9c2a65e910a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899005469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3899005469
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1810361992
Short name T444
Test name
Test status
Simulation time 1227608723 ps
CPU time 8.77 seconds
Started Mar 07 02:44:17 PM PST 24
Finished Mar 07 02:44:26 PM PST 24
Peak memory 232088 kb
Host smart-80921f92-8ed1-4ad0-b509-1840d23d1144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810361992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1810361992
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.227868870
Short name T1000
Test name
Test status
Simulation time 2064566095 ps
CPU time 16.92 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 220816 kb
Host smart-65bd377a-1c76-460c-926b-705a0dd5c505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227868870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.227868870
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1187268066
Short name T1147
Test name
Test status
Simulation time 10030403064 ps
CPU time 8.84 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:32 PM PST 24
Peak memory 234084 kb
Host smart-9cab05e1-dff0-45f5-b736-528256fee62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187268066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1187268066
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intercept.241989427
Short name T1643
Test name
Test status
Simulation time 2016930793 ps
CPU time 4.72 seconds
Started Mar 07 02:44:12 PM PST 24
Finished Mar 07 02:44:17 PM PST 24
Peak memory 232652 kb
Host smart-d85c4ca2-162b-4250-ab26-f6cda17ce061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241989427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.241989427
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2558309909
Short name T1842
Test name
Test status
Simulation time 694090794 ps
CPU time 6.53 seconds
Started Mar 07 12:42:21 PM PST 24
Finished Mar 07 12:42:28 PM PST 24
Peak memory 229864 kb
Host smart-0b6179eb-dbc3-44dd-a8db-200a308d4f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558309909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2558309909
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2620813594
Short name T1609
Test name
Test status
Simulation time 383728860 ps
CPU time 3.03 seconds
Started Mar 07 02:44:13 PM PST 24
Finished Mar 07 02:44:16 PM PST 24
Peak memory 232636 kb
Host smart-1aea7c04-b644-494e-a56f-92b2ca050d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620813594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2620813594
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3274638820
Short name T1721
Test name
Test status
Simulation time 136233315 ps
CPU time 1.03 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:44:12 PM PST 24
Peak memory 217276 kb
Host smart-06d6c5da-b0c1-429d-9e3b-4a0ff029eef9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274638820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3274638820
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3242917568
Short name T1576
Test name
Test status
Simulation time 7492627754 ps
CPU time 10.76 seconds
Started Mar 07 02:44:12 PM PST 24
Finished Mar 07 02:44:23 PM PST 24
Peak memory 223828 kb
Host smart-92790a3e-cb72-4727-b082-a345dd85083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242917568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3242917568
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4223488891
Short name T1607
Test name
Test status
Simulation time 72492047758 ps
CPU time 17.74 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:42:42 PM PST 24
Peak memory 232676 kb
Host smart-e3fb001e-1e78-4848-8eb6-a895f7f9a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223488891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4223488891
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.4011316795
Short name T633
Test name
Test status
Simulation time 162797919 ps
CPU time 2.99 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:44:14 PM PST 24
Peak memory 216160 kb
Host smart-c99d4b07-8ab7-4569-b893-33a3ea33efdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011316795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.4011316795
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.578443860
Short name T887
Test name
Test status
Simulation time 6323702478 ps
CPU time 12.25 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:42:37 PM PST 24
Peak memory 235012 kb
Host smart-c3414f70-242e-4eef-bc92-850b13fb83bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578443860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.578443860
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.108958147
Short name T1012
Test name
Test status
Simulation time 25566578 ps
CPU time 0.75 seconds
Started Mar 07 02:44:10 PM PST 24
Finished Mar 07 02:44:11 PM PST 24
Peak memory 215608 kb
Host smart-49ee7cb0-0fee-41db-81b4-883d5cec918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108958147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.108958147
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2261919332
Short name T1848
Test name
Test status
Simulation time 18392843 ps
CPU time 0.8 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 216196 kb
Host smart-661c47d4-7d56-4fa2-945b-5f31edb82826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261919332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2261919332
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3763244099
Short name T1443
Test name
Test status
Simulation time 1094074950 ps
CPU time 3.75 seconds
Started Mar 07 12:42:28 PM PST 24
Finished Mar 07 12:42:32 PM PST 24
Peak memory 218944 kb
Host smart-fc70025d-cb71-4b6e-9a9d-0b51b8f65e90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3763244099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3763244099
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.685760980
Short name T1386
Test name
Test status
Simulation time 222385825 ps
CPU time 4.19 seconds
Started Mar 07 02:44:22 PM PST 24
Finished Mar 07 02:44:26 PM PST 24
Peak memory 221964 kb
Host smart-922b7e4f-bda8-458b-a8bb-76a3a0d204bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=685760980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.685760980
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2965271523
Short name T284
Test name
Test status
Simulation time 26099105644 ps
CPU time 236.29 seconds
Started Mar 07 12:42:22 PM PST 24
Finished Mar 07 12:46:18 PM PST 24
Peak memory 265796 kb
Host smart-db155d0b-a6b3-4748-9f5a-492749a15fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965271523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2965271523
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3809443781
Short name T662
Test name
Test status
Simulation time 10932210024 ps
CPU time 129.25 seconds
Started Mar 07 02:44:21 PM PST 24
Finished Mar 07 02:46:31 PM PST 24
Peak memory 265080 kb
Host smart-ba583e37-2bd8-4046-9efa-3c6f043c157f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809443781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3809443781
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3719727110
Short name T15
Test name
Test status
Simulation time 2169245082 ps
CPU time 27.17 seconds
Started Mar 07 02:44:12 PM PST 24
Finished Mar 07 02:44:39 PM PST 24
Peak memory 215820 kb
Host smart-ea45c624-7ad1-4335-bda9-dde8b2477a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719727110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3719727110
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4041255435
Short name T1336
Test name
Test status
Simulation time 21595922650 ps
CPU time 44.21 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:43:08 PM PST 24
Peak memory 216260 kb
Host smart-cc70b1db-d324-4b6d-9fa7-ccb6b6b5208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041255435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4041255435
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1295652406
Short name T1074
Test name
Test status
Simulation time 507843521 ps
CPU time 3.84 seconds
Started Mar 07 02:44:12 PM PST 24
Finished Mar 07 02:44:16 PM PST 24
Peak memory 207668 kb
Host smart-43d41be3-28ed-4ce5-992b-02cffb9fa91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295652406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1295652406
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3282239484
Short name T650
Test name
Test status
Simulation time 8942286952 ps
CPU time 25.72 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:42:50 PM PST 24
Peak memory 216232 kb
Host smart-f6e049e5-20d2-4915-bd9f-5e353dd184a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282239484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3282239484
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2546022281
Short name T1028
Test name
Test status
Simulation time 241344399 ps
CPU time 1.44 seconds
Started Mar 07 02:44:11 PM PST 24
Finished Mar 07 02:44:12 PM PST 24
Peak memory 215832 kb
Host smart-0621f23f-8bbd-4daa-9d9d-a537ba6e7f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546022281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2546022281
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.376117818
Short name T1621
Test name
Test status
Simulation time 312597744 ps
CPU time 2.37 seconds
Started Mar 07 12:42:26 PM PST 24
Finished Mar 07 12:42:29 PM PST 24
Peak memory 216212 kb
Host smart-4e3b7feb-defb-4bb6-af96-26539306510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376117818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.376117818
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.187890112
Short name T1538
Test name
Test status
Simulation time 47870694 ps
CPU time 0.96 seconds
Started Mar 07 12:42:24 PM PST 24
Finished Mar 07 12:42:26 PM PST 24
Peak memory 205436 kb
Host smart-17b479ac-e380-4f4d-bde7-76fba6fbb0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187890112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.187890112
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2216396278
Short name T986
Test name
Test status
Simulation time 124359408 ps
CPU time 1.08 seconds
Started Mar 07 02:44:14 PM PST 24
Finished Mar 07 02:44:15 PM PST 24
Peak memory 205832 kb
Host smart-7cff2c8e-c7d0-439f-9f21-f0bd5ff54a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216396278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2216396278
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3232387832
Short name T1167
Test name
Test status
Simulation time 13190243397 ps
CPU time 9.27 seconds
Started Mar 07 02:44:17 PM PST 24
Finished Mar 07 02:44:27 PM PST 24
Peak memory 218944 kb
Host smart-159b76bc-8df5-4dea-9637-8ab11d96c86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232387832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3232387832
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_upload.3238901815
Short name T605
Test name
Test status
Simulation time 3046395408 ps
CPU time 3.38 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:27 PM PST 24
Peak memory 216460 kb
Host smart-f0ee739f-944c-42cf-8dfe-1a023e50359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238901815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3238901815
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3321832430
Short name T1571
Test name
Test status
Simulation time 50109540 ps
CPU time 0.74 seconds
Started Mar 07 12:42:28 PM PST 24
Finished Mar 07 12:42:29 PM PST 24
Peak memory 205160 kb
Host smart-ab2dfd8e-509d-4a35-8865-bd8d87da3e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321832430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3321832430
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.51250423
Short name T889
Test name
Test status
Simulation time 40652335 ps
CPU time 0.76 seconds
Started Mar 07 02:44:27 PM PST 24
Finished Mar 07 02:44:29 PM PST 24
Peak memory 204272 kb
Host smart-b1784c00-24b7-46d1-932d-ba69d1ef220d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51250423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.51250423
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3682863488
Short name T1691
Test name
Test status
Simulation time 7317405673 ps
CPU time 14.14 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:33 PM PST 24
Peak memory 233872 kb
Host smart-194375f6-7bba-47c5-bbaa-0c7c37940a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682863488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3682863488
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3953087938
Short name T1695
Test name
Test status
Simulation time 915752626 ps
CPU time 3.58 seconds
Started Mar 07 12:42:26 PM PST 24
Finished Mar 07 12:42:30 PM PST 24
Peak memory 218572 kb
Host smart-3a07bd9b-a427-40cb-85f3-7124dc3d599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953087938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3953087938
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2614662090
Short name T933
Test name
Test status
Simulation time 22697870 ps
CPU time 0.76 seconds
Started Mar 07 12:42:26 PM PST 24
Finished Mar 07 12:42:27 PM PST 24
Peak memory 205208 kb
Host smart-6ee9fae6-3b2e-4225-a816-20e384f50b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614662090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2614662090
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3595100890
Short name T744
Test name
Test status
Simulation time 48593387 ps
CPU time 0.78 seconds
Started Mar 07 02:44:23 PM PST 24
Finished Mar 07 02:44:24 PM PST 24
Peak memory 205544 kb
Host smart-1682407e-ae39-4b1d-91c9-bb549e360ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595100890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3595100890
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.412447991
Short name T1587
Test name
Test status
Simulation time 190573948466 ps
CPU time 236.63 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:48:16 PM PST 24
Peak memory 248560 kb
Host smart-5e666059-337c-4b7a-bc2a-6fb3c8ef69d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412447991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.412447991
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.784631449
Short name T1149
Test name
Test status
Simulation time 136081587079 ps
CPU time 37.59 seconds
Started Mar 07 12:42:26 PM PST 24
Finished Mar 07 12:43:04 PM PST 24
Peak memory 240916 kb
Host smart-45589978-b802-48f1-b2b4-0f5f9fe75b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784631449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.784631449
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2108336713
Short name T286
Test name
Test status
Simulation time 469619351050 ps
CPU time 733.25 seconds
Started Mar 07 02:44:21 PM PST 24
Finished Mar 07 02:56:35 PM PST 24
Peak memory 260560 kb
Host smart-727df59c-31e2-4ba2-9552-81a8be12c0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108336713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2108336713
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3403240160
Short name T1917
Test name
Test status
Simulation time 46785285902 ps
CPU time 326.19 seconds
Started Mar 07 12:42:29 PM PST 24
Finished Mar 07 12:47:55 PM PST 24
Peak memory 273592 kb
Host smart-03128102-8a66-4313-aa52-cedad842b7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403240160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3403240160
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1015238400
Short name T313
Test name
Test status
Simulation time 4602964241 ps
CPU time 28.6 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:48 PM PST 24
Peak memory 240284 kb
Host smart-8f87a8c7-b198-45f0-bcac-adb019e85c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015238400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1015238400
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.160360194
Short name T1612
Test name
Test status
Simulation time 17720773718 ps
CPU time 20.12 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:42:45 PM PST 24
Peak memory 236756 kb
Host smart-46914619-f106-4500-b1cc-c691f4175836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160360194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.160360194
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2485472037
Short name T1569
Test name
Test status
Simulation time 863711522 ps
CPU time 6.08 seconds
Started Mar 07 02:44:25 PM PST 24
Finished Mar 07 02:44:32 PM PST 24
Peak memory 236288 kb
Host smart-1a24c04c-972b-49d3-8222-06566308fcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485472037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2485472037
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3479371864
Short name T220
Test name
Test status
Simulation time 2312587443 ps
CPU time 4.79 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:42:30 PM PST 24
Peak memory 224540 kb
Host smart-8a60fb79-e920-4438-91ed-5a4df548c525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479371864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3479371864
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2819692171
Short name T677
Test name
Test status
Simulation time 9076188260 ps
CPU time 28.34 seconds
Started Mar 07 02:44:20 PM PST 24
Finished Mar 07 02:44:49 PM PST 24
Peak memory 232116 kb
Host smart-16bacede-4cab-4827-b0a8-c81db0d69e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819692171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2819692171
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.484520785
Short name T402
Test name
Test status
Simulation time 3151362669 ps
CPU time 7.83 seconds
Started Mar 07 12:42:28 PM PST 24
Finished Mar 07 12:42:36 PM PST 24
Peak memory 240916 kb
Host smart-1b507ebf-2a1f-4fb3-9920-1dc19af24f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484520785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.484520785
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2176513867
Short name T1803
Test name
Test status
Simulation time 27389670 ps
CPU time 1.06 seconds
Started Mar 07 02:44:21 PM PST 24
Finished Mar 07 02:44:23 PM PST 24
Peak memory 216004 kb
Host smart-b9566b0d-937a-4c7c-a69d-767b92a7c0d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176513867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2176513867
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1879850921
Short name T167
Test name
Test status
Simulation time 3748131481 ps
CPU time 11.69 seconds
Started Mar 07 02:44:17 PM PST 24
Finished Mar 07 02:44:28 PM PST 24
Peak memory 223884 kb
Host smart-090136b9-6456-430c-8a53-564896b84ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879850921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1879850921
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3113860175
Short name T1374
Test name
Test status
Simulation time 7822647124 ps
CPU time 8.73 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:31 PM PST 24
Peak memory 231980 kb
Host smart-ebe43017-7781-4594-8bcc-3c3d53e93872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113860175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3113860175
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1017372055
Short name T1106
Test name
Test status
Simulation time 165145048 ps
CPU time 2.72 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:26 PM PST 24
Peak memory 233616 kb
Host smart-a2925e62-645e-4350-b5d1-74a132f55253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017372055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1017372055
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.732145999
Short name T82
Test name
Test status
Simulation time 41925245081 ps
CPU time 24.83 seconds
Started Mar 07 02:44:21 PM PST 24
Finished Mar 07 02:44:46 PM PST 24
Peak memory 232164 kb
Host smart-ad4cc3f0-1d6e-4eb2-ad0e-887e58a5c620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732145999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.732145999
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1956725731
Short name T665
Test name
Test status
Simulation time 18972367 ps
CPU time 0.75 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 216144 kb
Host smart-8e94102a-2bb4-4348-89db-b8635d455114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956725731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1956725731
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2280225260
Short name T1496
Test name
Test status
Simulation time 17670502 ps
CPU time 0.73 seconds
Started Mar 07 02:44:18 PM PST 24
Finished Mar 07 02:44:18 PM PST 24
Peak memory 215624 kb
Host smart-6b5112e3-f29b-4fd4-bb46-ad5da498bed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280225260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2280225260
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.177887603
Short name T1226
Test name
Test status
Simulation time 8038702313 ps
CPU time 7.56 seconds
Started Mar 07 02:44:20 PM PST 24
Finished Mar 07 02:44:28 PM PST 24
Peak memory 222208 kb
Host smart-4a00de7e-0dc0-45fb-a367-355a47f2a301
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=177887603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.177887603
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3097137259
Short name T1633
Test name
Test status
Simulation time 119658516 ps
CPU time 3.88 seconds
Started Mar 07 12:42:28 PM PST 24
Finished Mar 07 12:42:32 PM PST 24
Peak memory 222172 kb
Host smart-5146929c-db9a-45ba-8c96-84b87b39e23f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3097137259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3097137259
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1417330994
Short name T1388
Test name
Test status
Simulation time 6380865372 ps
CPU time 73.55 seconds
Started Mar 07 12:42:26 PM PST 24
Finished Mar 07 12:43:40 PM PST 24
Peak memory 250876 kb
Host smart-0d100542-882a-4ca6-b139-e034fde58b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417330994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1417330994
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1908425322
Short name T213
Test name
Test status
Simulation time 114479719145 ps
CPU time 593.93 seconds
Started Mar 07 02:44:21 PM PST 24
Finished Mar 07 02:54:15 PM PST 24
Peak memory 281236 kb
Host smart-1d329876-9849-4fb0-8fd4-223541aaea86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908425322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1908425322
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2881562289
Short name T638
Test name
Test status
Simulation time 4221427883 ps
CPU time 30.64 seconds
Started Mar 07 02:44:25 PM PST 24
Finished Mar 07 02:44:56 PM PST 24
Peak memory 218964 kb
Host smart-bcc5cb69-a984-4aa3-a3da-3801b8a3d33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881562289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2881562289
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3697277586
Short name T1062
Test name
Test status
Simulation time 88414159436 ps
CPU time 37.26 seconds
Started Mar 07 12:42:28 PM PST 24
Finished Mar 07 12:43:06 PM PST 24
Peak memory 216276 kb
Host smart-6d940809-42b9-4b4a-acc7-37e3b5089bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697277586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3697277586
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1276653767
Short name T1480
Test name
Test status
Simulation time 3485523825 ps
CPU time 7.07 seconds
Started Mar 07 02:44:24 PM PST 24
Finished Mar 07 02:44:32 PM PST 24
Peak memory 215816 kb
Host smart-4e1ec280-c149-4b53-bc41-d029c4736a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276653767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1276653767
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.568448190
Short name T1672
Test name
Test status
Simulation time 3967997561 ps
CPU time 12.29 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:35 PM PST 24
Peak memory 216200 kb
Host smart-2dabb2df-4896-42e4-bb98-9d889b7e8592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568448190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.568448190
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.213780732
Short name T1394
Test name
Test status
Simulation time 128653911 ps
CPU time 2.02 seconds
Started Mar 07 12:42:22 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 216176 kb
Host smart-a4e2a61b-4de7-4f53-ae53-056d3349d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213780732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.213780732
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.684224340
Short name T436
Test name
Test status
Simulation time 38168949 ps
CPU time 0.72 seconds
Started Mar 07 02:44:18 PM PST 24
Finished Mar 07 02:44:19 PM PST 24
Peak memory 204876 kb
Host smart-210ba103-afb8-45c2-8db1-b5d316181caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684224340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.684224340
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.202481513
Short name T1595
Test name
Test status
Simulation time 288812244 ps
CPU time 0.8 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:20 PM PST 24
Peak memory 204864 kb
Host smart-e8fc91d6-8d33-4d2c-88e4-cfffa9348c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202481513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.202481513
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3668482339
Short name T603
Test name
Test status
Simulation time 232717107 ps
CPU time 0.87 seconds
Started Mar 07 12:42:30 PM PST 24
Finished Mar 07 12:42:31 PM PST 24
Peak memory 205416 kb
Host smart-df83bad5-a639-4935-80a6-2e7b24e5a212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668482339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3668482339
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.135599311
Short name T1801
Test name
Test status
Simulation time 60679215140 ps
CPU time 30.7 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:50 PM PST 24
Peak memory 228240 kb
Host smart-93aa797e-cf31-45e1-ad0d-8dbb04895193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135599311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.135599311
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_upload.902704592
Short name T238
Test name
Test status
Simulation time 412135586 ps
CPU time 3.25 seconds
Started Mar 07 12:42:28 PM PST 24
Finished Mar 07 12:42:31 PM PST 24
Peak memory 234704 kb
Host smart-d60bbf87-a872-498f-8c6c-ef89b35c6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902704592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.902704592
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3227370035
Short name T854
Test name
Test status
Simulation time 18990699 ps
CPU time 0.71 seconds
Started Mar 07 02:44:31 PM PST 24
Finished Mar 07 02:44:31 PM PST 24
Peak memory 203868 kb
Host smart-bfda77bd-ea72-42e3-b566-8837c22f4275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227370035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3227370035
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3755663907
Short name T1427
Test name
Test status
Simulation time 48899041 ps
CPU time 0.75 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:37 PM PST 24
Peak memory 204556 kb
Host smart-5aebae5d-6f8e-4037-826c-e657c90d54f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755663907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3755663907
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2547487895
Short name T1018
Test name
Test status
Simulation time 489685734 ps
CPU time 3.38 seconds
Started Mar 07 02:44:27 PM PST 24
Finished Mar 07 02:44:31 PM PST 24
Peak memory 216920 kb
Host smart-3feced36-8e2e-4d3a-b0d4-8b9bb1d37fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547487895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2547487895
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3860409564
Short name T580
Test name
Test status
Simulation time 1335595951 ps
CPU time 3.72 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:40 PM PST 24
Peak memory 219496 kb
Host smart-1cbba4c9-91fb-40fb-900c-3f61672d4b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860409564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3860409564
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1492518611
Short name T475
Test name
Test status
Simulation time 20880729 ps
CPU time 0.85 seconds
Started Mar 07 02:44:20 PM PST 24
Finished Mar 07 02:44:21 PM PST 24
Peak memory 205788 kb
Host smart-a6ca94f7-69ee-4865-bd60-89eddd126926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492518611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1492518611
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2381626993
Short name T369
Test name
Test status
Simulation time 22368068 ps
CPU time 0.83 seconds
Started Mar 07 12:42:25 PM PST 24
Finished Mar 07 12:42:26 PM PST 24
Peak memory 206596 kb
Host smart-8b99b1a3-dc7d-458f-8762-0f5a1d755bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381626993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2381626993
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.227331237
Short name T1505
Test name
Test status
Simulation time 4673917217 ps
CPU time 12.08 seconds
Started Mar 07 02:44:28 PM PST 24
Finished Mar 07 02:44:40 PM PST 24
Peak memory 223876 kb
Host smart-b6059dfe-3e92-4897-b7bc-013eebf643e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227331237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.227331237
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2683301862
Short name T1356
Test name
Test status
Simulation time 56900779014 ps
CPU time 306.44 seconds
Started Mar 07 12:42:35 PM PST 24
Finished Mar 07 12:47:42 PM PST 24
Peak memory 265552 kb
Host smart-c343642e-88b9-436d-b0f0-cd4b3dbcbb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683301862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2683301862
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1314227849
Short name T1105
Test name
Test status
Simulation time 25612170094 ps
CPU time 154.68 seconds
Started Mar 07 12:42:39 PM PST 24
Finished Mar 07 12:45:14 PM PST 24
Peak memory 249112 kb
Host smart-7b1f8a73-3e68-4f90-974c-9e0e14a73d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314227849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1314227849
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1394859814
Short name T1533
Test name
Test status
Simulation time 155504244660 ps
CPU time 218.79 seconds
Started Mar 07 02:44:29 PM PST 24
Finished Mar 07 02:48:09 PM PST 24
Peak memory 248556 kb
Host smart-9c77a474-e1f2-4902-bd06-9a77386bc52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394859814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1394859814
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2149306500
Short name T1196
Test name
Test status
Simulation time 8026500956 ps
CPU time 64.23 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:45:39 PM PST 24
Peak memory 237888 kb
Host smart-01882cb6-d628-4028-a330-038cd7db25bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149306500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2149306500
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2136639552
Short name T2
Test name
Test status
Simulation time 413432451 ps
CPU time 10 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:46 PM PST 24
Peak memory 248640 kb
Host smart-2e5b35a7-40ea-4ff6-b589-74095cbd9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136639552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2136639552
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2576678905
Short name T314
Test name
Test status
Simulation time 9463775790 ps
CPU time 17.42 seconds
Started Mar 07 02:44:27 PM PST 24
Finished Mar 07 02:44:45 PM PST 24
Peak memory 240284 kb
Host smart-ca4294d4-5e78-4e0a-aad6-b665efb818b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576678905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2576678905
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1033403431
Short name T208
Test name
Test status
Simulation time 786178652 ps
CPU time 3.22 seconds
Started Mar 07 02:44:21 PM PST 24
Finished Mar 07 02:44:25 PM PST 24
Peak memory 223908 kb
Host smart-002b06be-0243-4ad5-bcc6-60ed957642a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033403431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1033403431
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intercept.277145829
Short name T219
Test name
Test status
Simulation time 815595846 ps
CPU time 5.15 seconds
Started Mar 07 12:42:35 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 218644 kb
Host smart-e3175825-d6a1-48de-b9db-9f184a1fcf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277145829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.277145829
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2278767559
Short name T1248
Test name
Test status
Simulation time 489717611 ps
CPU time 2.73 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:22 PM PST 24
Peak memory 223812 kb
Host smart-e3dd2ae1-fe9b-4834-b72d-a76bc69ca1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278767559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2278767559
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3110804625
Short name T1445
Test name
Test status
Simulation time 1450517489 ps
CPU time 12.7 seconds
Started Mar 07 12:42:35 PM PST 24
Finished Mar 07 12:42:48 PM PST 24
Peak memory 247316 kb
Host smart-0ed1763f-6ccc-45eb-abe6-51a21fd0359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110804625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3110804625
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3335247029
Short name T664
Test name
Test status
Simulation time 15407709 ps
CPU time 1.05 seconds
Started Mar 07 02:44:27 PM PST 24
Finished Mar 07 02:44:29 PM PST 24
Peak memory 217084 kb
Host smart-9e49feac-08ad-4da3-9a8c-bcc75f597d47
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335247029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3335247029
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1033488666
Short name T1774
Test name
Test status
Simulation time 13135589778 ps
CPU time 30.9 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:50 PM PST 24
Peak memory 232088 kb
Host smart-4aa6cae2-62bb-4bae-91af-c01fce4830ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033488666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1033488666
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1544556719
Short name T296
Test name
Test status
Simulation time 36476956055 ps
CPU time 43.14 seconds
Started Mar 07 12:42:34 PM PST 24
Finished Mar 07 12:43:17 PM PST 24
Peak memory 224508 kb
Host smart-22d83509-ebfc-4bc2-b485-4869e38441f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544556719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1544556719
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.126966108
Short name T488
Test name
Test status
Simulation time 46778911 ps
CPU time 2.01 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 218356 kb
Host smart-0dc81741-fc1e-4bf3-a4b3-a3a9802f4660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126966108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.126966108
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2109576879
Short name T415
Test name
Test status
Simulation time 1090896444 ps
CPU time 8.83 seconds
Started Mar 07 02:44:17 PM PST 24
Finished Mar 07 02:44:26 PM PST 24
Peak memory 248488 kb
Host smart-1be71be5-0235-4e8b-a4b1-68a1d30547ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109576879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2109576879
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2126788226
Short name T63
Test name
Test status
Simulation time 22291248 ps
CPU time 0.82 seconds
Started Mar 07 12:42:23 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 216120 kb
Host smart-a4a32419-ec36-452a-be28-ee452822a0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126788226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2126788226
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.466360308
Short name T483
Test name
Test status
Simulation time 38053453 ps
CPU time 0.73 seconds
Started Mar 07 02:44:22 PM PST 24
Finished Mar 07 02:44:23 PM PST 24
Peak memory 215628 kb
Host smart-341f658d-4a7a-46a6-a797-7fa326b68525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466360308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.466360308
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3191304642
Short name T1140
Test name
Test status
Simulation time 1812114579 ps
CPU time 5.22 seconds
Started Mar 07 12:42:39 PM PST 24
Finished Mar 07 12:42:45 PM PST 24
Peak memory 218492 kb
Host smart-51595515-e6f7-494b-939a-9f4ca3c94cfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3191304642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3191304642
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3499350503
Short name T678
Test name
Test status
Simulation time 2211884957 ps
CPU time 3.99 seconds
Started Mar 07 02:44:24 PM PST 24
Finished Mar 07 02:44:28 PM PST 24
Peak memory 217848 kb
Host smart-4cfe8c3a-d5e4-47c1-8543-e59055eb0f84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3499350503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3499350503
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3408844714
Short name T1244
Test name
Test status
Simulation time 57944444504 ps
CPU time 288.4 seconds
Started Mar 07 02:44:24 PM PST 24
Finished Mar 07 02:49:13 PM PST 24
Peak memory 289648 kb
Host smart-43383d19-2a83-4a57-80d8-d2cf7b128392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408844714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3408844714
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.789551161
Short name T1558
Test name
Test status
Simulation time 57912264521 ps
CPU time 89.73 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:44:06 PM PST 24
Peak memory 255496 kb
Host smart-e2cfb538-b163-4092-a055-bdc2758462a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789551161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.789551161
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3382881518
Short name T95
Test name
Test status
Simulation time 2972832793 ps
CPU time 19.42 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:42:57 PM PST 24
Peak memory 216320 kb
Host smart-f8a081ea-3388-4915-b6c7-a8d781e32edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382881518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3382881518
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.565618361
Short name T1264
Test name
Test status
Simulation time 23686477121 ps
CPU time 22.95 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:42 PM PST 24
Peak memory 215824 kb
Host smart-95300107-1e45-43da-b99c-0d1a678cfddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565618361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.565618361
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3390417044
Short name T702
Test name
Test status
Simulation time 261277598 ps
CPU time 2.29 seconds
Started Mar 07 02:44:19 PM PST 24
Finished Mar 07 02:44:21 PM PST 24
Peak memory 207564 kb
Host smart-85a0cb7d-395d-46fd-99d1-fe7b408734a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390417044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3390417044
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3821943284
Short name T1908
Test name
Test status
Simulation time 611905552 ps
CPU time 2.01 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 215728 kb
Host smart-e4d3998a-7fa8-4b70-8d5e-0afa67cbc488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821943284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3821943284
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2057357433
Short name T1439
Test name
Test status
Simulation time 84732086 ps
CPU time 2.29 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 216188 kb
Host smart-57ff7c64-26b6-4799-82ae-c798107917c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057357433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2057357433
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2534919547
Short name T1560
Test name
Test status
Simulation time 108191112 ps
CPU time 1.48 seconds
Started Mar 07 02:44:18 PM PST 24
Finished Mar 07 02:44:20 PM PST 24
Peak memory 215968 kb
Host smart-3f2d2fd3-5a72-4262-b43d-e671b8da15e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534919547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2534919547
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2839746806
Short name T1001
Test name
Test status
Simulation time 24451800 ps
CPU time 0.77 seconds
Started Mar 07 02:44:25 PM PST 24
Finished Mar 07 02:44:27 PM PST 24
Peak memory 204900 kb
Host smart-5d16ce35-375c-4803-ad31-72dcd8f54f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839746806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2839746806
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3288603451
Short name T426
Test name
Test status
Simulation time 170366084 ps
CPU time 0.84 seconds
Started Mar 07 12:42:33 PM PST 24
Finished Mar 07 12:42:34 PM PST 24
Peak memory 205372 kb
Host smart-38e93ac7-452a-4c24-91e1-94c2c67865b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288603451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3288603451
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3010646167
Short name T1519
Test name
Test status
Simulation time 11204093144 ps
CPU time 14.64 seconds
Started Mar 07 02:44:27 PM PST 24
Finished Mar 07 02:44:42 PM PST 24
Peak memory 248752 kb
Host smart-d4cfc489-714d-4838-82a8-86907fc8df7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010646167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3010646167
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_upload.3512674944
Short name T670
Test name
Test status
Simulation time 545853285 ps
CPU time 2.87 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 217280 kb
Host smart-fcf841a1-aa9c-4142-bac3-9770d1972093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512674944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3512674944
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1999490935
Short name T717
Test name
Test status
Simulation time 80392228 ps
CPU time 0.71 seconds
Started Mar 07 02:42:54 PM PST 24
Finished Mar 07 02:42:55 PM PST 24
Peak memory 204800 kb
Host smart-0396c4e1-a93b-4620-9414-5f6f7c92fcbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999490935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
999490935
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.756015874
Short name T373
Test name
Test status
Simulation time 50273850 ps
CPU time 0.73 seconds
Started Mar 07 12:41:04 PM PST 24
Finished Mar 07 12:41:04 PM PST 24
Peak memory 205140 kb
Host smart-fc0d876a-f6b5-45b1-b4ab-18b463275842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756015874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.756015874
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1902411086
Short name T1421
Test name
Test status
Simulation time 175126070 ps
CPU time 3.77 seconds
Started Mar 07 02:42:56 PM PST 24
Finished Mar 07 02:43:01 PM PST 24
Peak memory 233008 kb
Host smart-c38068c2-165b-4c08-bc9b-e6e25972c88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902411086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1902411086
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3155803801
Short name T474
Test name
Test status
Simulation time 738329348 ps
CPU time 4.12 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:41:01 PM PST 24
Peak memory 233604 kb
Host smart-0508bbb5-21cd-46ea-9e07-ac5d02116207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155803801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3155803801
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1019404974
Short name T534
Test name
Test status
Simulation time 63494141 ps
CPU time 0.82 seconds
Started Mar 07 02:43:00 PM PST 24
Finished Mar 07 02:43:01 PM PST 24
Peak memory 205732 kb
Host smart-f03aa1b4-9dce-45b9-8c77-0ea859528361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019404974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1019404974
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3428056345
Short name T468
Test name
Test status
Simulation time 64991734 ps
CPU time 0.77 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:01 PM PST 24
Peak memory 206372 kb
Host smart-1f89293f-f936-4991-ab81-acd8794f2a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428056345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3428056345
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1832234649
Short name T1623
Test name
Test status
Simulation time 2342638920 ps
CPU time 45.57 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:41:42 PM PST 24
Peak memory 249024 kb
Host smart-d942559d-2973-4b1e-88cd-c2b6470f3373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832234649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1832234649
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2749478934
Short name T36
Test name
Test status
Simulation time 969213647 ps
CPU time 14.99 seconds
Started Mar 07 02:43:00 PM PST 24
Finished Mar 07 02:43:16 PM PST 24
Peak memory 251752 kb
Host smart-1573bf80-3059-4925-a5f8-25cd84064eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749478934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2749478934
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2019053268
Short name T946
Test name
Test status
Simulation time 31272561318 ps
CPU time 219.75 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:44:36 PM PST 24
Peak memory 250156 kb
Host smart-54ffcb1c-f313-49fd-8d3c-78d3ae75d848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019053268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2019053268
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.264927384
Short name T673
Test name
Test status
Simulation time 22423718159 ps
CPU time 149.44 seconds
Started Mar 07 02:43:00 PM PST 24
Finished Mar 07 02:45:30 PM PST 24
Peak memory 264936 kb
Host smart-e1b7c3a4-eddc-4c11-a4ea-8074352d42ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264927384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.264927384
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1364116349
Short name T629
Test name
Test status
Simulation time 18587955124 ps
CPU time 151.01 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 268304 kb
Host smart-b2992045-14d0-4209-ba8d-7d23d0544239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364116349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1364116349
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.558735819
Short name T540
Test name
Test status
Simulation time 154892953818 ps
CPU time 93.5 seconds
Started Mar 07 02:43:01 PM PST 24
Finished Mar 07 02:44:34 PM PST 24
Peak memory 251620 kb
Host smart-55ac9936-3ccc-4393-9abe-cba542332f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558735819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
558735819
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1511557767
Short name T1165
Test name
Test status
Simulation time 44803547929 ps
CPU time 54.68 seconds
Started Mar 07 02:42:58 PM PST 24
Finished Mar 07 02:43:53 PM PST 24
Peak memory 239416 kb
Host smart-2f7645bc-8f84-4fd5-864f-5c60d12246f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511557767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1511557767
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.738702959
Short name T1038
Test name
Test status
Simulation time 23435586583 ps
CPU time 70.28 seconds
Started Mar 07 12:40:55 PM PST 24
Finished Mar 07 12:42:05 PM PST 24
Peak memory 251824 kb
Host smart-460f20a7-6c9a-43b1-a1c7-27c95d26a121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738702959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.738702959
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3342721985
Short name T260
Test name
Test status
Simulation time 386025542 ps
CPU time 3.54 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:03 PM PST 24
Peak memory 232988 kb
Host smart-ceca48ee-f8cb-4130-aa76-cb868949a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342721985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3342721985
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intercept.431515104
Short name T1837
Test name
Test status
Simulation time 1970087485 ps
CPU time 3.8 seconds
Started Mar 07 02:42:54 PM PST 24
Finished Mar 07 02:42:58 PM PST 24
Peak memory 218140 kb
Host smart-a8f51b0d-38b2-4370-a382-937c49a3fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431515104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.431515104
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1307064545
Short name T1856
Test name
Test status
Simulation time 9783266722 ps
CPU time 33.24 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:33 PM PST 24
Peak memory 249036 kb
Host smart-8cce9d34-9454-488e-b5b9-6e0037426a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307064545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1307064545
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3369903538
Short name T1212
Test name
Test status
Simulation time 1393057225 ps
CPU time 10.86 seconds
Started Mar 07 02:42:55 PM PST 24
Finished Mar 07 02:43:06 PM PST 24
Peak memory 247492 kb
Host smart-58f35a53-7bf8-4536-8f34-5ad8ba2e7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369903538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3369903538
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1234841327
Short name T445
Test name
Test status
Simulation time 49396371 ps
CPU time 1.01 seconds
Started Mar 07 02:42:54 PM PST 24
Finished Mar 07 02:42:55 PM PST 24
Peak memory 216004 kb
Host smart-a94530f1-c1ca-43a2-b774-4830f6b6e9c5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234841327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1234841327
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2491957415
Short name T1436
Test name
Test status
Simulation time 4593309413 ps
CPU time 13.87 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:14 PM PST 24
Peak memory 240880 kb
Host smart-998cd1be-d324-42e9-a1e7-2f3389784ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491957415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2491957415
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4268024834
Short name T1720
Test name
Test status
Simulation time 9598379140 ps
CPU time 10.9 seconds
Started Mar 07 02:43:00 PM PST 24
Finished Mar 07 02:43:11 PM PST 24
Peak memory 223984 kb
Host smart-696567ed-2f6e-4554-8c99-d22473acdfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268024834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4268024834
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3959232748
Short name T928
Test name
Test status
Simulation time 740574003 ps
CPU time 4.63 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:41:01 PM PST 24
Peak memory 233280 kb
Host smart-8114f851-e43d-46fc-9289-4764f1c3c623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959232748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3959232748
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.938548116
Short name T1862
Test name
Test status
Simulation time 8768462745 ps
CPU time 11.6 seconds
Started Mar 07 02:42:55 PM PST 24
Finished Mar 07 02:43:07 PM PST 24
Peak memory 216960 kb
Host smart-ec244364-6a62-421b-b5ef-212541290272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938548116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.938548116
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2007100957
Short name T715
Test name
Test status
Simulation time 22240105 ps
CPU time 0.7 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:40:57 PM PST 24
Peak memory 216128 kb
Host smart-73ebf5d8-e7fb-4e7d-8f1c-1568eeca4fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007100957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2007100957
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.64268038
Short name T994
Test name
Test status
Simulation time 15763865 ps
CPU time 0.76 seconds
Started Mar 07 02:42:57 PM PST 24
Finished Mar 07 02:42:58 PM PST 24
Peak memory 215640 kb
Host smart-f7b09f29-03bf-4c41-9d00-519917d92146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64268038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.64268038
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2378598927
Short name T1055
Test name
Test status
Simulation time 752715589 ps
CPU time 4.66 seconds
Started Mar 07 02:42:53 PM PST 24
Finished Mar 07 02:42:58 PM PST 24
Peak memory 217936 kb
Host smart-8af16831-ac4c-4e9b-8957-0540c9e15deb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2378598927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2378598927
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.514416619
Short name T900
Test name
Test status
Simulation time 357499991 ps
CPU time 3.24 seconds
Started Mar 07 12:40:57 PM PST 24
Finished Mar 07 12:41:01 PM PST 24
Peak memory 221488 kb
Host smart-eb805e6a-4a52-474b-a4e9-e6b283993f2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=514416619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.514416619
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1887961295
Short name T70
Test name
Test status
Simulation time 91983355 ps
CPU time 1.19 seconds
Started Mar 07 02:42:58 PM PST 24
Finished Mar 07 02:42:59 PM PST 24
Peak memory 235028 kb
Host smart-57ed19bb-ecdc-4272-aa1c-1e6db6c15485
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887961295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1887961295
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1964572722
Short name T71
Test name
Test status
Simulation time 32975049 ps
CPU time 1.07 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:40:58 PM PST 24
Peak memory 234560 kb
Host smart-71efab90-fb21-4c81-bbb1-c971dfc23a7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964572722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1964572722
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.16448190
Short name T1070
Test name
Test status
Simulation time 136215849 ps
CPU time 1.05 seconds
Started Mar 07 12:41:02 PM PST 24
Finished Mar 07 12:41:03 PM PST 24
Peak memory 205368 kb
Host smart-3174f10c-d2c6-439f-8f17-d2b782d21f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16448190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_
all.16448190
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1800497195
Short name T535
Test name
Test status
Simulation time 114158310805 ps
CPU time 330.56 seconds
Started Mar 07 02:42:55 PM PST 24
Finished Mar 07 02:48:26 PM PST 24
Peak memory 265040 kb
Host smart-978c708c-bf9a-4890-be5a-79ca7fde4974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800497195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1800497195
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2382100344
Short name T1256
Test name
Test status
Simulation time 2329025962 ps
CPU time 25.06 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:41:21 PM PST 24
Peak memory 216236 kb
Host smart-c26b1581-05a5-46d1-b05f-15395184fcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382100344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2382100344
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.419199950
Short name T989
Test name
Test status
Simulation time 7694196199 ps
CPU time 38.43 seconds
Started Mar 07 02:42:55 PM PST 24
Finished Mar 07 02:43:33 PM PST 24
Peak memory 218784 kb
Host smart-937c7db4-80f5-4160-b225-202e51a6d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419199950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.419199950
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1955264663
Short name T1603
Test name
Test status
Simulation time 15841025304 ps
CPU time 12.44 seconds
Started Mar 07 12:41:03 PM PST 24
Finished Mar 07 12:41:16 PM PST 24
Peak memory 216220 kb
Host smart-5b99ebc2-c4ce-419e-869b-95f18c459ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955264663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1955264663
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2507142587
Short name T343
Test name
Test status
Simulation time 10934854894 ps
CPU time 20.64 seconds
Started Mar 07 02:42:54 PM PST 24
Finished Mar 07 02:43:15 PM PST 24
Peak memory 215768 kb
Host smart-7bebe6d3-24ca-40bd-8402-2f790868169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507142587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2507142587
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.904380763
Short name T909
Test name
Test status
Simulation time 699205519 ps
CPU time 8.96 seconds
Started Mar 07 02:42:57 PM PST 24
Finished Mar 07 02:43:06 PM PST 24
Peak memory 215844 kb
Host smart-a220aa87-2491-4c30-86b9-6b1428aa5b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904380763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.904380763
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.908880380
Short name T1772
Test name
Test status
Simulation time 152232191 ps
CPU time 2.28 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:40:58 PM PST 24
Peak memory 216356 kb
Host smart-4de51373-d948-4c8e-b1c1-2813d6354f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908880380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.908880380
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.232303854
Short name T733
Test name
Test status
Simulation time 53845224 ps
CPU time 0.9 seconds
Started Mar 07 02:42:55 PM PST 24
Finished Mar 07 02:42:56 PM PST 24
Peak memory 205904 kb
Host smart-b587e874-134d-4a9e-a470-478423cb6afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232303854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.232303854
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3359926886
Short name T1754
Test name
Test status
Simulation time 122676165 ps
CPU time 0.82 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:01 PM PST 24
Peak memory 205500 kb
Host smart-26d54e49-57f8-46b9-88bd-4617b06771fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359926886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3359926886
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1826416484
Short name T1148
Test name
Test status
Simulation time 3925083221 ps
CPU time 15.31 seconds
Started Mar 07 02:43:00 PM PST 24
Finished Mar 07 02:43:16 PM PST 24
Peak memory 220836 kb
Host smart-b8dd4c73-88fe-4e36-b288-a88027fccb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826416484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1826416484
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_upload.2739226719
Short name T714
Test name
Test status
Simulation time 33527736514 ps
CPU time 26.38 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:26 PM PST 24
Peak memory 220248 kb
Host smart-5ecfa0bc-dd6d-4594-b368-6173ffa1d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739226719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2739226719
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1075436248
Short name T1492
Test name
Test status
Simulation time 72298000 ps
CPU time 0.72 seconds
Started Mar 07 02:44:27 PM PST 24
Finished Mar 07 02:44:29 PM PST 24
Peak memory 204384 kb
Host smart-509304f9-faea-4992-af96-8a42246f78ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075436248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1075436248
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1124360927
Short name T1527
Test name
Test status
Simulation time 24438576 ps
CPU time 0.77 seconds
Started Mar 07 12:42:35 PM PST 24
Finished Mar 07 12:42:35 PM PST 24
Peak memory 204568 kb
Host smart-ef6a61b3-baf2-47a3-9a86-2b2450bec524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124360927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1124360927
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1269212611
Short name T794
Test name
Test status
Simulation time 30926786 ps
CPU time 2.62 seconds
Started Mar 07 12:42:33 PM PST 24
Finished Mar 07 12:42:36 PM PST 24
Peak memory 232580 kb
Host smart-71c89926-12d2-4b5c-8596-ac8a5597da53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269212611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1269212611
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.424221641
Short name T225
Test name
Test status
Simulation time 385834207 ps
CPU time 4.18 seconds
Started Mar 07 02:44:26 PM PST 24
Finished Mar 07 02:44:31 PM PST 24
Peak memory 232840 kb
Host smart-cb8ccbcd-d1e3-44a2-8d90-53dfd6e70a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424221641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.424221641
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.312932298
Short name T1157
Test name
Test status
Simulation time 15285577 ps
CPU time 0.74 seconds
Started Mar 07 02:44:28 PM PST 24
Finished Mar 07 02:44:29 PM PST 24
Peak memory 204760 kb
Host smart-9ed0130a-bb22-47e8-9954-fa19ed14d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312932298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.312932298
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3548017958
Short name T505
Test name
Test status
Simulation time 20221601 ps
CPU time 0.79 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 205196 kb
Host smart-74b0c127-83eb-4006-8b5b-2d28afe09b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548017958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3548017958
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3415214510
Short name T1042
Test name
Test status
Simulation time 16030086505 ps
CPU time 82.66 seconds
Started Mar 07 12:42:33 PM PST 24
Finished Mar 07 12:43:56 PM PST 24
Peak memory 250276 kb
Host smart-cae2b53d-082a-47c4-b9a8-89c679237546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415214510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3415214510
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2366047481
Short name T859
Test name
Test status
Simulation time 10272266343 ps
CPU time 21.54 seconds
Started Mar 07 02:44:26 PM PST 24
Finished Mar 07 02:44:48 PM PST 24
Peak memory 220564 kb
Host smart-f0007223-11c6-4001-b642-8cc88f0de1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366047481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2366047481
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.328833077
Short name T1258
Test name
Test status
Simulation time 52873933886 ps
CPU time 364.45 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:48:41 PM PST 24
Peak memory 253112 kb
Host smart-f9426f79-57ba-45fb-972f-376147dac609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328833077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.328833077
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.215880948
Short name T1247
Test name
Test status
Simulation time 24661608950 ps
CPU time 102.26 seconds
Started Mar 07 02:44:30 PM PST 24
Finished Mar 07 02:46:13 PM PST 24
Peak memory 260644 kb
Host smart-c89e0831-29d8-4047-ac77-a55aa3667540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215880948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.215880948
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2849726531
Short name T94
Test name
Test status
Simulation time 48585904525 ps
CPU time 113.07 seconds
Started Mar 07 12:42:39 PM PST 24
Finished Mar 07 12:44:33 PM PST 24
Peak memory 254608 kb
Host smart-24319e27-e206-453d-9f6f-ad25bd9f2920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849726531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2849726531
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1683201855
Short name T1634
Test name
Test status
Simulation time 418587155 ps
CPU time 8.83 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:42:46 PM PST 24
Peak memory 240208 kb
Host smart-fd45b901-7f24-4b33-8c5b-346700abb9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683201855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1683201855
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1728651700
Short name T37
Test name
Test status
Simulation time 10391818165 ps
CPU time 26.28 seconds
Started Mar 07 02:44:29 PM PST 24
Finished Mar 07 02:44:56 PM PST 24
Peak memory 239672 kb
Host smart-c54836d0-4975-4ea6-9182-919126ac83b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728651700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1728651700
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1695478499
Short name T1046
Test name
Test status
Simulation time 3190274317 ps
CPU time 4.99 seconds
Started Mar 07 12:42:34 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 233188 kb
Host smart-3497fb75-8ea2-4bba-9d65-7c56ba136230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695478499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1695478499
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intercept.639697497
Short name T1536
Test name
Test status
Simulation time 4144518159 ps
CPU time 6.23 seconds
Started Mar 07 02:44:32 PM PST 24
Finished Mar 07 02:44:39 PM PST 24
Peak memory 232968 kb
Host smart-454e66a4-8784-4ad3-b9d8-926ee766263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639697497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.639697497
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3024556494
Short name T841
Test name
Test status
Simulation time 1866800299 ps
CPU time 3.81 seconds
Started Mar 07 02:44:32 PM PST 24
Finished Mar 07 02:44:36 PM PST 24
Peak memory 232968 kb
Host smart-72ca98f0-06de-4aed-af55-f2e5f3f768b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024556494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3024556494
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3686853411
Short name T972
Test name
Test status
Simulation time 144668779 ps
CPU time 4.09 seconds
Started Mar 07 12:42:34 PM PST 24
Finished Mar 07 12:42:38 PM PST 24
Peak memory 240772 kb
Host smart-4c87cdaa-dd96-4c5a-ae6c-1f755636ddce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686853411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3686853411
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1234588767
Short name T1483
Test name
Test status
Simulation time 5385396776 ps
CPU time 8.42 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:42:45 PM PST 24
Peak memory 233560 kb
Host smart-e4f718f0-6af2-4663-8cba-22a6956a52ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234588767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1234588767
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.756785221
Short name T276
Test name
Test status
Simulation time 33816802649 ps
CPU time 30.17 seconds
Started Mar 07 02:44:30 PM PST 24
Finished Mar 07 02:45:01 PM PST 24
Peak memory 232612 kb
Host smart-2536f69e-3fef-434f-ba54-3c5b27e2894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756785221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.756785221
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1820206675
Short name T1397
Test name
Test status
Simulation time 122785653 ps
CPU time 2.91 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 224364 kb
Host smart-b0e61e29-ebf9-459b-be0f-779057129a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820206675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1820206675
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.377166446
Short name T747
Test name
Test status
Simulation time 94340161343 ps
CPU time 13.99 seconds
Started Mar 07 02:44:25 PM PST 24
Finished Mar 07 02:44:40 PM PST 24
Peak memory 223852 kb
Host smart-36f0b0b7-dd02-4624-bdde-7da5f98d0e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377166446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.377166446
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2191614550
Short name T547
Test name
Test status
Simulation time 508135751 ps
CPU time 3.62 seconds
Started Mar 07 02:44:30 PM PST 24
Finished Mar 07 02:44:34 PM PST 24
Peak memory 222160 kb
Host smart-557768f1-97cf-4cc9-bd2e-eb37afa06daa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2191614550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2191614550
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3649065763
Short name T1637
Test name
Test status
Simulation time 78192839 ps
CPU time 3.04 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 220112 kb
Host smart-6f1ed2a2-4496-4e52-97ce-4601d5b87aba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3649065763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3649065763
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2708809012
Short name T738
Test name
Test status
Simulation time 116383065 ps
CPU time 0.93 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:44:35 PM PST 24
Peak memory 205940 kb
Host smart-270feaea-3f58-406b-9feb-2c9f56404da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708809012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2708809012
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3408332867
Short name T1268
Test name
Test status
Simulation time 385912337499 ps
CPU time 1180.34 seconds
Started Mar 07 12:42:39 PM PST 24
Finished Mar 07 01:02:20 PM PST 24
Peak memory 290084 kb
Host smart-6afd8a2f-30f5-4c50-b94c-dc072828b61a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408332867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3408332867
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1335304953
Short name T1004
Test name
Test status
Simulation time 8086196768 ps
CPU time 30.59 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:43:07 PM PST 24
Peak memory 216308 kb
Host smart-f5221c12-bb09-4a7c-be85-d92c3dd5622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335304953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1335304953
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2069773258
Short name T566
Test name
Test status
Simulation time 3702300483 ps
CPU time 23.81 seconds
Started Mar 07 02:44:25 PM PST 24
Finished Mar 07 02:44:50 PM PST 24
Peak memory 215872 kb
Host smart-44b954c4-a392-4db7-89cd-b6a6c586ffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069773258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2069773258
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2910978347
Short name T98
Test name
Test status
Simulation time 4573992508 ps
CPU time 18.94 seconds
Started Mar 07 02:44:25 PM PST 24
Finished Mar 07 02:44:45 PM PST 24
Peak memory 215864 kb
Host smart-232465e1-aa67-4ced-9280-8ac4a34ed8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910978347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2910978347
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3153613705
Short name T501
Test name
Test status
Simulation time 5607215547 ps
CPU time 15.58 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:42:52 PM PST 24
Peak memory 216220 kb
Host smart-1d8f3d79-8ea0-40e8-aff0-2fff56a109ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153613705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3153613705
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1680994553
Short name T1776
Test name
Test status
Simulation time 185094714 ps
CPU time 2.51 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:42:40 PM PST 24
Peak memory 216192 kb
Host smart-130c3ade-0320-4e57-8cab-567c089e54f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680994553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1680994553
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4193805170
Short name T515
Test name
Test status
Simulation time 169949179 ps
CPU time 2.62 seconds
Started Mar 07 02:44:29 PM PST 24
Finished Mar 07 02:44:33 PM PST 24
Peak memory 215600 kb
Host smart-c412f4ac-c8fc-4c27-8c35-c25840f380d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193805170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4193805170
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2378179582
Short name T1311
Test name
Test status
Simulation time 212084883 ps
CPU time 0.86 seconds
Started Mar 07 02:44:25 PM PST 24
Finished Mar 07 02:44:26 PM PST 24
Peak memory 204892 kb
Host smart-ab6f86bd-9228-4dc6-8420-3fdc87e8a49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378179582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2378179582
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.504596545
Short name T637
Test name
Test status
Simulation time 148127446 ps
CPU time 1.02 seconds
Started Mar 07 12:42:38 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 206516 kb
Host smart-67737c93-dc44-4aab-86eb-009b90e684d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504596545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.504596545
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2690889031
Short name T917
Test name
Test status
Simulation time 1198585017 ps
CPU time 6.63 seconds
Started Mar 07 02:44:27 PM PST 24
Finished Mar 07 02:44:35 PM PST 24
Peak memory 237796 kb
Host smart-c89c9881-b353-4aba-a88a-26a403e67ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690889031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2690889031
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_upload.3280176284
Short name T1781
Test name
Test status
Simulation time 1690173970 ps
CPU time 9.15 seconds
Started Mar 07 12:42:39 PM PST 24
Finished Mar 07 12:42:49 PM PST 24
Peak memory 234228 kb
Host smart-dbf7b0d9-6db8-4aac-afd8-e0ee6d6877f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280176284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3280176284
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2200276696
Short name T938
Test name
Test status
Simulation time 40811610 ps
CPU time 0.7 seconds
Started Mar 07 12:42:38 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 205028 kb
Host smart-5c474906-d0fd-4e24-9ccf-5431272a82da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200276696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2200276696
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.531950177
Short name T950
Test name
Test status
Simulation time 12852692 ps
CPU time 0.72 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:44:35 PM PST 24
Peak memory 204816 kb
Host smart-316609ad-a8d8-4a20-bc91-8ad4dd3f2ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531950177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.531950177
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1219452481
Short name T1294
Test name
Test status
Simulation time 972533202 ps
CPU time 6.59 seconds
Started Mar 07 02:44:35 PM PST 24
Finished Mar 07 02:44:42 PM PST 24
Peak memory 232916 kb
Host smart-d09be65f-f9cb-4986-b189-11d9a93b6cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219452481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1219452481
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3310457802
Short name T1109
Test name
Test status
Simulation time 1884005017 ps
CPU time 4.19 seconds
Started Mar 07 12:42:41 PM PST 24
Finished Mar 07 12:42:46 PM PST 24
Peak memory 233668 kb
Host smart-5ff7134e-bb44-4607-b4aa-e92a4c9c32a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310457802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3310457802
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3789827329
Short name T1863
Test name
Test status
Simulation time 16285423 ps
CPU time 0.73 seconds
Started Mar 07 12:42:35 PM PST 24
Finished Mar 07 12:42:36 PM PST 24
Peak memory 205108 kb
Host smart-52d6aade-25da-4377-8628-32f2f5d1a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789827329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3789827329
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3950448300
Short name T1091
Test name
Test status
Simulation time 12307777 ps
CPU time 0.74 seconds
Started Mar 07 02:44:29 PM PST 24
Finished Mar 07 02:44:30 PM PST 24
Peak memory 204488 kb
Host smart-f3a23ab2-50ed-4ccc-8b6a-1076fd11edcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950448300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3950448300
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1595064435
Short name T1476
Test name
Test status
Simulation time 421649066089 ps
CPU time 289.07 seconds
Started Mar 07 02:44:32 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 271104 kb
Host smart-414a15e2-ef1f-42e6-b289-820b2575a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595064435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1595064435
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3115939587
Short name T277
Test name
Test status
Simulation time 232009019757 ps
CPU time 262.26 seconds
Started Mar 07 12:42:41 PM PST 24
Finished Mar 07 12:47:04 PM PST 24
Peak memory 257232 kb
Host smart-d8c36818-5913-4bd0-bb8f-74fd7b4cf1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115939587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3115939587
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3891833118
Short name T209
Test name
Test status
Simulation time 87901399967 ps
CPU time 168.95 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:47:23 PM PST 24
Peak memory 253460 kb
Host smart-13edaa2d-3284-4919-a121-8afa11f5970a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891833118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3891833118
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3571859449
Short name T792
Test name
Test status
Simulation time 5222495160 ps
CPU time 93.18 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:44:09 PM PST 24
Peak memory 265720 kb
Host smart-010e14e7-7ca1-493b-827a-82a71f1adb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571859449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3571859449
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.783642012
Short name T1594
Test name
Test status
Simulation time 105769067203 ps
CPU time 231.58 seconds
Started Mar 07 02:44:38 PM PST 24
Finished Mar 07 02:48:30 PM PST 24
Peak memory 261652 kb
Host smart-d7bc722f-4542-436c-a242-1f1fa2f96468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783642012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.783642012
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.467411201
Short name T591
Test name
Test status
Simulation time 2646393662 ps
CPU time 20.13 seconds
Started Mar 07 02:44:33 PM PST 24
Finished Mar 07 02:44:53 PM PST 24
Peak memory 240228 kb
Host smart-910fb9f4-d75f-41af-b236-ee3b2f02090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467411201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.467411201
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.963760001
Short name T1732
Test name
Test status
Simulation time 2235104077 ps
CPU time 19.99 seconds
Started Mar 07 12:42:38 PM PST 24
Finished Mar 07 12:42:59 PM PST 24
Peak memory 224580 kb
Host smart-18a97368-7c3e-428a-b8f9-8c1bb43a27c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963760001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.963760001
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.115514501
Short name T1407
Test name
Test status
Simulation time 1057217441 ps
CPU time 5.27 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:44:40 PM PST 24
Peak memory 218132 kb
Host smart-99f227b5-abb6-4498-b51f-83e60c4b1de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115514501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.115514501
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_intercept.532787843
Short name T417
Test name
Test status
Simulation time 1640925623 ps
CPU time 4.78 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:42:42 PM PST 24
Peak memory 235160 kb
Host smart-ce5e2236-a57d-42c4-a363-1cd20777c161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532787843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.532787843
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.410571622
Short name T50
Test name
Test status
Simulation time 41278944503 ps
CPU time 34.73 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:45:09 PM PST 24
Peak memory 230152 kb
Host smart-f3c2ea45-d0a9-40ac-bcd7-e2b13f5f1a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410571622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.410571622
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.974114278
Short name T585
Test name
Test status
Simulation time 285815437 ps
CPU time 6.34 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:42:44 PM PST 24
Peak memory 238324 kb
Host smart-82142738-cae1-4cae-b20c-609dc63cb155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974114278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.974114278
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3199830199
Short name T806
Test name
Test status
Simulation time 14748743772 ps
CPU time 12.59 seconds
Started Mar 07 02:44:39 PM PST 24
Finished Mar 07 02:44:52 PM PST 24
Peak memory 227484 kb
Host smart-3820f536-a8e2-4e32-bb81-296f3b8ce08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199830199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3199830199
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.914653330
Short name T377
Test name
Test status
Simulation time 241040774 ps
CPU time 2.51 seconds
Started Mar 07 12:42:38 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 218404 kb
Host smart-2b563bb7-5aaf-40ae-bbde-d197c3151f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914653330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.914653330
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.7245619
Short name T1164
Test name
Test status
Simulation time 7500623989 ps
CPU time 8.68 seconds
Started Mar 07 12:42:38 PM PST 24
Finished Mar 07 12:42:48 PM PST 24
Peak memory 233608 kb
Host smart-baf44bf4-0c72-4d10-89aa-aa16c2fdecb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7245619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.7245619
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.773212525
Short name T1199
Test name
Test status
Simulation time 1715891488 ps
CPU time 6.7 seconds
Started Mar 07 02:44:35 PM PST 24
Finished Mar 07 02:44:42 PM PST 24
Peak memory 232016 kb
Host smart-940da518-e738-4a7e-88dd-fdf612057f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773212525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.773212525
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2660497521
Short name T486
Test name
Test status
Simulation time 569297653 ps
CPU time 3.44 seconds
Started Mar 07 02:44:35 PM PST 24
Finished Mar 07 02:44:38 PM PST 24
Peak memory 215808 kb
Host smart-64cf5dd6-25ed-458a-8bd8-e70829a91363
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660497521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2660497521
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3310180198
Short name T982
Test name
Test status
Simulation time 196642911 ps
CPU time 3.2 seconds
Started Mar 07 12:42:41 PM PST 24
Finished Mar 07 12:42:45 PM PST 24
Peak memory 218496 kb
Host smart-b931c777-3514-4add-89c3-8f0c92c6a5b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3310180198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3310180198
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2901899923
Short name T1629
Test name
Test status
Simulation time 2083891158 ps
CPU time 33.42 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:43:14 PM PST 24
Peak memory 221520 kb
Host smart-f1e3d379-4550-472e-b075-d072c7ffa1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901899923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2901899923
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2459078234
Short name T1284
Test name
Test status
Simulation time 24873982755 ps
CPU time 34.66 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:45:08 PM PST 24
Peak memory 215812 kb
Host smart-be06fc08-e8f3-4eaf-86e6-9169b08a8a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459078234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2459078234
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4248605468
Short name T1798
Test name
Test status
Simulation time 7194935433 ps
CPU time 28.24 seconds
Started Mar 07 12:42:36 PM PST 24
Finished Mar 07 12:43:05 PM PST 24
Peak memory 216404 kb
Host smart-c0e17ba2-441c-48d5-86b1-fece0be5298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248605468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4248605468
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2194212594
Short name T1331
Test name
Test status
Simulation time 2067587699 ps
CPU time 5.54 seconds
Started Mar 07 12:42:35 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 216172 kb
Host smart-6885c0c9-57f5-436f-b76e-55f36cf827c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194212594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2194212594
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.440499781
Short name T1112
Test name
Test status
Simulation time 27900038763 ps
CPU time 6.3 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:44:40 PM PST 24
Peak memory 215828 kb
Host smart-5d536264-b675-4c78-b85a-8cacb3854af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440499781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.440499781
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3850936130
Short name T949
Test name
Test status
Simulation time 149472875 ps
CPU time 1.74 seconds
Started Mar 07 02:44:26 PM PST 24
Finished Mar 07 02:44:29 PM PST 24
Peak memory 215724 kb
Host smart-76f85392-8568-4c58-8e00-8ae9974427c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850936130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3850936130
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3869380279
Short name T1845
Test name
Test status
Simulation time 234723066 ps
CPU time 2.28 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:42:43 PM PST 24
Peak memory 216088 kb
Host smart-ecc66072-fc8a-4431-81f9-c3361ec1eb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869380279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3869380279
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1272223610
Short name T808
Test name
Test status
Simulation time 33246540 ps
CPU time 0.91 seconds
Started Mar 07 02:44:30 PM PST 24
Finished Mar 07 02:44:31 PM PST 24
Peak memory 204796 kb
Host smart-029847be-14b9-4703-afeb-23568be56d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272223610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1272223610
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.222015850
Short name T1717
Test name
Test status
Simulation time 87336824 ps
CPU time 0.75 seconds
Started Mar 07 12:42:33 PM PST 24
Finished Mar 07 12:42:34 PM PST 24
Peak memory 205492 kb
Host smart-1e6f3699-1b4c-47c3-b183-63f18dec9614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222015850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.222015850
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1572054
Short name T1200
Test name
Test status
Simulation time 1999451924 ps
CPU time 7.1 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:42:47 PM PST 24
Peak memory 218884 kb
Host smart-5654e1cb-094c-4051-9aca-429db06724c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1572054
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_upload.3488097915
Short name T750
Test name
Test status
Simulation time 1129238830 ps
CPU time 2.2 seconds
Started Mar 07 02:44:33 PM PST 24
Finished Mar 07 02:44:36 PM PST 24
Peak memory 215716 kb
Host smart-788a06d9-502c-4b8a-9724-9cf22a8960b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488097915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3488097915
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2528706234
Short name T1648
Test name
Test status
Simulation time 15479772 ps
CPU time 0.75 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:42:38 PM PST 24
Peak memory 205164 kb
Host smart-bfdc4f19-b692-4733-b161-b344bcc62bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528706234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2528706234
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2922584742
Short name T1882
Test name
Test status
Simulation time 15635508 ps
CPU time 0.71 seconds
Started Mar 07 02:44:42 PM PST 24
Finished Mar 07 02:44:43 PM PST 24
Peak memory 203844 kb
Host smart-96ce59a2-4029-4a55-bc7c-431065011055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922584742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2922584742
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2327400039
Short name T1559
Test name
Test status
Simulation time 36411858 ps
CPU time 2.25 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:42:43 PM PST 24
Peak memory 233648 kb
Host smart-4f3a72a4-ff93-4371-8a18-5ffbba6c8177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327400039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2327400039
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3109790475
Short name T698
Test name
Test status
Simulation time 94701645 ps
CPU time 2.43 seconds
Started Mar 07 02:44:45 PM PST 24
Finished Mar 07 02:44:48 PM PST 24
Peak memory 232920 kb
Host smart-0cbb3870-856f-4b55-b6b3-2c49717c4b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109790475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3109790475
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2054643930
Short name T1718
Test name
Test status
Simulation time 64469836 ps
CPU time 0.75 seconds
Started Mar 07 12:42:38 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 205144 kb
Host smart-b5db6e80-7c08-43c1-b6a4-c0eb344f25ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054643930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2054643930
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4191679462
Short name T1451
Test name
Test status
Simulation time 29036463 ps
CPU time 0.77 seconds
Started Mar 07 02:44:35 PM PST 24
Finished Mar 07 02:44:36 PM PST 24
Peak memory 205464 kb
Host smart-375d89cd-f040-469c-a419-5bd12b6578c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191679462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4191679462
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1569092379
Short name T1592
Test name
Test status
Simulation time 52465237062 ps
CPU time 236.26 seconds
Started Mar 07 12:42:41 PM PST 24
Finished Mar 07 12:46:38 PM PST 24
Peak memory 273000 kb
Host smart-38a98edd-9156-42ee-ab59-fa8ccb034b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569092379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1569092379
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1858341667
Short name T289
Test name
Test status
Simulation time 17837372727 ps
CPU time 123.15 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:46:47 PM PST 24
Peak memory 262676 kb
Host smart-4cc9aa1f-0a8e-458f-893b-f87c756b1ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858341667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1858341667
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2968733280
Short name T598
Test name
Test status
Simulation time 5578838530 ps
CPU time 86.56 seconds
Started Mar 07 02:44:45 PM PST 24
Finished Mar 07 02:46:12 PM PST 24
Peak memory 273184 kb
Host smart-c3c84d29-f224-4532-8086-78487cb69cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968733280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2968733280
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.864602751
Short name T1546
Test name
Test status
Simulation time 23952943790 ps
CPU time 167.25 seconds
Started Mar 07 12:42:41 PM PST 24
Finished Mar 07 12:45:29 PM PST 24
Peak memory 250160 kb
Host smart-7c2627d1-852a-417c-8579-7aeb09d9ba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864602751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.864602751
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2614420391
Short name T1132
Test name
Test status
Simulation time 223878599964 ps
CPU time 365.82 seconds
Started Mar 07 12:42:41 PM PST 24
Finished Mar 07 12:48:47 PM PST 24
Peak memory 249208 kb
Host smart-adcebd57-fb14-47ee-9ab7-25dcc6d8655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614420391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2614420391
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3904988280
Short name T81
Test name
Test status
Simulation time 204197499785 ps
CPU time 259.56 seconds
Started Mar 07 02:44:46 PM PST 24
Finished Mar 07 02:49:06 PM PST 24
Peak memory 254608 kb
Host smart-c8ea7fb9-3820-4fc6-8d2f-4272b7e6a794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904988280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3904988280
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2550245486
Short name T455
Test name
Test status
Simulation time 54812549954 ps
CPU time 29.57 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:43:08 PM PST 24
Peak memory 240788 kb
Host smart-cb92d965-c929-4a42-b242-002e2269950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550245486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2550245486
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1741073317
Short name T1362
Test name
Test status
Simulation time 2776244662 ps
CPU time 5.38 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:44:40 PM PST 24
Peak memory 233036 kb
Host smart-313b728b-bed7-4e18-b214-88c55617132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741073317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1741073317
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intercept.950406925
Short name T1262
Test name
Test status
Simulation time 1079029927 ps
CPU time 4.83 seconds
Started Mar 07 12:42:38 PM PST 24
Finished Mar 07 12:42:44 PM PST 24
Peak memory 218560 kb
Host smart-72e9a547-ed03-4a84-9c4b-7ee41fcdf1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950406925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.950406925
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1184833653
Short name T1911
Test name
Test status
Simulation time 400554506 ps
CPU time 2.87 seconds
Started Mar 07 02:44:46 PM PST 24
Finished Mar 07 02:44:49 PM PST 24
Peak memory 217808 kb
Host smart-bf584b6e-95ca-4f34-ae5a-3311ee581b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184833653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1184833653
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2165382648
Short name T679
Test name
Test status
Simulation time 22774543436 ps
CPU time 58.73 seconds
Started Mar 07 12:42:43 PM PST 24
Finished Mar 07 12:43:42 PM PST 24
Peak memory 228040 kb
Host smart-e730bd33-9b3d-448f-9cc2-3999383ec8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165382648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2165382648
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2198663664
Short name T916
Test name
Test status
Simulation time 10623436584 ps
CPU time 28.12 seconds
Started Mar 07 12:42:41 PM PST 24
Finished Mar 07 12:43:10 PM PST 24
Peak memory 232820 kb
Host smart-89112b47-2628-4af8-b49a-44a4c9c8f3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198663664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2198663664
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3557354418
Short name T307
Test name
Test status
Simulation time 2252669512 ps
CPU time 5.26 seconds
Started Mar 07 02:44:39 PM PST 24
Finished Mar 07 02:44:45 PM PST 24
Peak memory 223812 kb
Host smart-2de3cc4f-f465-4096-89ab-bf9dc8dab714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557354418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3557354418
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1822636065
Short name T1033
Test name
Test status
Simulation time 3240098570 ps
CPU time 4.92 seconds
Started Mar 07 12:42:35 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 224356 kb
Host smart-00a868aa-2ed7-4943-999d-fec82aea0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822636065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1822636065
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2665749019
Short name T1026
Test name
Test status
Simulation time 4661130805 ps
CPU time 15.29 seconds
Started Mar 07 02:44:35 PM PST 24
Finished Mar 07 02:44:50 PM PST 24
Peak memory 223212 kb
Host smart-49e09b75-83fc-41f0-b4ad-293a6728e49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665749019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2665749019
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4007310453
Short name T440
Test name
Test status
Simulation time 692872504 ps
CPU time 5.09 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:42:46 PM PST 24
Peak memory 222876 kb
Host smart-6223c9ca-05e1-4b33-a19c-6ef14ed91cd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4007310453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4007310453
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.759951531
Short name T974
Test name
Test status
Simulation time 1896881461 ps
CPU time 5.61 seconds
Started Mar 07 02:44:41 PM PST 24
Finished Mar 07 02:44:46 PM PST 24
Peak memory 222112 kb
Host smart-479374db-e2cb-42b7-8124-3cb4128edbd7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=759951531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.759951531
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2131260014
Short name T1060
Test name
Test status
Simulation time 210170914 ps
CPU time 1 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:44:45 PM PST 24
Peak memory 206056 kb
Host smart-f3508943-804b-4021-a7de-a7f763886f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131260014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2131260014
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4224256650
Short name T962
Test name
Test status
Simulation time 81791840976 ps
CPU time 315.62 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:47:53 PM PST 24
Peak memory 271024 kb
Host smart-4020b365-fe97-44ed-88e1-de90006ffa60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224256650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4224256650
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.103494458
Short name T770
Test name
Test status
Simulation time 7973909539 ps
CPU time 27.52 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:43:08 PM PST 24
Peak memory 216180 kb
Host smart-4379baab-02f8-4ae0-8dba-7ff8b05082b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103494458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.103494458
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1140489380
Short name T1763
Test name
Test status
Simulation time 14896247092 ps
CPU time 32.73 seconds
Started Mar 07 02:44:35 PM PST 24
Finished Mar 07 02:45:08 PM PST 24
Peak memory 215792 kb
Host smart-5cc4ec51-5bda-40af-923a-9187394ffb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140489380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1140489380
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3271508894
Short name T1183
Test name
Test status
Simulation time 560783049 ps
CPU time 3.75 seconds
Started Mar 07 02:44:36 PM PST 24
Finished Mar 07 02:44:39 PM PST 24
Peak memory 215632 kb
Host smart-ebbac9f8-51d6-454f-bc6b-229cabd9d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271508894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3271508894
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3403247064
Short name T1526
Test name
Test status
Simulation time 32197444155 ps
CPU time 23.89 seconds
Started Mar 07 12:42:37 PM PST 24
Finished Mar 07 12:43:01 PM PST 24
Peak memory 216240 kb
Host smart-47901cb6-885f-4fbb-8920-973fe8dda7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403247064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3403247064
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.199040751
Short name T1466
Test name
Test status
Simulation time 931406285 ps
CPU time 4.19 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:42:45 PM PST 24
Peak memory 216216 kb
Host smart-9fb1e2a8-ccc4-4a74-9513-5c38b41d4bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199040751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.199040751
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2996662206
Short name T1827
Test name
Test status
Simulation time 56501953 ps
CPU time 0.75 seconds
Started Mar 07 02:44:39 PM PST 24
Finished Mar 07 02:44:40 PM PST 24
Peak memory 204888 kb
Host smart-d939caa7-768e-4370-9e9c-65d72451611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996662206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2996662206
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1039783557
Short name T512
Test name
Test status
Simulation time 49954848 ps
CPU time 0.8 seconds
Started Mar 07 02:44:34 PM PST 24
Finished Mar 07 02:44:35 PM PST 24
Peak memory 204812 kb
Host smart-60e2de01-d987-4b49-96cc-8c776356c8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039783557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1039783557
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.296454442
Short name T548
Test name
Test status
Simulation time 119243696 ps
CPU time 0.81 seconds
Started Mar 07 12:42:40 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 205384 kb
Host smart-4881ce64-6b4a-4d5c-a8ce-30503ff48b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296454442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.296454442
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2784787706
Short name T635
Test name
Test status
Simulation time 355365376 ps
CPU time 3.94 seconds
Started Mar 07 12:42:43 PM PST 24
Finished Mar 07 12:42:47 PM PST 24
Peak memory 234208 kb
Host smart-25630cee-81cb-4ce1-a470-f2ed68d4108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784787706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2784787706
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_upload.488538756
Short name T198
Test name
Test status
Simulation time 17008671141 ps
CPU time 14.7 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:44:58 PM PST 24
Peak memory 217884 kb
Host smart-7e527a0f-b6d6-4654-bdf3-cc76d7816f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488538756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.488538756
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2172371919
Short name T1083
Test name
Test status
Simulation time 40674501 ps
CPU time 0.7 seconds
Started Mar 07 02:44:41 PM PST 24
Finished Mar 07 02:44:43 PM PST 24
Peak memory 203892 kb
Host smart-a0379223-5d9e-4747-b399-cb5ffc6f319f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172371919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2172371919
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3070045431
Short name T1696
Test name
Test status
Simulation time 34533995 ps
CPU time 0.71 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:42:58 PM PST 24
Peak memory 204504 kb
Host smart-12beb4f2-b25f-48d3-b3ea-cff251a83a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070045431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3070045431
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1309764231
Short name T935
Test name
Test status
Simulation time 4505667465 ps
CPU time 8.41 seconds
Started Mar 07 02:44:46 PM PST 24
Finished Mar 07 02:44:54 PM PST 24
Peak memory 218912 kb
Host smart-e4180ee8-9202-47e7-abd9-69f17ae9e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309764231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1309764231
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.520687272
Short name T11
Test name
Test status
Simulation time 766127631 ps
CPU time 3.97 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:42:49 PM PST 24
Peak memory 219824 kb
Host smart-e46931e1-c642-40a4-b352-a4be834a667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520687272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.520687272
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3912807621
Short name T1793
Test name
Test status
Simulation time 37881820 ps
CPU time 0.73 seconds
Started Mar 07 02:44:45 PM PST 24
Finished Mar 07 02:44:46 PM PST 24
Peak memory 204660 kb
Host smart-3f19efe7-a674-467d-af4e-1074596a8545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912807621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3912807621
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4038816340
Short name T1099
Test name
Test status
Simulation time 25620225 ps
CPU time 0.75 seconds
Started Mar 07 12:42:44 PM PST 24
Finished Mar 07 12:42:44 PM PST 24
Peak memory 205564 kb
Host smart-97300d53-67c6-4d47-a5c4-462f3aad75cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038816340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4038816340
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1857111208
Short name T1883
Test name
Test status
Simulation time 467768362286 ps
CPU time 202.08 seconds
Started Mar 07 12:42:48 PM PST 24
Finished Mar 07 12:46:10 PM PST 24
Peak memory 250016 kb
Host smart-49f27ac7-fb65-4148-abd8-47c4f0cbd4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857111208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1857111208
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3881481978
Short name T1885
Test name
Test status
Simulation time 94786835148 ps
CPU time 206.68 seconds
Started Mar 07 02:44:42 PM PST 24
Finished Mar 07 02:48:10 PM PST 24
Peak memory 248456 kb
Host smart-4dbdf431-4b55-4845-ad42-2855c0b8313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881481978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3881481978
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1518669293
Short name T542
Test name
Test status
Simulation time 10719609546 ps
CPU time 64.13 seconds
Started Mar 07 02:44:44 PM PST 24
Finished Mar 07 02:45:49 PM PST 24
Peak memory 250220 kb
Host smart-61d9593d-dfa4-4fa3-bf84-39b6e2567a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518669293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1518669293
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.539924183
Short name T953
Test name
Test status
Simulation time 7744270772 ps
CPU time 31.39 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:43:21 PM PST 24
Peak memory 233856 kb
Host smart-e2792287-b342-46f3-b272-8e32fa7b474b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539924183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.539924183
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3252126941
Short name T1785
Test name
Test status
Simulation time 76388327561 ps
CPU time 192.02 seconds
Started Mar 07 12:42:53 PM PST 24
Finished Mar 07 12:46:06 PM PST 24
Peak memory 255764 kb
Host smart-ea562263-bcab-493a-9713-5f35112ed8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252126941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3252126941
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1989619550
Short name T1170
Test name
Test status
Simulation time 9186747966 ps
CPU time 24.84 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:43:10 PM PST 24
Peak memory 233804 kb
Host smart-e2781b1b-6284-4e53-a271-7db2dbe449a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989619550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1989619550
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2245423457
Short name T648
Test name
Test status
Simulation time 5626034225 ps
CPU time 28.44 seconds
Started Mar 07 02:44:44 PM PST 24
Finished Mar 07 02:45:13 PM PST 24
Peak memory 239400 kb
Host smart-c3b35be0-0aac-446b-b71d-a5dd1be98528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245423457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2245423457
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1808916270
Short name T333
Test name
Test status
Simulation time 279243731 ps
CPU time 2.85 seconds
Started Mar 07 02:44:42 PM PST 24
Finished Mar 07 02:44:45 PM PST 24
Peak memory 232024 kb
Host smart-5b4db595-9b71-4d93-a03c-a2f1a945e2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808916270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1808916270
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3718671259
Short name T708
Test name
Test status
Simulation time 593057498 ps
CPU time 3.86 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:42:49 PM PST 24
Peak memory 217556 kb
Host smart-7bac366e-afc6-4893-91d8-e60bd9b1352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718671259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3718671259
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1316526798
Short name T1448
Test name
Test status
Simulation time 243269937432 ps
CPU time 40.49 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:43:26 PM PST 24
Peak memory 228220 kb
Host smart-1a7efd22-2bc6-400e-b173-cecee17e29b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316526798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1316526798
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4031109198
Short name T1416
Test name
Test status
Simulation time 6066935900 ps
CPU time 18.89 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:45:03 PM PST 24
Peak memory 237964 kb
Host smart-c983fc39-0b2b-4cdf-8403-16a5b2641200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031109198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4031109198
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1867048451
Short name T1088
Test name
Test status
Simulation time 723366165 ps
CPU time 5.37 seconds
Started Mar 07 12:42:48 PM PST 24
Finished Mar 07 12:42:54 PM PST 24
Peak memory 224468 kb
Host smart-f03079bf-9b55-4dcf-a622-bdf4f5247623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867048451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1867048451
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.779876824
Short name T1414
Test name
Test status
Simulation time 2637852318 ps
CPU time 10.71 seconds
Started Mar 07 02:44:44 PM PST 24
Finished Mar 07 02:44:55 PM PST 24
Peak memory 228324 kb
Host smart-e2b71682-4693-4d3d-b9c3-54ea573051bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779876824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.779876824
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.162883958
Short name T970
Test name
Test status
Simulation time 143095797 ps
CPU time 2.33 seconds
Started Mar 07 02:44:46 PM PST 24
Finished Mar 07 02:44:48 PM PST 24
Peak memory 232136 kb
Host smart-a98dbeba-85c7-4c09-bc8a-d8c81b8b4557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162883958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.162883958
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2758328636
Short name T237
Test name
Test status
Simulation time 1280913006 ps
CPU time 2.85 seconds
Started Mar 07 12:42:48 PM PST 24
Finished Mar 07 12:42:51 PM PST 24
Peak memory 224372 kb
Host smart-2189cff3-9488-4bf6-80f8-32d713c00a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758328636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2758328636
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.110910867
Short name T1681
Test name
Test status
Simulation time 5876441580 ps
CPU time 5.33 seconds
Started Mar 07 12:42:44 PM PST 24
Finished Mar 07 12:42:49 PM PST 24
Peak memory 219936 kb
Host smart-5dcf93ee-9eb9-452c-a6af-c6eea90ff001
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=110910867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.110910867
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.79125331
Short name T352
Test name
Test status
Simulation time 1596781846 ps
CPU time 3.51 seconds
Started Mar 07 02:44:45 PM PST 24
Finished Mar 07 02:44:49 PM PST 24
Peak memory 218284 kb
Host smart-052ef6c9-0795-4337-87c1-5f286d17ba26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=79125331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.79125331
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1552626948
Short name T1537
Test name
Test status
Simulation time 802366698905 ps
CPU time 632.83 seconds
Started Mar 07 12:42:46 PM PST 24
Finished Mar 07 12:53:19 PM PST 24
Peak memory 273344 kb
Host smart-875c9f15-fb80-4dac-8c67-c2ad78011179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552626948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1552626948
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2895190113
Short name T1694
Test name
Test status
Simulation time 75170825216 ps
CPU time 237.06 seconds
Started Mar 07 02:44:42 PM PST 24
Finished Mar 07 02:48:40 PM PST 24
Peak memory 248636 kb
Host smart-8b1e6e62-d5f0-4eb7-85f2-35e560981a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895190113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2895190113
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2319848983
Short name T358
Test name
Test status
Simulation time 2859408280 ps
CPU time 21.76 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:43:20 PM PST 24
Peak memory 216208 kb
Host smart-db4e0f77-03df-4cb5-88f5-44f6392266a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319848983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2319848983
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2650078331
Short name T984
Test name
Test status
Simulation time 8779445909 ps
CPU time 51.62 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:45:35 PM PST 24
Peak memory 215748 kb
Host smart-44dfef1b-e0a4-46a8-85c3-9a5a66dfbf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650078331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2650078331
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2403181245
Short name T1831
Test name
Test status
Simulation time 5409723192 ps
CPU time 19.06 seconds
Started Mar 07 02:44:45 PM PST 24
Finished Mar 07 02:45:05 PM PST 24
Peak memory 215772 kb
Host smart-d118e89c-510f-460d-9204-266df7c025cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403181245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2403181245
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4121089582
Short name T1339
Test name
Test status
Simulation time 4316850278 ps
CPU time 6.74 seconds
Started Mar 07 12:42:44 PM PST 24
Finished Mar 07 12:42:51 PM PST 24
Peak memory 216228 kb
Host smart-6e4606ff-91ea-46a1-ad76-ed7c8a34c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121089582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4121089582
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2321002585
Short name T965
Test name
Test status
Simulation time 301842538 ps
CPU time 2.86 seconds
Started Mar 07 12:42:44 PM PST 24
Finished Mar 07 12:42:47 PM PST 24
Peak memory 217376 kb
Host smart-50988e33-7498-4ada-ae09-e43673565335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321002585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2321002585
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3881079493
Short name T1773
Test name
Test status
Simulation time 192521364 ps
CPU time 1.11 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:44:45 PM PST 24
Peak memory 206000 kb
Host smart-f9e14884-578c-4a0d-9c07-216c2007710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881079493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3881079493
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1661561115
Short name T1561
Test name
Test status
Simulation time 139598883 ps
CPU time 0.9 seconds
Started Mar 07 02:44:47 PM PST 24
Finished Mar 07 02:44:48 PM PST 24
Peak memory 205876 kb
Host smart-15a96093-27e2-46be-b7d7-1c60c3a79bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661561115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1661561115
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.274539528
Short name T978
Test name
Test status
Simulation time 238981531 ps
CPU time 0.89 seconds
Started Mar 07 12:42:44 PM PST 24
Finished Mar 07 12:42:45 PM PST 24
Peak memory 205464 kb
Host smart-7fd9a20c-2069-4df6-9c08-f079905d7657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274539528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.274539528
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.243148274
Short name T521
Test name
Test status
Simulation time 3425078354 ps
CPU time 6 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:42:51 PM PST 24
Peak memory 234260 kb
Host smart-97409d9c-2d83-4a8b-ba25-a454424f1e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243148274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.243148274
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_upload.400552540
Short name T563
Test name
Test status
Simulation time 694609096 ps
CPU time 5.38 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:44:49 PM PST 24
Peak memory 232948 kb
Host smart-13d138d1-c2b7-48bb-9faa-bd37349264b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400552540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.400552540
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2645712061
Short name T1207
Test name
Test status
Simulation time 16991729 ps
CPU time 0.75 seconds
Started Mar 07 12:42:48 PM PST 24
Finished Mar 07 12:42:49 PM PST 24
Peak memory 204596 kb
Host smart-b719513b-84b9-4b6f-9688-fdf88e3d5d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645712061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2645712061
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3202185548
Short name T817
Test name
Test status
Simulation time 22131755 ps
CPU time 0.71 seconds
Started Mar 07 02:44:51 PM PST 24
Finished Mar 07 02:44:52 PM PST 24
Peak memory 203792 kb
Host smart-8b4cea3e-2369-4ce1-b6b6-72cbb356fb5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202185548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3202185548
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.324216016
Short name T1229
Test name
Test status
Simulation time 127146300 ps
CPU time 2.34 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:42:47 PM PST 24
Peak memory 224360 kb
Host smart-4f7fa8a8-d2aa-4980-b77c-c8579386243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324216016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.324216016
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.4002692561
Short name T1232
Test name
Test status
Simulation time 585578686 ps
CPU time 3.83 seconds
Started Mar 07 02:44:49 PM PST 24
Finished Mar 07 02:44:53 PM PST 24
Peak memory 235088 kb
Host smart-53e82f39-2584-4949-a020-9ed3cdab96bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002692561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4002692561
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1639970952
Short name T562
Test name
Test status
Simulation time 41332206 ps
CPU time 0.75 seconds
Started Mar 07 02:44:42 PM PST 24
Finished Mar 07 02:44:44 PM PST 24
Peak memory 204824 kb
Host smart-e0a8efe9-0d61-4365-8086-1f598c4b145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639970952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1639970952
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1832061550
Short name T1353
Test name
Test status
Simulation time 20120678 ps
CPU time 0.75 seconds
Started Mar 07 12:42:44 PM PST 24
Finished Mar 07 12:42:45 PM PST 24
Peak memory 206588 kb
Host smart-2efeb075-e393-4023-9cba-01ac51281687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832061550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1832061550
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2291762457
Short name T1584
Test name
Test status
Simulation time 27706233466 ps
CPU time 130.3 seconds
Started Mar 07 12:42:47 PM PST 24
Finished Mar 07 12:44:58 PM PST 24
Peak memory 265140 kb
Host smart-a6980559-c7f9-4e6f-8a89-a430c94aab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291762457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2291762457
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.872305812
Short name T1002
Test name
Test status
Simulation time 22301845124 ps
CPU time 90.14 seconds
Started Mar 07 02:44:49 PM PST 24
Finished Mar 07 02:46:19 PM PST 24
Peak memory 251184 kb
Host smart-83234d52-3f31-4345-8a29-7732a8e1d787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872305812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.872305812
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2178636821
Short name T1861
Test name
Test status
Simulation time 45037521216 ps
CPU time 162.04 seconds
Started Mar 07 12:42:46 PM PST 24
Finished Mar 07 12:45:28 PM PST 24
Peak memory 263324 kb
Host smart-f554a2da-6676-4591-a362-17f165908ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178636821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2178636821
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2949705020
Short name T1047
Test name
Test status
Simulation time 69879347690 ps
CPU time 406.1 seconds
Started Mar 07 02:44:51 PM PST 24
Finished Mar 07 02:51:37 PM PST 24
Peak memory 267300 kb
Host smart-d4dc55ce-e3bb-4300-bfea-932f8fc6b35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949705020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2949705020
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.10939115
Short name T602
Test name
Test status
Simulation time 57233475532 ps
CPU time 190.32 seconds
Started Mar 07 12:42:46 PM PST 24
Finished Mar 07 12:45:56 PM PST 24
Peak memory 240956 kb
Host smart-eff4c7eb-253c-41aa-8c95-b1c4068dc512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10939115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.10939115
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1232541985
Short name T897
Test name
Test status
Simulation time 154907048833 ps
CPU time 154.69 seconds
Started Mar 07 02:44:51 PM PST 24
Finished Mar 07 02:47:26 PM PST 24
Peak memory 264472 kb
Host smart-0e9541b4-6d98-4c17-9d76-07ff0627aa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232541985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1232541985
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2054678956
Short name T912
Test name
Test status
Simulation time 3832805665 ps
CPU time 12.49 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:43:10 PM PST 24
Peak memory 234972 kb
Host smart-de2a6666-b932-4771-914e-7a6e15f6890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054678956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2054678956
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3829700769
Short name T985
Test name
Test status
Simulation time 2920150602 ps
CPU time 18.19 seconds
Started Mar 07 02:44:51 PM PST 24
Finished Mar 07 02:45:10 PM PST 24
Peak memory 239916 kb
Host smart-9fd80910-63ee-4099-9a4c-1b5b17fc3a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829700769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3829700769
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1336564414
Short name T221
Test name
Test status
Simulation time 11859596991 ps
CPU time 10.51 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:43:01 PM PST 24
Peak memory 233292 kb
Host smart-2360a1bd-e4a7-4785-8b64-729e57bb24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336564414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1336564414
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3498041030
Short name T671
Test name
Test status
Simulation time 4104381380 ps
CPU time 3.69 seconds
Started Mar 07 02:44:53 PM PST 24
Finished Mar 07 02:44:56 PM PST 24
Peak memory 223916 kb
Host smart-2685c129-4745-4b02-b682-8126cb12f775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498041030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3498041030
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2532479680
Short name T1484
Test name
Test status
Simulation time 4132375574 ps
CPU time 4.31 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:42:54 PM PST 24
Peak memory 233652 kb
Host smart-f040e42d-2d0f-412c-9e0b-b1243b138f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532479680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2532479680
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3387048560
Short name T434
Test name
Test status
Simulation time 22766726055 ps
CPU time 12.26 seconds
Started Mar 07 02:44:52 PM PST 24
Finished Mar 07 02:45:04 PM PST 24
Peak memory 223884 kb
Host smart-367c5e67-dc1a-4e23-835b-85ba985478f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387048560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3387048560
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2066401039
Short name T1072
Test name
Test status
Simulation time 393013200 ps
CPU time 5.54 seconds
Started Mar 07 12:42:44 PM PST 24
Finished Mar 07 12:42:50 PM PST 24
Peak memory 224548 kb
Host smart-6dc77e3f-4427-4d57-8ce8-34d358dd22a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066401039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2066401039
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.46478700
Short name T191
Test name
Test status
Simulation time 2431462966 ps
CPU time 6.66 seconds
Started Mar 07 02:44:50 PM PST 24
Finished Mar 07 02:44:57 PM PST 24
Peak memory 226596 kb
Host smart-7a7ac3f4-d568-4f76-b3b0-549f7f4dabcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46478700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.46478700
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1277031632
Short name T835
Test name
Test status
Simulation time 815881559 ps
CPU time 3.77 seconds
Started Mar 07 02:44:50 PM PST 24
Finished Mar 07 02:44:54 PM PST 24
Peak memory 216636 kb
Host smart-ddbfd33e-1874-455a-b903-3fec7fdbe9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277031632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1277031632
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1512581401
Short name T948
Test name
Test status
Simulation time 454985063 ps
CPU time 4.38 seconds
Started Mar 07 12:42:48 PM PST 24
Finished Mar 07 12:42:53 PM PST 24
Peak memory 224384 kb
Host smart-a6ae3fc7-d6ab-42a6-a80d-be60c394a3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512581401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1512581401
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3331395455
Short name T723
Test name
Test status
Simulation time 515437675 ps
CPU time 3.59 seconds
Started Mar 07 02:44:51 PM PST 24
Finished Mar 07 02:44:55 PM PST 24
Peak memory 219788 kb
Host smart-23149148-902c-4a99-a140-7deeb0bbd02c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3331395455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3331395455
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.644688284
Short name T1582
Test name
Test status
Simulation time 700048808 ps
CPU time 5.01 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:42:50 PM PST 24
Peak memory 222668 kb
Host smart-a8dbf7ba-e87d-42b6-98da-9f50e9199bc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=644688284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.644688284
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2460038357
Short name T1597
Test name
Test status
Simulation time 142511675951 ps
CPU time 447.16 seconds
Started Mar 07 02:44:52 PM PST 24
Finished Mar 07 02:52:20 PM PST 24
Peak memory 268504 kb
Host smart-f0f626bc-03a3-4576-bd11-985edd3c2068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460038357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2460038357
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.405166388
Short name T1401
Test name
Test status
Simulation time 63618739037 ps
CPU time 429.35 seconds
Started Mar 07 12:42:47 PM PST 24
Finished Mar 07 12:49:57 PM PST 24
Peak memory 257248 kb
Host smart-564a5f71-1638-4b1d-87ac-52b5c6fd5dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405166388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.405166388
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1200836076
Short name T1692
Test name
Test status
Simulation time 3589915131 ps
CPU time 6.3 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:44:50 PM PST 24
Peak memory 215916 kb
Host smart-c3a17ebb-e713-4593-a90a-9239035de1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200836076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1200836076
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.915267525
Short name T572
Test name
Test status
Simulation time 4758989154 ps
CPU time 21.43 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:43:06 PM PST 24
Peak memory 216272 kb
Host smart-6c8f0d52-9ac9-41a6-ad4b-af954021b283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915267525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.915267525
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.222187132
Short name T413
Test name
Test status
Simulation time 3227319700 ps
CPU time 5.4 seconds
Started Mar 07 02:44:42 PM PST 24
Finished Mar 07 02:44:49 PM PST 24
Peak memory 215732 kb
Host smart-1ce3c017-bda3-4f37-a7bc-b14ce5e75b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222187132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.222187132
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2700507904
Short name T1715
Test name
Test status
Simulation time 3100189485 ps
CPU time 9.26 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:42:54 PM PST 24
Peak memory 216116 kb
Host smart-2a4c2fda-3cce-4d6e-8c33-03e1df732579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700507904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2700507904
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2370608556
Short name T593
Test name
Test status
Simulation time 744856834 ps
CPU time 3.26 seconds
Started Mar 07 02:44:43 PM PST 24
Finished Mar 07 02:44:47 PM PST 24
Peak memory 215800 kb
Host smart-401db748-73d9-42fc-b880-01a1cefb6363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370608556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2370608556
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.998970153
Short name T348
Test name
Test status
Simulation time 34463619 ps
CPU time 0.93 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:42:47 PM PST 24
Peak memory 205724 kb
Host smart-40562b03-4405-473f-9883-c39f8d2169d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998970153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.998970153
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3347654772
Short name T1358
Test name
Test status
Simulation time 151221142 ps
CPU time 0.81 seconds
Started Mar 07 02:44:45 PM PST 24
Finished Mar 07 02:44:46 PM PST 24
Peak memory 204860 kb
Host smart-bf621bfe-447c-4e01-a263-f0dde61ebce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347654772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3347654772
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.486550705
Short name T1400
Test name
Test status
Simulation time 321002787 ps
CPU time 0.78 seconds
Started Mar 07 12:42:43 PM PST 24
Finished Mar 07 12:42:44 PM PST 24
Peak memory 205380 kb
Host smart-cdf8ca6f-83d7-4a6f-b9df-fbb3135a9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486550705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.486550705
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2496039123
Short name T245
Test name
Test status
Simulation time 950857161 ps
CPU time 4.42 seconds
Started Mar 07 12:42:48 PM PST 24
Finished Mar 07 12:42:53 PM PST 24
Peak memory 233860 kb
Host smart-9cea4fb0-84b3-4f46-8951-fe8971ae772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496039123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2496039123
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_upload.3934551366
Short name T765
Test name
Test status
Simulation time 4692761116 ps
CPU time 12.12 seconds
Started Mar 07 02:44:52 PM PST 24
Finished Mar 07 02:45:05 PM PST 24
Peak memory 217756 kb
Host smart-899cfb5f-fce7-4b41-8c95-c77f6c93d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934551366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3934551366
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1133421097
Short name T1090
Test name
Test status
Simulation time 34341542 ps
CPU time 0.71 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:01 PM PST 24
Peak memory 203816 kb
Host smart-0439ac67-3be7-4343-95b8-6bf7492271f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133421097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1133421097
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.693299874
Short name T527
Test name
Test status
Simulation time 36560663 ps
CPU time 0.71 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:42:51 PM PST 24
Peak memory 204472 kb
Host smart-6829ded4-12be-4165-9009-924d1a798d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693299874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.693299874
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2465013137
Short name T647
Test name
Test status
Simulation time 1839946422 ps
CPU time 4.89 seconds
Started Mar 07 02:45:01 PM PST 24
Finished Mar 07 02:45:07 PM PST 24
Peak memory 218216 kb
Host smart-132a9f91-e75a-4f66-91ee-1ace55faf747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465013137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2465013137
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3128067377
Short name T236
Test name
Test status
Simulation time 6825587796 ps
CPU time 5.64 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:42:56 PM PST 24
Peak memory 224520 kb
Host smart-a386ff91-8f98-41b5-b3ee-1372ce4058f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128067377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3128067377
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1146097729
Short name T1866
Test name
Test status
Simulation time 18584561 ps
CPU time 0.82 seconds
Started Mar 07 02:44:50 PM PST 24
Finished Mar 07 02:44:51 PM PST 24
Peak memory 204828 kb
Host smart-8e6b8b17-0ff8-4808-b321-e33914d4133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146097729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1146097729
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.659391945
Short name T1297
Test name
Test status
Simulation time 18604408 ps
CPU time 0.83 seconds
Started Mar 07 12:42:45 PM PST 24
Finished Mar 07 12:42:46 PM PST 24
Peak memory 206220 kb
Host smart-541a8e50-1e2d-4542-97e8-86a9ac0ac70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659391945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.659391945
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2130753905
Short name T1261
Test name
Test status
Simulation time 56114929756 ps
CPU time 77.56 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:44:08 PM PST 24
Peak memory 240760 kb
Host smart-1aa896f8-25ba-4d65-b9a9-a0b4d58a790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130753905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2130753905
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2587534109
Short name T1422
Test name
Test status
Simulation time 15136101281 ps
CPU time 51.32 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:52 PM PST 24
Peak memory 250136 kb
Host smart-7ed35eaf-effe-4304-8a8a-dd1301f39a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587534109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2587534109
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.405050226
Short name T192
Test name
Test status
Simulation time 42862728012 ps
CPU time 151.96 seconds
Started Mar 07 12:42:46 PM PST 24
Finished Mar 07 12:45:18 PM PST 24
Peak memory 257412 kb
Host smart-9f97bda1-6b36-4a91-9f93-59bb93f3ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405050226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.405050226
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.681575769
Short name T510
Test name
Test status
Simulation time 13695366212 ps
CPU time 89.29 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:46:30 PM PST 24
Peak memory 254288 kb
Host smart-85e70ca5-3fe4-4891-81ef-2233619cec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681575769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.681575769
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1895123727
Short name T1572
Test name
Test status
Simulation time 3160118318 ps
CPU time 61.62 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 249148 kb
Host smart-e2b0fe8a-b7b9-4e0f-a43a-9054a68b9354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895123727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1895123727
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.379410162
Short name T761
Test name
Test status
Simulation time 40998253570 ps
CPU time 127.6 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:47:09 PM PST 24
Peak memory 248716 kb
Host smart-529bbbbe-ce59-4ed3-b7a7-2d6ec5f21a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379410162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.379410162
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4126343948
Short name T899
Test name
Test status
Simulation time 15418349373 ps
CPU time 23.28 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:43:13 PM PST 24
Peak memory 223664 kb
Host smart-cf5679f9-8cff-4d06-9b93-d7c2c6864944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126343948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4126343948
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.632985258
Short name T1880
Test name
Test status
Simulation time 1447458657 ps
CPU time 13.66 seconds
Started Mar 07 02:44:58 PM PST 24
Finished Mar 07 02:45:13 PM PST 24
Peak memory 240128 kb
Host smart-4849d167-22ee-4778-83fb-d19082fbdd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632985258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.632985258
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1622201295
Short name T1586
Test name
Test status
Simulation time 2457213057 ps
CPU time 5.02 seconds
Started Mar 07 02:44:49 PM PST 24
Finished Mar 07 02:44:54 PM PST 24
Peak memory 233748 kb
Host smart-cc4d8765-16ac-4af7-9962-c2a14c9c302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622201295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1622201295
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3033059877
Short name T1890
Test name
Test status
Simulation time 565689276 ps
CPU time 5.06 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:43:03 PM PST 24
Peak memory 237480 kb
Host smart-d1818b6a-ccaf-41b5-95d2-0c5a3c57b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033059877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3033059877
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2373437385
Short name T1402
Test name
Test status
Simulation time 32212900190 ps
CPU time 22.91 seconds
Started Mar 07 02:45:01 PM PST 24
Finished Mar 07 02:45:25 PM PST 24
Peak memory 233092 kb
Host smart-8941ee59-6395-441f-a4c4-ca09d6b7eabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373437385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2373437385
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3882065154
Short name T589
Test name
Test status
Simulation time 3367463982 ps
CPU time 10.72 seconds
Started Mar 07 12:42:48 PM PST 24
Finished Mar 07 12:42:59 PM PST 24
Peak memory 232488 kb
Host smart-947597aa-337e-4bd3-b64f-629c708cf8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882065154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3882065154
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3548611681
Short name T1516
Test name
Test status
Simulation time 10827135377 ps
CPU time 28.63 seconds
Started Mar 07 02:44:52 PM PST 24
Finished Mar 07 02:45:20 PM PST 24
Peak memory 216376 kb
Host smart-85783dd4-566e-49dc-8c2c-f9d1b26b53f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548611681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3548611681
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.529291994
Short name T1531
Test name
Test status
Simulation time 1172568865 ps
CPU time 7.13 seconds
Started Mar 07 12:42:49 PM PST 24
Finished Mar 07 12:42:56 PM PST 24
Peak memory 240792 kb
Host smart-655a62c4-22bb-42dc-b889-bf5634d50b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529291994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.529291994
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1519454701
Short name T165
Test name
Test status
Simulation time 81575664658 ps
CPU time 37.69 seconds
Started Mar 07 02:44:51 PM PST 24
Finished Mar 07 02:45:30 PM PST 24
Peak memory 239424 kb
Host smart-a758c4e5-79e1-4981-a03e-86321fc96089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519454701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1519454701
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1783758830
Short name T979
Test name
Test status
Simulation time 135645398 ps
CPU time 2.81 seconds
Started Mar 07 12:42:46 PM PST 24
Finished Mar 07 12:42:49 PM PST 24
Peak memory 232636 kb
Host smart-8ee2aa85-4e61-4f19-9a79-54813690f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783758830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1783758830
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1679775058
Short name T1807
Test name
Test status
Simulation time 5988448701 ps
CPU time 4.34 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:42:54 PM PST 24
Peak memory 222572 kb
Host smart-11b9deb5-7ea0-4679-baad-828bc25aac86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1679775058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1679775058
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3430267969
Short name T615
Test name
Test status
Simulation time 1187240351 ps
CPU time 4.49 seconds
Started Mar 07 02:45:01 PM PST 24
Finished Mar 07 02:45:06 PM PST 24
Peak memory 215748 kb
Host smart-df9d05c0-f5b6-46ae-a9bd-3083547a5b3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430267969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3430267969
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3824105255
Short name T1237
Test name
Test status
Simulation time 22208615504 ps
CPU time 48.5 seconds
Started Mar 07 02:45:05 PM PST 24
Finished Mar 07 02:45:53 PM PST 24
Peak memory 239144 kb
Host smart-ec48394a-c608-4257-b5a1-baea15d5857b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824105255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3824105255
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.716573731
Short name T158
Test name
Test status
Simulation time 103674408655 ps
CPU time 298.85 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:47:57 PM PST 24
Peak memory 251292 kb
Host smart-4efac311-f84e-4110-8359-9bd00454bcc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716573731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.716573731
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2147564803
Short name T1032
Test name
Test status
Simulation time 16032506988 ps
CPU time 44.42 seconds
Started Mar 07 02:44:53 PM PST 24
Finished Mar 07 02:45:39 PM PST 24
Peak memory 215728 kb
Host smart-83624256-dd27-4a4f-86e1-1ced531861be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147564803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2147564803
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.287837351
Short name T1139
Test name
Test status
Simulation time 2876571000 ps
CPU time 21.36 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:43:11 PM PST 24
Peak memory 218432 kb
Host smart-3d882aa9-ef99-4812-8995-9201c94f0c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287837351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.287837351
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.395517142
Short name T1435
Test name
Test status
Simulation time 9082720322 ps
CPU time 23.66 seconds
Started Mar 07 02:44:51 PM PST 24
Finished Mar 07 02:45:15 PM PST 24
Peak memory 215756 kb
Host smart-1017d41d-1d25-4ef4-9be5-8e7c5a5bca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395517142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.395517142
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4287197900
Short name T1219
Test name
Test status
Simulation time 41214246383 ps
CPU time 16.37 seconds
Started Mar 07 12:42:44 PM PST 24
Finished Mar 07 12:43:01 PM PST 24
Peak memory 216188 kb
Host smart-846e54b4-d115-41d6-ad03-ea071bdda95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287197900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4287197900
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.791663048
Short name T564
Test name
Test status
Simulation time 40726463 ps
CPU time 1.18 seconds
Started Mar 07 02:44:57 PM PST 24
Finished Mar 07 02:44:59 PM PST 24
Peak memory 207436 kb
Host smart-3d97204c-626f-4659-8b2d-7c6b8d5aa62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791663048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.791663048
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.935938629
Short name T771
Test name
Test status
Simulation time 580450250 ps
CPU time 9.54 seconds
Started Mar 07 12:42:56 PM PST 24
Finished Mar 07 12:43:06 PM PST 24
Peak memory 216304 kb
Host smart-62dbb3e1-cdb0-47f9-bcbb-d606d0122262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935938629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.935938629
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1497105487
Short name T742
Test name
Test status
Simulation time 151819439 ps
CPU time 0.93 seconds
Started Mar 07 02:44:49 PM PST 24
Finished Mar 07 02:44:50 PM PST 24
Peak memory 205976 kb
Host smart-9501d1c0-c308-457a-9759-7cafed63a406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497105487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1497105487
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2628543855
Short name T1722
Test name
Test status
Simulation time 307233621 ps
CPU time 0.99 seconds
Started Mar 07 12:42:49 PM PST 24
Finished Mar 07 12:42:50 PM PST 24
Peak memory 206524 kb
Host smart-09649b33-14a3-48d5-9d95-249e7538faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628543855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2628543855
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3148232471
Short name T1895
Test name
Test status
Simulation time 182365701 ps
CPU time 3.84 seconds
Started Mar 07 12:42:56 PM PST 24
Finished Mar 07 12:43:00 PM PST 24
Peak memory 233336 kb
Host smart-8af1135b-27fb-4627-b0b8-b6bcf459b92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148232471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3148232471
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_upload.639667246
Short name T1250
Test name
Test status
Simulation time 1509947113 ps
CPU time 5.47 seconds
Started Mar 07 02:45:05 PM PST 24
Finished Mar 07 02:45:10 PM PST 24
Peak memory 217936 kb
Host smart-84308334-1d21-4119-9ee3-87462f354bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639667246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.639667246
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2863675251
Short name T1502
Test name
Test status
Simulation time 24479126 ps
CPU time 0.77 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:42:59 PM PST 24
Peak memory 204632 kb
Host smart-8f94b3a3-5df8-4d3d-b1c1-dbc770a5e8c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863675251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2863675251
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3543881495
Short name T1780
Test name
Test status
Simulation time 18909444 ps
CPU time 0.69 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:02 PM PST 24
Peak memory 204688 kb
Host smart-d23ae08b-19a5-4a6d-967b-644baf486b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543881495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3543881495
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.353310027
Short name T778
Test name
Test status
Simulation time 203248126 ps
CPU time 3.54 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:05 PM PST 24
Peak memory 232956 kb
Host smart-5e3e87b5-30c8-4897-9669-f19df3c67b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353310027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.353310027
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4143999712
Short name T496
Test name
Test status
Simulation time 7744124248 ps
CPU time 7.09 seconds
Started Mar 07 12:43:01 PM PST 24
Finished Mar 07 12:43:09 PM PST 24
Peak memory 234080 kb
Host smart-0a1b2a15-1f62-4ee3-9298-e7bfeeb20451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143999712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4143999712
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1450968803
Short name T1129
Test name
Test status
Simulation time 38372770 ps
CPU time 0.77 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:42:58 PM PST 24
Peak memory 206232 kb
Host smart-336d48a2-68a0-4fe9-9feb-eb8c4a8ec81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450968803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1450968803
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3506416456
Short name T363
Test name
Test status
Simulation time 17884016 ps
CPU time 0.75 seconds
Started Mar 07 02:44:58 PM PST 24
Finished Mar 07 02:45:00 PM PST 24
Peak memory 204472 kb
Host smart-cb331447-2d45-4136-98ef-1ecfaf7d62f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506416456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3506416456
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1463076084
Short name T28
Test name
Test status
Simulation time 57406619332 ps
CPU time 303.37 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:50:04 PM PST 24
Peak memory 263988 kb
Host smart-19dbbee7-5ad6-42f4-8969-1edf965a215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463076084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1463076084
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2621751558
Short name T1384
Test name
Test status
Simulation time 11809820961 ps
CPU time 22.04 seconds
Started Mar 07 12:43:04 PM PST 24
Finished Mar 07 12:43:26 PM PST 24
Peak memory 240808 kb
Host smart-9a2b9af7-0109-41b9-aaa8-e05daac8ca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621751558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2621751558
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.198097335
Short name T47
Test name
Test status
Simulation time 151550035012 ps
CPU time 217.91 seconds
Started Mar 07 02:44:59 PM PST 24
Finished Mar 07 02:48:38 PM PST 24
Peak memory 256404 kb
Host smart-ee79ed05-c5e4-49ed-b527-89ecea99e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198097335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.198097335
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3140120566
Short name T1501
Test name
Test status
Simulation time 37674722149 ps
CPU time 213.73 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:46:31 PM PST 24
Peak memory 251184 kb
Host smart-a49b8970-3ef1-41ef-8d59-8435be75b19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140120566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3140120566
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.125152138
Short name T1288
Test name
Test status
Simulation time 20711373759 ps
CPU time 75.19 seconds
Started Mar 07 02:44:59 PM PST 24
Finished Mar 07 02:46:15 PM PST 24
Peak memory 233316 kb
Host smart-d7cee053-fe78-4319-901e-b29401dfc702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125152138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.125152138
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2081651446
Short name T1285
Test name
Test status
Simulation time 92241401637 ps
CPU time 463.03 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:50:41 PM PST 24
Peak memory 270544 kb
Host smart-e197f6d0-83f7-4376-865f-d4099c2e57d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081651446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2081651446
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1984454143
Short name T419
Test name
Test status
Simulation time 2773280716 ps
CPU time 10.13 seconds
Started Mar 07 02:45:04 PM PST 24
Finished Mar 07 02:45:14 PM PST 24
Peak memory 235628 kb
Host smart-194e2711-bd0c-4533-817c-4b7c679f5362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984454143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1984454143
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4062744013
Short name T1013
Test name
Test status
Simulation time 5391026531 ps
CPU time 31.85 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 241000 kb
Host smart-5fa258e8-1d57-4857-9052-9432b83a65fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062744013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4062744013
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1909962589
Short name T1216
Test name
Test status
Simulation time 1242838868 ps
CPU time 5.11 seconds
Started Mar 07 02:44:59 PM PST 24
Finished Mar 07 02:45:05 PM PST 24
Peak memory 232840 kb
Host smart-18e8f158-866c-4860-b121-be8f74146c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909962589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1909962589
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3625224850
Short name T577
Test name
Test status
Simulation time 307335829 ps
CPU time 3.78 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:43:01 PM PST 24
Peak memory 233236 kb
Host smart-31894480-ffa5-420e-8bf7-4d89e91d5274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625224850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3625224850
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1522103388
Short name T588
Test name
Test status
Simulation time 704420461 ps
CPU time 3.33 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:43:02 PM PST 24
Peak memory 224364 kb
Host smart-8c928780-b04b-43fc-8271-df1704c91e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522103388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1522103388
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2131430704
Short name T1203
Test name
Test status
Simulation time 15213767373 ps
CPU time 10.3 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:11 PM PST 24
Peak memory 223864 kb
Host smart-56968873-43a5-4aa4-8617-856f118f4bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131430704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2131430704
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1138749540
Short name T1751
Test name
Test status
Simulation time 8765984035 ps
CPU time 7.68 seconds
Started Mar 07 02:45:05 PM PST 24
Finished Mar 07 02:45:13 PM PST 24
Peak memory 232348 kb
Host smart-1e060716-519b-4bed-9860-10a36b0eed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138749540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1138749540
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1824759861
Short name T1097
Test name
Test status
Simulation time 13723910672 ps
CPU time 31.25 seconds
Started Mar 07 12:43:00 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 228004 kb
Host smart-5c80e5c0-ad2f-4f43-855b-b1e1414b8549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824759861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1824759861
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1198775182
Short name T1849
Test name
Test status
Simulation time 541915896 ps
CPU time 2.75 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:03 PM PST 24
Peak memory 232096 kb
Host smart-d9051232-ccad-4957-aab6-dd1610354b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198775182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1198775182
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1827987670
Short name T812
Test name
Test status
Simulation time 74509036 ps
CPU time 2.15 seconds
Started Mar 07 12:42:59 PM PST 24
Finished Mar 07 12:43:01 PM PST 24
Peak memory 216676 kb
Host smart-4f69bd42-a0f4-45f9-ae11-59c8ce709f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827987670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1827987670
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1838963335
Short name T1525
Test name
Test status
Simulation time 2381516799 ps
CPU time 6.53 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:08 PM PST 24
Peak memory 221980 kb
Host smart-1f4a24ec-5418-4870-89f3-81388e08ae55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1838963335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1838963335
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2558333129
Short name T1444
Test name
Test status
Simulation time 4154516670 ps
CPU time 5.66 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:43:03 PM PST 24
Peak memory 219084 kb
Host smart-a2096439-0f91-4995-9ef0-99aede6fa4d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2558333129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2558333129
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2283602855
Short name T1389
Test name
Test status
Simulation time 7293808256 ps
CPU time 46.67 seconds
Started Mar 07 02:44:59 PM PST 24
Finished Mar 07 02:45:46 PM PST 24
Peak memory 248608 kb
Host smart-df1e1256-cb53-42b3-a9d5-cae31a131c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283602855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2283602855
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2337920437
Short name T1766
Test name
Test status
Simulation time 26884305552 ps
CPU time 98.83 seconds
Started Mar 07 12:42:59 PM PST 24
Finished Mar 07 12:44:38 PM PST 24
Peak memory 256832 kb
Host smart-5ae44864-88b6-4ceb-b14c-8f80c6307af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337920437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2337920437
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1578710392
Short name T1337
Test name
Test status
Simulation time 1167863096 ps
CPU time 6.58 seconds
Started Mar 07 12:42:47 PM PST 24
Finished Mar 07 12:42:54 PM PST 24
Peak memory 216164 kb
Host smart-9e6a7c87-6d35-4316-bea0-74c59000ac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578710392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1578710392
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1847887696
Short name T872
Test name
Test status
Simulation time 15376186760 ps
CPU time 70.87 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:46:11 PM PST 24
Peak memory 215832 kb
Host smart-2ed40871-d357-4f4b-8e92-8617ccdb140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847887696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1847887696
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1136253842
Short name T722
Test name
Test status
Simulation time 5840781316 ps
CPU time 12.22 seconds
Started Mar 07 12:42:50 PM PST 24
Finished Mar 07 12:43:02 PM PST 24
Peak memory 216216 kb
Host smart-c434b59c-d62b-4ad4-b3af-3f09ef171231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136253842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1136253842
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3685987181
Short name T423
Test name
Test status
Simulation time 10828447160 ps
CPU time 18.65 seconds
Started Mar 07 02:45:02 PM PST 24
Finished Mar 07 02:45:20 PM PST 24
Peak memory 215812 kb
Host smart-0eeaceff-eecd-4f10-ace3-10eaca36b90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685987181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3685987181
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1445480969
Short name T336
Test name
Test status
Simulation time 196234243 ps
CPU time 1.33 seconds
Started Mar 07 12:42:56 PM PST 24
Finished Mar 07 12:42:57 PM PST 24
Peak memory 216200 kb
Host smart-def016b3-eacf-48f2-a184-eec9c7e718ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445480969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1445480969
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2583389824
Short name T1494
Test name
Test status
Simulation time 248431060 ps
CPU time 1.66 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:02 PM PST 24
Peak memory 215772 kb
Host smart-17fd5d32-f1fe-433c-b6d9-4d0459d86a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583389824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2583389824
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3407332154
Short name T356
Test name
Test status
Simulation time 178397683 ps
CPU time 0.82 seconds
Started Mar 07 02:44:58 PM PST 24
Finished Mar 07 02:44:59 PM PST 24
Peak memory 204924 kb
Host smart-ea6adab4-143d-4c59-aef9-4cadbc3a6463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407332154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3407332154
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.960329485
Short name T1632
Test name
Test status
Simulation time 257278259 ps
CPU time 0.95 seconds
Started Mar 07 12:42:46 PM PST 24
Finished Mar 07 12:42:47 PM PST 24
Peak memory 206496 kb
Host smart-9014330a-773c-4602-bd51-3047a2d10165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960329485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.960329485
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2066197962
Short name T1700
Test name
Test status
Simulation time 527803085 ps
CPU time 2.51 seconds
Started Mar 07 12:42:56 PM PST 24
Finished Mar 07 12:42:59 PM PST 24
Peak memory 216316 kb
Host smart-6088a491-d3de-46da-adca-831b501869df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066197962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2066197962
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_upload.4129781847
Short name T1065
Test name
Test status
Simulation time 7547143328 ps
CPU time 22.87 seconds
Started Mar 07 02:44:58 PM PST 24
Finished Mar 07 02:45:21 PM PST 24
Peak memory 232384 kb
Host smart-26be903b-d41e-4ba2-9588-7935605cc963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129781847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4129781847
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.302853047
Short name T385
Test name
Test status
Simulation time 13235047 ps
CPU time 0.74 seconds
Started Mar 07 12:43:01 PM PST 24
Finished Mar 07 12:43:02 PM PST 24
Peak memory 205556 kb
Host smart-b05e56da-b1dc-4bf1-ad60-8f7c0acc94c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302853047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.302853047
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3588938432
Short name T355
Test name
Test status
Simulation time 39265286 ps
CPU time 0.8 seconds
Started Mar 07 02:45:12 PM PST 24
Finished Mar 07 02:45:13 PM PST 24
Peak memory 203844 kb
Host smart-b79a4fcb-8d1b-4d44-85ae-870dec377c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588938432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3588938432
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.752260144
Short name T1071
Test name
Test status
Simulation time 251619343 ps
CPU time 3.3 seconds
Started Mar 07 12:43:00 PM PST 24
Finished Mar 07 12:43:03 PM PST 24
Peak memory 233544 kb
Host smart-33fe499d-41aa-4571-bf3b-32179ced9f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752260144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.752260144
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.850388413
Short name T231
Test name
Test status
Simulation time 1676762070 ps
CPU time 8.02 seconds
Started Mar 07 02:45:05 PM PST 24
Finished Mar 07 02:45:13 PM PST 24
Peak memory 233128 kb
Host smart-be0901e0-7abf-417c-a369-bdeddc17d652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850388413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.850388413
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1508253826
Short name T1714
Test name
Test status
Simulation time 21133107 ps
CPU time 0.8 seconds
Started Mar 07 02:45:04 PM PST 24
Finished Mar 07 02:45:05 PM PST 24
Peak memory 205496 kb
Host smart-b4f025cc-1ed7-4b03-9262-603e286134c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508253826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1508253826
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.707640801
Short name T1462
Test name
Test status
Simulation time 54661076 ps
CPU time 0.71 seconds
Started Mar 07 12:43:05 PM PST 24
Finished Mar 07 12:43:06 PM PST 24
Peak memory 205228 kb
Host smart-dd71372f-9869-4040-802c-009cecd1152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707640801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.707640801
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1717699264
Short name T1490
Test name
Test status
Simulation time 56551327125 ps
CPU time 224.88 seconds
Started Mar 07 02:45:11 PM PST 24
Finished Mar 07 02:48:56 PM PST 24
Peak memory 256152 kb
Host smart-c7078540-13fe-4a02-9e61-715df4b14a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717699264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1717699264
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2243762473
Short name T1380
Test name
Test status
Simulation time 34720165765 ps
CPU time 181.4 seconds
Started Mar 07 12:43:00 PM PST 24
Finished Mar 07 12:46:02 PM PST 24
Peak memory 240896 kb
Host smart-8e35c06c-7e50-41e2-bdef-931bb5d6d63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243762473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2243762473
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2389809877
Short name T1225
Test name
Test status
Simulation time 150160564295 ps
CPU time 230.78 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:49:00 PM PST 24
Peak memory 272392 kb
Host smart-7dfca584-a8ae-4c29-952d-ec42edc11cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389809877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2389809877
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.797048167
Short name T168
Test name
Test status
Simulation time 10910406443 ps
CPU time 92.19 seconds
Started Mar 07 12:43:00 PM PST 24
Finished Mar 07 12:44:33 PM PST 24
Peak memory 267396 kb
Host smart-26d8f55d-d12a-4d03-a635-8e9ea4d35c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797048167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.797048167
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1335761030
Short name T1340
Test name
Test status
Simulation time 71017181791 ps
CPU time 179.53 seconds
Started Mar 07 12:42:59 PM PST 24
Finished Mar 07 12:45:58 PM PST 24
Peak memory 253600 kb
Host smart-28cb13ea-3bc4-410d-9fc9-d89d7a57b37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335761030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1335761030
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.871073074
Short name T189
Test name
Test status
Simulation time 183054559090 ps
CPU time 271.79 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:49:41 PM PST 24
Peak memory 256836 kb
Host smart-26fb786c-f697-422f-874a-8eacb33ddce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871073074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.871073074
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1191655252
Short name T804
Test name
Test status
Simulation time 8291560482 ps
CPU time 34.46 seconds
Started Mar 07 12:42:59 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 236032 kb
Host smart-d454462d-591b-43b9-b328-9a6e787ca09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191655252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1191655252
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1122701961
Short name T830
Test name
Test status
Simulation time 17282220949 ps
CPU time 14.71 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:43:13 PM PST 24
Peak memory 224448 kb
Host smart-c5022f92-b165-4937-b546-e8a8162dbbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122701961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1122701961
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intercept.197132991
Short name T85
Test name
Test status
Simulation time 211322572 ps
CPU time 5.1 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:45:14 PM PST 24
Peak memory 233104 kb
Host smart-d385df03-d753-4607-ad0e-653bdcd411b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197132991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.197132991
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1803875672
Short name T611
Test name
Test status
Simulation time 13334205870 ps
CPU time 14.44 seconds
Started Mar 07 12:43:01 PM PST 24
Finished Mar 07 12:43:15 PM PST 24
Peak memory 240876 kb
Host smart-66e32be1-4dde-430b-b252-b13ef66a0803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803875672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1803875672
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3530189214
Short name T672
Test name
Test status
Simulation time 10244898648 ps
CPU time 7.98 seconds
Started Mar 07 02:45:08 PM PST 24
Finished Mar 07 02:45:16 PM PST 24
Peak memory 232132 kb
Host smart-63580fe6-b002-4bed-8732-10769c7465f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530189214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3530189214
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1100349058
Short name T849
Test name
Test status
Simulation time 25521995563 ps
CPU time 28.6 seconds
Started Mar 07 02:45:06 PM PST 24
Finished Mar 07 02:45:35 PM PST 24
Peak memory 227564 kb
Host smart-ca7e2d40-986e-47ca-b310-2c11fd7f7d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100349058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1100349058
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.32164381
Short name T185
Test name
Test status
Simulation time 1227119658 ps
CPU time 6.81 seconds
Started Mar 07 12:42:59 PM PST 24
Finished Mar 07 12:43:06 PM PST 24
Peak memory 238152 kb
Host smart-3199a079-5650-45be-aa9e-a2679c5fdb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32164381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.32164381
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1144534983
Short name T1155
Test name
Test status
Simulation time 11028630002 ps
CPU time 32.96 seconds
Started Mar 07 12:43:00 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 236064 kb
Host smart-17e53e64-bc5f-47e7-a07f-e3122bc67559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144534983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1144534983
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.985298368
Short name T659
Test name
Test status
Simulation time 986718715 ps
CPU time 7.25 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:45:17 PM PST 24
Peak memory 235168 kb
Host smart-aa56263c-4256-4b62-a051-faa1a34a3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985298368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.985298368
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1792750861
Short name T1631
Test name
Test status
Simulation time 4849918152 ps
CPU time 5.33 seconds
Started Mar 07 12:42:59 PM PST 24
Finished Mar 07 12:43:04 PM PST 24
Peak memory 220380 kb
Host smart-6fe0f04d-46a3-44a3-81f5-20dd154485ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1792750861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1792750861
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.817114795
Short name T680
Test name
Test status
Simulation time 679514166 ps
CPU time 3.34 seconds
Started Mar 07 02:45:10 PM PST 24
Finished Mar 07 02:45:14 PM PST 24
Peak memory 215760 kb
Host smart-13bab92b-8b1f-4491-95b4-dd65af5a6184
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=817114795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.817114795
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1205048364
Short name T1568
Test name
Test status
Simulation time 42172342942 ps
CPU time 208.16 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:46:26 PM PST 24
Peak memory 256868 kb
Host smart-96292c0e-9447-4163-b244-1ed3a4e26b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205048364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1205048364
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2073685756
Short name T1085
Test name
Test status
Simulation time 110016450 ps
CPU time 1.07 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:45:10 PM PST 24
Peak memory 206176 kb
Host smart-b32d4179-c076-4be4-b6fa-d0cbbd50c406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073685756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2073685756
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1329028437
Short name T600
Test name
Test status
Simulation time 831095377 ps
CPU time 3.46 seconds
Started Mar 07 12:43:04 PM PST 24
Finished Mar 07 12:43:07 PM PST 24
Peak memory 216172 kb
Host smart-7a0294d9-dee9-4a3d-97ee-8f0cc8d4f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329028437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1329028437
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.982661560
Short name T1202
Test name
Test status
Simulation time 6719555075 ps
CPU time 20.63 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:45:30 PM PST 24
Peak memory 215820 kb
Host smart-337d48cf-75ca-447d-ae6b-4bdd47622b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982661560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.982661560
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2326164217
Short name T760
Test name
Test status
Simulation time 19152064243 ps
CPU time 17.95 seconds
Started Mar 07 12:43:01 PM PST 24
Finished Mar 07 12:43:19 PM PST 24
Peak memory 216196 kb
Host smart-886a87d5-445c-4ba3-8453-54cfd08dac21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326164217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2326164217
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3198590417
Short name T1370
Test name
Test status
Simulation time 492674699 ps
CPU time 3.88 seconds
Started Mar 07 02:45:00 PM PST 24
Finished Mar 07 02:45:05 PM PST 24
Peak memory 215796 kb
Host smart-bfd2d205-6284-4f50-b8d7-7827ae08de55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198590417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3198590417
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2172917190
Short name T842
Test name
Test status
Simulation time 36474942 ps
CPU time 1.23 seconds
Started Mar 07 12:42:56 PM PST 24
Finished Mar 07 12:42:57 PM PST 24
Peak memory 207612 kb
Host smart-f451919c-f71d-4b07-b71e-0b6d18ed3cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172917190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2172917190
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.831754896
Short name T1298
Test name
Test status
Simulation time 29595874 ps
CPU time 0.94 seconds
Started Mar 07 02:45:12 PM PST 24
Finished Mar 07 02:45:14 PM PST 24
Peak memory 205956 kb
Host smart-73c6c6b8-09b7-404b-aa50-73fd87d8dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831754896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.831754896
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2370140024
Short name T1852
Test name
Test status
Simulation time 288774186 ps
CPU time 1.02 seconds
Started Mar 07 12:43:01 PM PST 24
Finished Mar 07 12:43:02 PM PST 24
Peak memory 206416 kb
Host smart-1edea558-d896-4c00-8279-e3d398e62c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370140024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2370140024
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2572711052
Short name T876
Test name
Test status
Simulation time 124416779 ps
CPU time 0.78 seconds
Started Mar 07 02:45:07 PM PST 24
Finished Mar 07 02:45:09 PM PST 24
Peak memory 204812 kb
Host smart-6c78e0ee-8a61-420e-bd81-e847ed596e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572711052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2572711052
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2351438840
Short name T532
Test name
Test status
Simulation time 23491089177 ps
CPU time 14.88 seconds
Started Mar 07 12:43:04 PM PST 24
Finished Mar 07 12:43:19 PM PST 24
Peak memory 231316 kb
Host smart-4821793e-2dac-4ec5-bf09-cb39593a1d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351438840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2351438840
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_upload.584694029
Short name T1517
Test name
Test status
Simulation time 808185711 ps
CPU time 5.11 seconds
Started Mar 07 02:45:10 PM PST 24
Finished Mar 07 02:45:15 PM PST 24
Peak memory 220544 kb
Host smart-5a51c85f-d744-4fb2-bea0-8f8c0d03a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584694029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.584694029
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2884406916
Short name T737
Test name
Test status
Simulation time 33351224 ps
CPU time 0.7 seconds
Started Mar 07 02:45:12 PM PST 24
Finished Mar 07 02:45:13 PM PST 24
Peak memory 203840 kb
Host smart-ec3fe4ab-a4f2-48ed-b5ef-835b39cf44ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884406916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2884406916
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3199917591
Short name T379
Test name
Test status
Simulation time 23370722 ps
CPU time 0.74 seconds
Started Mar 07 12:43:07 PM PST 24
Finished Mar 07 12:43:08 PM PST 24
Peak memory 205136 kb
Host smart-e5e6a8ef-a050-4868-aec6-594d5c216652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199917591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3199917591
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2804337637
Short name T1563
Test name
Test status
Simulation time 30278122704 ps
CPU time 8.42 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:45:17 PM PST 24
Peak memory 219124 kb
Host smart-5f6c2f42-8503-415b-84de-9d516e834cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804337637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2804337637
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.748561727
Short name T1255
Test name
Test status
Simulation time 286396700 ps
CPU time 2.83 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:43:01 PM PST 24
Peak memory 236180 kb
Host smart-6eb655b4-14e4-4b4a-a266-9572952fe564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748561727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.748561727
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1141599307
Short name T549
Test name
Test status
Simulation time 221429051 ps
CPU time 0.76 seconds
Started Mar 07 02:45:07 PM PST 24
Finished Mar 07 02:45:09 PM PST 24
Peak memory 205512 kb
Host smart-67063366-369e-4403-8b42-4ff7161348a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141599307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1141599307
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3641524597
Short name T1399
Test name
Test status
Simulation time 14823538 ps
CPU time 0.79 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:42:59 PM PST 24
Peak memory 206360 kb
Host smart-d39a819d-e6b2-48fa-869f-3f8cc70c8b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641524597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3641524597
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2001616837
Short name T724
Test name
Test status
Simulation time 68927736529 ps
CPU time 86.29 seconds
Started Mar 07 12:43:06 PM PST 24
Finished Mar 07 12:44:33 PM PST 24
Peak memory 240860 kb
Host smart-7da02921-a7b9-44dc-81f5-dcb8881324a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001616837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2001616837
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.663763027
Short name T888
Test name
Test status
Simulation time 15379819946 ps
CPU time 90.43 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:44:39 PM PST 24
Peak memory 251256 kb
Host smart-5cb97678-def5-4501-9763-005352adb509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663763027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.663763027
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.724681981
Short name T1726
Test name
Test status
Simulation time 171298467574 ps
CPU time 315.53 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:50:24 PM PST 24
Peak memory 252580 kb
Host smart-2c16b332-3e1b-451e-aebc-af8397bdec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724681981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.724681981
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3190020633
Short name T1323
Test name
Test status
Simulation time 7506750497 ps
CPU time 79.49 seconds
Started Mar 07 02:45:04 PM PST 24
Finished Mar 07 02:46:24 PM PST 24
Peak memory 238120 kb
Host smart-50981cef-ad1b-48d2-8b25-ce20a0497b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190020633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3190020633
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3875869779
Short name T210
Test name
Test status
Simulation time 75914008847 ps
CPU time 117.33 seconds
Started Mar 07 12:43:06 PM PST 24
Finished Mar 07 12:45:03 PM PST 24
Peak memory 256104 kb
Host smart-b30b0013-7c2c-4524-b67c-619fae1538ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875869779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3875869779
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2129736689
Short name T1767
Test name
Test status
Simulation time 14818401409 ps
CPU time 39.6 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:45:49 PM PST 24
Peak memory 240380 kb
Host smart-4b101934-8f91-4fc7-ad38-bdbc10f17ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129736689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2129736689
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2598847944
Short name T990
Test name
Test status
Simulation time 19378404680 ps
CPU time 23.4 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:43:20 PM PST 24
Peak memory 251200 kb
Host smart-d38ffcb0-5d08-4dce-b309-e534cafd9e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598847944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2598847944
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1771017654
Short name T1130
Test name
Test status
Simulation time 669769815 ps
CPU time 5.81 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:43:04 PM PST 24
Peak memory 220036 kb
Host smart-2c005ef1-ac58-4477-834f-c174a07a33e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771017654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1771017654
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4219061416
Short name T504
Test name
Test status
Simulation time 2030252829 ps
CPU time 8.18 seconds
Started Mar 07 02:45:10 PM PST 24
Finished Mar 07 02:45:18 PM PST 24
Peak memory 223804 kb
Host smart-a819ed43-ff20-4645-a4aa-f6e5d1176a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219061416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4219061416
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2603680295
Short name T1914
Test name
Test status
Simulation time 6904589939 ps
CPU time 31.76 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 250896 kb
Host smart-53df168a-9db5-44fc-b044-b8f80e3b6bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603680295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2603680295
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.306108240
Short name T759
Test name
Test status
Simulation time 45457154852 ps
CPU time 38.61 seconds
Started Mar 07 02:45:08 PM PST 24
Finished Mar 07 02:45:47 PM PST 24
Peak memory 237332 kb
Host smart-c4fbc211-0fcf-4c43-8644-a4d704655c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306108240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.306108240
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3093742428
Short name T1719
Test name
Test status
Simulation time 6292755911 ps
CPU time 10.52 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:43:08 PM PST 24
Peak memory 233764 kb
Host smart-6022c78e-2998-49ff-b3f1-823f69c06a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093742428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3093742428
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3598864875
Short name T1404
Test name
Test status
Simulation time 1647950338 ps
CPU time 4.67 seconds
Started Mar 07 02:45:07 PM PST 24
Finished Mar 07 02:45:12 PM PST 24
Peak memory 223888 kb
Host smart-d1772b81-216e-4001-a4f3-90d36d036407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598864875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3598864875
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3240529547
Short name T1101
Test name
Test status
Simulation time 5699340231 ps
CPU time 11.79 seconds
Started Mar 07 02:45:10 PM PST 24
Finished Mar 07 02:45:22 PM PST 24
Peak memory 231956 kb
Host smart-6c4f6888-b37a-4a27-ba1b-9e69b044d1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240529547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3240529547
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.881395654
Short name T1794
Test name
Test status
Simulation time 3381322477 ps
CPU time 4.91 seconds
Started Mar 07 12:43:00 PM PST 24
Finished Mar 07 12:43:05 PM PST 24
Peak memory 233556 kb
Host smart-1e5da3a1-1805-4437-9d1c-776b5cc0ce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881395654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.881395654
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1012330628
Short name T464
Test name
Test status
Simulation time 2053607996 ps
CPU time 4.14 seconds
Started Mar 07 02:45:08 PM PST 24
Finished Mar 07 02:45:12 PM PST 24
Peak memory 221952 kb
Host smart-310c80c1-190c-4673-9115-07e68d86765e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1012330628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1012330628
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3295610795
Short name T1666
Test name
Test status
Simulation time 1161702892 ps
CPU time 3.82 seconds
Started Mar 07 12:43:06 PM PST 24
Finished Mar 07 12:43:11 PM PST 24
Peak memory 220200 kb
Host smart-39b810ed-07c2-4a9b-a1ba-e7be014652ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3295610795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3295610795
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1283155578
Short name T1528
Test name
Test status
Simulation time 11014619670 ps
CPU time 89.99 seconds
Started Mar 07 02:45:08 PM PST 24
Finished Mar 07 02:46:38 PM PST 24
Peak memory 240508 kb
Host smart-7a05b364-68f5-47a5-82b2-6c16fdd854f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283155578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1283155578
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3969138547
Short name T1327
Test name
Test status
Simulation time 46400631856 ps
CPU time 340.17 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:48:50 PM PST 24
Peak memory 272876 kb
Host smart-8670c5b5-da4f-48f1-a265-a62a6abe48f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969138547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3969138547
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1816889421
Short name T1234
Test name
Test status
Simulation time 8930764361 ps
CPU time 35.36 seconds
Started Mar 07 12:42:59 PM PST 24
Finished Mar 07 12:43:35 PM PST 24
Peak memory 216236 kb
Host smart-71b1e557-25f5-4b9b-bd0c-49ce42e95100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816889421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1816889421
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2249117443
Short name T873
Test name
Test status
Simulation time 14035362109 ps
CPU time 38.16 seconds
Started Mar 07 02:45:10 PM PST 24
Finished Mar 07 02:45:49 PM PST 24
Peak memory 214896 kb
Host smart-2ca95243-8672-4309-93de-5953652a4ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249117443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2249117443
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1279283307
Short name T349
Test name
Test status
Simulation time 7027824674 ps
CPU time 17.03 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:43:14 PM PST 24
Peak memory 216228 kb
Host smart-dc56ac98-44e4-4cf3-8535-d295e57af43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279283307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1279283307
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4138895667
Short name T1743
Test name
Test status
Simulation time 12002723270 ps
CPU time 6.41 seconds
Started Mar 07 02:45:10 PM PST 24
Finished Mar 07 02:45:16 PM PST 24
Peak memory 215796 kb
Host smart-59361c24-3d0c-49b0-80c9-54e1fe0a0b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138895667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4138895667
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2892227559
Short name T1671
Test name
Test status
Simulation time 41442260 ps
CPU time 0.81 seconds
Started Mar 07 02:45:09 PM PST 24
Finished Mar 07 02:45:10 PM PST 24
Peak memory 205688 kb
Host smart-3682e988-e84c-40f6-b085-e2a26ff3687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892227559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2892227559
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4227987192
Short name T1913
Test name
Test status
Simulation time 107887396 ps
CPU time 1.37 seconds
Started Mar 07 12:42:58 PM PST 24
Finished Mar 07 12:43:00 PM PST 24
Peak memory 216232 kb
Host smart-ed05d878-6402-4c92-9a6c-fb37943740ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227987192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4227987192
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1316472126
Short name T1653
Test name
Test status
Simulation time 20740235 ps
CPU time 0.74 seconds
Started Mar 07 02:45:08 PM PST 24
Finished Mar 07 02:45:09 PM PST 24
Peak memory 204888 kb
Host smart-f4708f07-4751-4018-bfa7-898474e3f7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316472126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1316472126
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2853642690
Short name T1622
Test name
Test status
Simulation time 90937338 ps
CPU time 0.77 seconds
Started Mar 07 12:42:57 PM PST 24
Finished Mar 07 12:42:58 PM PST 24
Peak memory 205476 kb
Host smart-cd6202bb-c18b-4369-b7ce-47bd4d278340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853642690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2853642690
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1583401195
Short name T810
Test name
Test status
Simulation time 12872296912 ps
CPU time 16.83 seconds
Started Mar 07 02:45:07 PM PST 24
Finished Mar 07 02:45:25 PM PST 24
Peak memory 240148 kb
Host smart-bb226a4a-c1b3-42cd-9802-e9b646efe300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583401195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1583401195
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_upload.1667518688
Short name T755
Test name
Test status
Simulation time 5527085580 ps
CPU time 14.42 seconds
Started Mar 07 12:43:04 PM PST 24
Finished Mar 07 12:43:18 PM PST 24
Peak memory 240404 kb
Host smart-56ea49ca-167b-4225-9663-c8de5054ccec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667518688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1667518688
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2996973697
Short name T964
Test name
Test status
Simulation time 14265893 ps
CPU time 0.7 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:45:17 PM PST 24
Peak memory 204840 kb
Host smart-9720eab3-6242-40a9-a6f6-9f4f0c056e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996973697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2996973697
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3822846668
Short name T802
Test name
Test status
Simulation time 47565953 ps
CPU time 0.71 seconds
Started Mar 07 12:43:08 PM PST 24
Finished Mar 07 12:43:09 PM PST 24
Peak memory 205204 kb
Host smart-b6f2e6d0-7cbf-4944-9885-70e9936ca94c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822846668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3822846668
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2528372983
Short name T1142
Test name
Test status
Simulation time 1293734617 ps
CPU time 6.39 seconds
Started Mar 07 02:45:20 PM PST 24
Finished Mar 07 02:45:26 PM PST 24
Peak memory 232868 kb
Host smart-0c536292-edc4-4e38-a7fd-2d36a3e8d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528372983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2528372983
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3085465527
Short name T976
Test name
Test status
Simulation time 288852956 ps
CPU time 4.39 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:43:15 PM PST 24
Peak memory 236508 kb
Host smart-499fc609-38cb-4fe9-a50d-558b457053d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085465527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3085465527
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.326317390
Short name T431
Test name
Test status
Simulation time 20083922 ps
CPU time 0.81 seconds
Started Mar 07 12:43:07 PM PST 24
Finished Mar 07 12:43:08 PM PST 24
Peak memory 206644 kb
Host smart-d263b977-7ab1-4828-91a8-dd0ebb6753a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326317390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.326317390
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3739702180
Short name T689
Test name
Test status
Simulation time 46606817 ps
CPU time 0.73 seconds
Started Mar 07 02:45:10 PM PST 24
Finished Mar 07 02:45:11 PM PST 24
Peak memory 204436 kb
Host smart-ed5a29f6-6e33-4ebc-b398-209e0ab40a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739702180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3739702180
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2485316656
Short name T1910
Test name
Test status
Simulation time 62932710389 ps
CPU time 78.26 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:46:34 PM PST 24
Peak memory 248456 kb
Host smart-438d3272-bb44-424d-a861-930d69e45194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485316656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2485316656
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3043642289
Short name T1118
Test name
Test status
Simulation time 21577838006 ps
CPU time 105.26 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:44:56 PM PST 24
Peak memory 264192 kb
Host smart-7da51c97-e8c9-4278-a4ff-e69333154253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043642289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3043642289
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1429784793
Short name T1897
Test name
Test status
Simulation time 5794352028 ps
CPU time 51.55 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:44:02 PM PST 24
Peak memory 249232 kb
Host smart-e255e9ec-0f7d-4e18-bc48-1585a8d2f0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429784793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1429784793
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2084360724
Short name T753
Test name
Test status
Simulation time 18258059300 ps
CPU time 101.94 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:46:58 PM PST 24
Peak memory 248620 kb
Host smart-673e5cf3-9eab-470b-8300-fa3e205cd083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084360724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2084360724
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1960092420
Short name T92
Test name
Test status
Simulation time 49348387285 ps
CPU time 390.46 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:51:47 PM PST 24
Peak memory 265032 kb
Host smart-490b73db-feaa-4b9f-9944-75ca18b8ae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960092420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1960092420
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.550333952
Short name T1817
Test name
Test status
Simulation time 244638913969 ps
CPU time 200.59 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:46:29 PM PST 24
Peak memory 251336 kb
Host smart-a16c2b6b-9bc9-481e-a027-c11cbb237079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550333952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.550333952
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3090347377
Short name T1146
Test name
Test status
Simulation time 2202216883 ps
CPU time 23.31 seconds
Started Mar 07 12:43:13 PM PST 24
Finished Mar 07 12:43:36 PM PST 24
Peak memory 251760 kb
Host smart-288525cc-0e1c-4a5d-b8d4-6dc101411622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090347377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3090347377
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.645635278
Short name T147
Test name
Test status
Simulation time 63041498041 ps
CPU time 44.79 seconds
Started Mar 07 02:45:15 PM PST 24
Finished Mar 07 02:46:00 PM PST 24
Peak memory 236888 kb
Host smart-75e1be02-6f52-4630-b1d0-b43ad345e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645635278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.645635278
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3063994701
Short name T1685
Test name
Test status
Simulation time 8033755040 ps
CPU time 12.68 seconds
Started Mar 07 12:43:08 PM PST 24
Finished Mar 07 12:43:21 PM PST 24
Peak memory 234720 kb
Host smart-488940a1-361c-4cc4-8706-07b4e41c075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063994701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3063994701
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3907492282
Short name T1839
Test name
Test status
Simulation time 6183160680 ps
CPU time 10.13 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:45:26 PM PST 24
Peak memory 232812 kb
Host smart-e2c2a2dc-2494-41a4-85a3-c1867ded9d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907492282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3907492282
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2733561411
Short name T769
Test name
Test status
Simulation time 1731573960 ps
CPU time 6.89 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:16 PM PST 24
Peak memory 226600 kb
Host smart-1fd94889-11ef-49e8-8cf3-dd97c90cb1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733561411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2733561411
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3556657362
Short name T1491
Test name
Test status
Simulation time 20831646582 ps
CPU time 18.44 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:45:34 PM PST 24
Peak memory 231764 kb
Host smart-026bb507-3a8f-4f97-ab43-e403c4d3e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556657362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3556657362
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1389762250
Short name T798
Test name
Test status
Simulation time 49691237718 ps
CPU time 32.36 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:45:48 PM PST 24
Peak memory 237116 kb
Host smart-96fe6e71-3ada-45f9-9ee5-a2108e0a5d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389762250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1389762250
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4073850780
Short name T306
Test name
Test status
Simulation time 9822406510 ps
CPU time 17.53 seconds
Started Mar 07 12:43:11 PM PST 24
Finished Mar 07 12:43:29 PM PST 24
Peak memory 245424 kb
Host smart-f26b034f-9209-447d-9ac3-8187f804f659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073850780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4073850780
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1480936526
Short name T1014
Test name
Test status
Simulation time 9850472460 ps
CPU time 14.96 seconds
Started Mar 07 02:45:15 PM PST 24
Finished Mar 07 02:45:30 PM PST 24
Peak memory 236136 kb
Host smart-4b61f617-116b-40ef-a23a-ea7e1e3686f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480936526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1480936526
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.226617281
Short name T1802
Test name
Test status
Simulation time 580659923 ps
CPU time 2.98 seconds
Started Mar 07 12:43:07 PM PST 24
Finished Mar 07 12:43:11 PM PST 24
Peak memory 218504 kb
Host smart-c59fe907-74f4-4a1c-a107-1ea45f8f48b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226617281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.226617281
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3165663473
Short name T1544
Test name
Test status
Simulation time 528581818 ps
CPU time 4.13 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:13 PM PST 24
Peak memory 222516 kb
Host smart-9b011579-1454-4662-8ebf-ce0bbdf9feb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3165663473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3165663473
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.659646063
Short name T403
Test name
Test status
Simulation time 2352955856 ps
CPU time 4.84 seconds
Started Mar 07 02:45:17 PM PST 24
Finished Mar 07 02:45:22 PM PST 24
Peak memory 215904 kb
Host smart-a8442c16-e621-4a81-9e76-abb874f4b44b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=659646063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.659646063
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2410452958
Short name T1541
Test name
Test status
Simulation time 238720661303 ps
CPU time 256.11 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:47:26 PM PST 24
Peak memory 271284 kb
Host smart-992e5df6-694c-4265-946d-dbb442284a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410452958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2410452958
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3676286658
Short name T308
Test name
Test status
Simulation time 16309332271 ps
CPU time 117.75 seconds
Started Mar 07 02:45:17 PM PST 24
Finished Mar 07 02:47:15 PM PST 24
Peak memory 250128 kb
Host smart-abe9b0c1-a508-4faf-814a-b940b933c755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676286658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3676286658
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1767879382
Short name T479
Test name
Test status
Simulation time 42362384211 ps
CPU time 77.64 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:44:27 PM PST 24
Peak memory 220888 kb
Host smart-87521e75-eb6e-45dc-aa5f-9a8f10b83e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767879382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1767879382
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1897673105
Short name T325
Test name
Test status
Simulation time 19888203042 ps
CPU time 58.41 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:46:14 PM PST 24
Peak memory 215788 kb
Host smart-fb936d61-c5a1-4cea-acc0-678c59e17c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897673105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1897673105
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1632723441
Short name T1096
Test name
Test status
Simulation time 9662675874 ps
CPU time 29.96 seconds
Started Mar 07 02:45:18 PM PST 24
Finished Mar 07 02:45:48 PM PST 24
Peak memory 215704 kb
Host smart-4ec3800c-bcc9-4290-a12f-4a8e0087e2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632723441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1632723441
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2400441403
Short name T894
Test name
Test status
Simulation time 4191322015 ps
CPU time 12.37 seconds
Started Mar 07 12:43:06 PM PST 24
Finished Mar 07 12:43:19 PM PST 24
Peak memory 216108 kb
Host smart-a8c57fce-766b-4080-bf7b-1b7ae9cc2db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400441403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2400441403
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3829788880
Short name T1499
Test name
Test status
Simulation time 171266564 ps
CPU time 9.58 seconds
Started Mar 07 02:45:17 PM PST 24
Finished Mar 07 02:45:26 PM PST 24
Peak memory 215740 kb
Host smart-5cfdc65c-bc7c-425c-9557-0960b811c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829788880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3829788880
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.555268611
Short name T1489
Test name
Test status
Simulation time 20742285 ps
CPU time 1.23 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:10 PM PST 24
Peak memory 216280 kb
Host smart-916c92a4-b6d0-48ae-af69-d464a78cfb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555268611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.555268611
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.285873100
Short name T1602
Test name
Test status
Simulation time 129721144 ps
CPU time 0.88 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:16 PM PST 24
Peak memory 205448 kb
Host smart-fb84fc8a-81b6-4cfc-a736-2623a2752f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285873100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.285873100
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3414849287
Short name T1915
Test name
Test status
Simulation time 91641505 ps
CPU time 0.87 seconds
Started Mar 07 02:45:17 PM PST 24
Finished Mar 07 02:45:18 PM PST 24
Peak memory 204928 kb
Host smart-21be92d4-dc70-4526-966c-410545df3055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414849287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3414849287
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1394879608
Short name T1276
Test name
Test status
Simulation time 68294463349 ps
CPU time 47.09 seconds
Started Mar 07 12:43:13 PM PST 24
Finished Mar 07 12:44:01 PM PST 24
Peak memory 235464 kb
Host smart-7ffde8a5-093d-402c-8948-c54586fda851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394879608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1394879608
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_upload.2528937841
Short name T1215
Test name
Test status
Simulation time 8912542641 ps
CPU time 9.41 seconds
Started Mar 07 02:45:16 PM PST 24
Finished Mar 07 02:45:26 PM PST 24
Peak memory 223904 kb
Host smart-5cf26e3e-a8f4-4cb6-9e76-a9822d6fe446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528937841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2528937841
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2481878119
Short name T1342
Test name
Test status
Simulation time 11301915 ps
CPU time 0.79 seconds
Started Mar 07 12:41:01 PM PST 24
Finished Mar 07 12:41:03 PM PST 24
Peak memory 205460 kb
Host smart-cca17544-dfa6-4bc4-a78b-4a7be2c5e660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481878119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
481878119
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2915539990
Short name T1334
Test name
Test status
Simulation time 14658304 ps
CPU time 0.73 seconds
Started Mar 07 02:43:02 PM PST 24
Finished Mar 07 02:43:03 PM PST 24
Peak memory 204436 kb
Host smart-21158e05-ce92-49af-8039-6232eff91db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915539990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
915539990
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3788195476
Short name T1904
Test name
Test status
Simulation time 1431647580 ps
CPU time 4.49 seconds
Started Mar 07 02:43:12 PM PST 24
Finished Mar 07 02:43:16 PM PST 24
Peak memory 232748 kb
Host smart-e47d0913-f7c0-44ef-898e-87cd9a0fef5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788195476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3788195476
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.436513326
Short name T645
Test name
Test status
Simulation time 273339199 ps
CPU time 2.41 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:02 PM PST 24
Peak memory 216204 kb
Host smart-a5a2ea37-535d-4853-a6db-7f8ef21e6516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436513326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.436513326
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2859833314
Short name T809
Test name
Test status
Simulation time 18580672 ps
CPU time 0.85 seconds
Started Mar 07 02:43:01 PM PST 24
Finished Mar 07 02:43:02 PM PST 24
Peak memory 205432 kb
Host smart-60a4c78f-a66b-4073-8594-617e33a145a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859833314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2859833314
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3032381756
Short name T1159
Test name
Test status
Simulation time 239504109 ps
CPU time 0.79 seconds
Started Mar 07 12:40:57 PM PST 24
Finished Mar 07 12:40:58 PM PST 24
Peak memory 206288 kb
Host smart-72d8d03c-0c40-4ae1-8c61-14a18c03b0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032381756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3032381756
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3362504375
Short name T384
Test name
Test status
Simulation time 68916334731 ps
CPU time 178.16 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:46:11 PM PST 24
Peak memory 266004 kb
Host smart-b8caf50c-623a-4d2b-aaa7-5cb6a734ed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362504375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3362504375
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.459029076
Short name T1588
Test name
Test status
Simulation time 22559203079 ps
CPU time 110.08 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:42:49 PM PST 24
Peak memory 239916 kb
Host smart-64592468-0658-474a-ab8c-0ef6e9dc1a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459029076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.459029076
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.702328939
Short name T253
Test name
Test status
Simulation time 10851393141 ps
CPU time 46.36 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:51 PM PST 24
Peak memory 238396 kb
Host smart-b2c1225b-ce17-486e-a272-be1dd372f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702328939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.702328939
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.78228499
Short name T1320
Test name
Test status
Simulation time 2145742575 ps
CPU time 35.2 seconds
Started Mar 07 12:40:58 PM PST 24
Finished Mar 07 12:41:33 PM PST 24
Peak memory 232640 kb
Host smart-c4497dee-bbd4-481f-80bc-e3e4c69189ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78228499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.78228499
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1926791606
Short name T1
Test name
Test status
Simulation time 57758596017 ps
CPU time 123.98 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:45:09 PM PST 24
Peak memory 248988 kb
Host smart-ddcd61e7-f537-4796-8e17-9cb73a961ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926791606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1926791606
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3247134348
Short name T267
Test name
Test status
Simulation time 116736809461 ps
CPU time 137.56 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:43:17 PM PST 24
Peak memory 248988 kb
Host smart-e7128a01-7f3c-46f8-9db9-12eb3d5f9829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247134348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3247134348
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2204076586
Short name T631
Test name
Test status
Simulation time 629211739 ps
CPU time 8.09 seconds
Started Mar 07 02:43:05 PM PST 24
Finished Mar 07 02:43:13 PM PST 24
Peak memory 231976 kb
Host smart-d6cc1a1c-9f07-490b-9615-2b37884cfce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204076586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2204076586
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4192950140
Short name T1573
Test name
Test status
Simulation time 10189876224 ps
CPU time 24.54 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:25 PM PST 24
Peak memory 232360 kb
Host smart-a8f9cc34-0e95-446c-b3f9-83e5707c01b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192950140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4192950140
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3769526246
Short name T375
Test name
Test status
Simulation time 3066524991 ps
CPU time 2.74 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:40:59 PM PST 24
Peak memory 224564 kb
Host smart-8a865112-2b09-49f7-9808-9fd319dcf4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769526246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3769526246
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intercept.685875117
Short name T1867
Test name
Test status
Simulation time 570886945 ps
CPU time 4.38 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:09 PM PST 24
Peak memory 232880 kb
Host smart-e019a095-b831-41a9-b37b-64ddfaabc909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685875117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.685875117
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2240112276
Short name T244
Test name
Test status
Simulation time 11411468543 ps
CPU time 17.31 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:17 PM PST 24
Peak memory 239992 kb
Host smart-88ad34b4-80c5-47e3-85a1-e35d6bb43d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240112276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2240112276
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3062959438
Short name T1564
Test name
Test status
Simulation time 5228933508 ps
CPU time 10.49 seconds
Started Mar 07 02:43:03 PM PST 24
Finished Mar 07 02:43:14 PM PST 24
Peak memory 233104 kb
Host smart-5de6603b-6d65-44b7-94bc-3aab08e75316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062959438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3062959438
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2701220389
Short name T860
Test name
Test status
Simulation time 25684127 ps
CPU time 1.1 seconds
Started Mar 07 02:42:57 PM PST 24
Finished Mar 07 02:42:58 PM PST 24
Peak memory 217300 kb
Host smart-16e20ab0-6c5c-4224-bbd7-cea17582528f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701220389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2701220389
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1284948493
Short name T1872
Test name
Test status
Simulation time 52036722517 ps
CPU time 40.43 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:40 PM PST 24
Peak memory 238732 kb
Host smart-24a07871-392d-456e-b2dd-9b3bb9d4eb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284948493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1284948493
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.649212357
Short name T27
Test name
Test status
Simulation time 8520192308 ps
CPU time 19.88 seconds
Started Mar 07 02:43:06 PM PST 24
Finished Mar 07 02:43:27 PM PST 24
Peak memory 218140 kb
Host smart-484bef9a-e2c5-4496-9cbc-f427fcf8dd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649212357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
649212357
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2512038779
Short name T494
Test name
Test status
Simulation time 10048094137 ps
CPU time 29.55 seconds
Started Mar 07 12:40:59 PM PST 24
Finished Mar 07 12:41:29 PM PST 24
Peak memory 249140 kb
Host smart-8841fb4b-f777-4e92-b67e-5f0d04931dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512038779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2512038779
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3233026871
Short name T1120
Test name
Test status
Simulation time 13635671492 ps
CPU time 18.68 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:23 PM PST 24
Peak memory 232908 kb
Host smart-22cb8cfc-710e-4926-bafb-4b81ba165ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233026871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3233026871
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.806160305
Short name T508
Test name
Test status
Simulation time 45228091 ps
CPU time 0.73 seconds
Started Mar 07 02:42:56 PM PST 24
Finished Mar 07 02:42:57 PM PST 24
Peak memory 215664 kb
Host smart-576455c4-3a6a-4eb1-8032-99b613b2cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806160305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.806160305
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.963080555
Short name T1020
Test name
Test status
Simulation time 18793396 ps
CPU time 0.77 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:40:58 PM PST 24
Peak memory 216140 kb
Host smart-4a298566-b8b8-4f47-8362-45dab84a1fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963080555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.963080555
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.103550475
Short name T450
Test name
Test status
Simulation time 271672572 ps
CPU time 4.47 seconds
Started Mar 07 12:40:58 PM PST 24
Finished Mar 07 12:41:03 PM PST 24
Peak memory 222244 kb
Host smart-e4c2ecfd-1ddd-4094-b4e2-bdc9706a5025
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=103550475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.103550475
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3412981477
Short name T1590
Test name
Test status
Simulation time 2909187511 ps
CPU time 4.85 seconds
Started Mar 07 02:43:07 PM PST 24
Finished Mar 07 02:43:13 PM PST 24
Peak memory 219824 kb
Host smart-aef1daf4-e398-4e20-bd7f-4f054186f1a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3412981477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3412981477
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.357211478
Short name T68
Test name
Test status
Simulation time 153665237 ps
CPU time 0.94 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:06 PM PST 24
Peak memory 235056 kb
Host smart-0608d7fa-b826-4242-9a8d-c1b20e8ff286
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357211478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.357211478
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.465782268
Short name T73
Test name
Test status
Simulation time 169166735 ps
CPU time 1.35 seconds
Started Mar 07 12:41:01 PM PST 24
Finished Mar 07 12:41:03 PM PST 24
Peak memory 235632 kb
Host smart-cb020a70-7ff3-4ea7-a629-e8c25ee6c8f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465782268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.465782268
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1714560624
Short name T1426
Test name
Test status
Simulation time 84210433427 ps
CPU time 295.72 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:48:00 PM PST 24
Peak memory 265056 kb
Host smart-a19b0041-4138-45db-ba56-c63b7de0bf40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714560624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1714560624
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3328279310
Short name T1826
Test name
Test status
Simulation time 864158315063 ps
CPU time 774.29 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:53:55 PM PST 24
Peak memory 257388 kb
Host smart-0cb228d2-b61e-404f-99b7-ccc6ebe98285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328279310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3328279310
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1262979622
Short name T1369
Test name
Test status
Simulation time 1175918766 ps
CPU time 9.38 seconds
Started Mar 07 12:40:56 PM PST 24
Finished Mar 07 12:41:06 PM PST 24
Peak memory 216264 kb
Host smart-cb4c61aa-8bb5-4a06-8109-ebc69e6fc02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262979622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1262979622
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.785032271
Short name T745
Test name
Test status
Simulation time 2262177081 ps
CPU time 27.15 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:31 PM PST 24
Peak memory 215860 kb
Host smart-f22c329f-6d77-4989-9e36-389dff3806db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785032271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.785032271
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3101782859
Short name T367
Test name
Test status
Simulation time 9943474051 ps
CPU time 25.21 seconds
Started Mar 07 02:43:00 PM PST 24
Finished Mar 07 02:43:26 PM PST 24
Peak memory 215760 kb
Host smart-00883470-ac83-4b18-9e9b-b03ac58dcd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101782859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3101782859
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4099678031
Short name T694
Test name
Test status
Simulation time 3519587399 ps
CPU time 2.63 seconds
Started Mar 07 12:40:57 PM PST 24
Finished Mar 07 12:41:00 PM PST 24
Peak memory 216152 kb
Host smart-152270c0-da69-4f9c-ba6f-3b023c55a542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099678031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4099678031
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.124221467
Short name T124
Test name
Test status
Simulation time 67012949 ps
CPU time 1.64 seconds
Started Mar 07 02:43:07 PM PST 24
Finished Mar 07 02:43:09 PM PST 24
Peak memory 215780 kb
Host smart-d91b462e-e262-4f4c-b652-c88d0b99de3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124221467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.124221467
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3917630080
Short name T1844
Test name
Test status
Simulation time 67015609 ps
CPU time 1.44 seconds
Started Mar 07 12:41:01 PM PST 24
Finished Mar 07 12:41:03 PM PST 24
Peak memory 216280 kb
Host smart-4df7c17c-e184-4f3b-b29c-1cb3f1dd8281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917630080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3917630080
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1613745963
Short name T58
Test name
Test status
Simulation time 26697863 ps
CPU time 0.81 seconds
Started Mar 07 12:40:58 PM PST 24
Finished Mar 07 12:41:00 PM PST 24
Peak memory 205464 kb
Host smart-bd90f5e1-94fd-4959-8834-2a7535c8b989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613745963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1613745963
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.716607007
Short name T519
Test name
Test status
Simulation time 96823478 ps
CPU time 0.86 seconds
Started Mar 07 02:43:05 PM PST 24
Finished Mar 07 02:43:06 PM PST 24
Peak memory 204888 kb
Host smart-2c39803c-9138-4b87-8e25-2b45719884a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716607007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.716607007
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1131253438
Short name T1542
Test name
Test status
Simulation time 578002072 ps
CPU time 2.36 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:06 PM PST 24
Peak memory 218096 kb
Host smart-68d12c83-c73f-4703-8842-14b7d03aa3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131253438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1131253438
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_upload.1821776799
Short name T1350
Test name
Test status
Simulation time 35367839676 ps
CPU time 34.06 seconds
Started Mar 07 12:41:02 PM PST 24
Finished Mar 07 12:41:37 PM PST 24
Peak memory 242744 kb
Host smart-73b27812-58a9-4342-9afd-71f7a4d16a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821776799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1821776799
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1885015345
Short name T346
Test name
Test status
Simulation time 33172178 ps
CPU time 0.7 seconds
Started Mar 07 02:45:27 PM PST 24
Finished Mar 07 02:45:28 PM PST 24
Peak memory 204444 kb
Host smart-072958eb-6e22-4c8d-87a8-bfab9ebcca93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885015345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1885015345
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2128619473
Short name T62
Test name
Test status
Simulation time 39138829 ps
CPU time 0.76 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:10 PM PST 24
Peak memory 204568 kb
Host smart-87671660-ca0e-47c6-baac-fc6688eb825b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128619473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2128619473
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3405150942
Short name T641
Test name
Test status
Simulation time 1124997186 ps
CPU time 5.36 seconds
Started Mar 07 02:45:24 PM PST 24
Finished Mar 07 02:45:29 PM PST 24
Peak memory 218836 kb
Host smart-0f4cd979-69db-4111-84cd-ec144158ced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405150942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3405150942
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.542967887
Short name T524
Test name
Test status
Simulation time 1247540413 ps
CPU time 4.21 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:14 PM PST 24
Peak memory 217824 kb
Host smart-c5489f35-e9f8-4563-afe1-4c37b30206d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542967887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.542967887
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3505291436
Short name T1408
Test name
Test status
Simulation time 41061599 ps
CPU time 0.75 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:10 PM PST 24
Peak memory 206580 kb
Host smart-5edc26f7-82be-4009-8b44-a580a60dda96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505291436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3505291436
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.651933652
Short name T14
Test name
Test status
Simulation time 79428657 ps
CPU time 0.75 seconds
Started Mar 07 02:45:19 PM PST 24
Finished Mar 07 02:45:20 PM PST 24
Peak memory 205540 kb
Host smart-905dd199-090c-4be8-a8e6-a6c75ce188d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651933652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.651933652
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1517968659
Short name T991
Test name
Test status
Simulation time 74370318128 ps
CPU time 24.01 seconds
Started Mar 07 02:45:27 PM PST 24
Finished Mar 07 02:45:51 PM PST 24
Peak memory 235856 kb
Host smart-6f46ff41-a9cc-4a2a-94bf-e561cfc587cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517968659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1517968659
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.886438477
Short name T1813
Test name
Test status
Simulation time 4372540398 ps
CPU time 34.49 seconds
Started Mar 07 12:43:11 PM PST 24
Finished Mar 07 12:43:45 PM PST 24
Peak memory 251844 kb
Host smart-162b453e-a469-48c0-9d0a-4b1f937f5da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886438477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.886438477
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4199938708
Short name T1222
Test name
Test status
Simulation time 6770422147 ps
CPU time 43.86 seconds
Started Mar 07 02:45:24 PM PST 24
Finished Mar 07 02:46:08 PM PST 24
Peak memory 232216 kb
Host smart-a31741cd-3e8b-454c-9691-102a684a5bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199938708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4199938708
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.458965149
Short name T1126
Test name
Test status
Simulation time 43286113697 ps
CPU time 83.18 seconds
Started Mar 07 12:43:12 PM PST 24
Finished Mar 07 12:44:35 PM PST 24
Peak memory 254520 kb
Host smart-340374d5-b1fe-44b8-9c15-084c5937d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458965149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.458965149
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3033075337
Short name T536
Test name
Test status
Simulation time 12434862806 ps
CPU time 152.34 seconds
Started Mar 07 02:45:23 PM PST 24
Finished Mar 07 02:47:55 PM PST 24
Peak memory 260812 kb
Host smart-97b5fd7c-c518-4ede-a3ef-a7f54e50eb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033075337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3033075337
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.981858100
Short name T1575
Test name
Test status
Simulation time 10128945692 ps
CPU time 50.99 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:44:00 PM PST 24
Peak memory 236300 kb
Host smart-9da4cb81-a528-4fa9-b46c-dc8c39564dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981858100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.981858100
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1614897311
Short name T924
Test name
Test status
Simulation time 6821245537 ps
CPU time 18.82 seconds
Started Mar 07 02:45:23 PM PST 24
Finished Mar 07 02:45:42 PM PST 24
Peak memory 246228 kb
Host smart-214b3419-1906-4bf3-bcfa-33a81bf6e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614897311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1614897311
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2649372131
Short name T1040
Test name
Test status
Simulation time 21876053769 ps
CPU time 65.55 seconds
Started Mar 07 12:43:11 PM PST 24
Finished Mar 07 12:44:17 PM PST 24
Peak memory 237704 kb
Host smart-15a8b6a3-04b9-4c8d-869c-e23cee67632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649372131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2649372131
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1711992428
Short name T458
Test name
Test status
Simulation time 135053799 ps
CPU time 3.66 seconds
Started Mar 07 12:43:06 PM PST 24
Finished Mar 07 12:43:11 PM PST 24
Peak memory 233628 kb
Host smart-4a1cc13a-c2df-4855-846e-59a2c044f7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711992428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1711992428
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1944279452
Short name T711
Test name
Test status
Simulation time 853934726 ps
CPU time 4.71 seconds
Started Mar 07 02:45:25 PM PST 24
Finished Mar 07 02:45:30 PM PST 24
Peak memory 233052 kb
Host smart-efe3edf5-b66a-4890-95a4-78e8058057eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944279452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1944279452
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1272582271
Short name T861
Test name
Test status
Simulation time 3236659375 ps
CPU time 15.4 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:26 PM PST 24
Peak memory 232824 kb
Host smart-a639f5e6-0a69-4465-bbf5-f09790be2923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272582271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1272582271
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.736654212
Short name T892
Test name
Test status
Simulation time 53353132734 ps
CPU time 39.22 seconds
Started Mar 07 02:45:23 PM PST 24
Finished Mar 07 02:46:02 PM PST 24
Peak memory 237272 kb
Host smart-36ef6490-1562-4d58-a1c0-965d0a589f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736654212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.736654212
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2482174195
Short name T279
Test name
Test status
Simulation time 25437460710 ps
CPU time 18.68 seconds
Started Mar 07 12:43:12 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 234988 kb
Host smart-6367edcf-1346-49ad-8284-3f17b112517f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482174195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2482174195
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2785909849
Short name T1788
Test name
Test status
Simulation time 373327488 ps
CPU time 3.24 seconds
Started Mar 07 02:45:22 PM PST 24
Finished Mar 07 02:45:26 PM PST 24
Peak memory 232112 kb
Host smart-33844fac-5eb8-4c77-904c-19d22de14c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785909849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2785909849
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2644158261
Short name T1562
Test name
Test status
Simulation time 3248854939 ps
CPU time 12.15 seconds
Started Mar 07 12:43:05 PM PST 24
Finished Mar 07 12:43:18 PM PST 24
Peak memory 231536 kb
Host smart-0df64839-6b9f-47d7-825f-a862f5c53821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644158261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2644158261
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3273234830
Short name T721
Test name
Test status
Simulation time 4594522696 ps
CPU time 15.98 seconds
Started Mar 07 02:45:24 PM PST 24
Finished Mar 07 02:45:40 PM PST 24
Peak memory 232384 kb
Host smart-27002a7b-47e8-429e-bb6f-38c665b8beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273234830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3273234830
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1753101463
Short name T1179
Test name
Test status
Simulation time 1836133945 ps
CPU time 4.35 seconds
Started Mar 07 02:45:24 PM PST 24
Finished Mar 07 02:45:28 PM PST 24
Peak memory 222048 kb
Host smart-b543073f-1aad-46e0-9f73-1ab621df19f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1753101463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1753101463
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2636991677
Short name T1413
Test name
Test status
Simulation time 1957105137 ps
CPU time 5.84 seconds
Started Mar 07 12:43:08 PM PST 24
Finished Mar 07 12:43:15 PM PST 24
Peak memory 222788 kb
Host smart-11dd6b43-501b-4e1d-90b4-cbe77e70fc05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2636991677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2636991677
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3277447220
Short name T1429
Test name
Test status
Simulation time 106802290822 ps
CPU time 249.86 seconds
Started Mar 07 02:45:23 PM PST 24
Finished Mar 07 02:49:33 PM PST 24
Peak memory 269668 kb
Host smart-5f729eb2-abfc-4e01-8888-cd2461c0fc35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277447220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3277447220
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.966305940
Short name T911
Test name
Test status
Simulation time 9923169063 ps
CPU time 55.64 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:44:06 PM PST 24
Peak memory 232744 kb
Host smart-d52925fd-c670-43da-a717-e349becd6a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966305940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.966305940
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3119540439
Short name T462
Test name
Test status
Simulation time 2746385449 ps
CPU time 34.38 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:43:45 PM PST 24
Peak memory 216304 kb
Host smart-2e1cfdb8-5196-4263-8bf9-70bfef4eb345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119540439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3119540439
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.467272697
Short name T1043
Test name
Test status
Simulation time 3144840762 ps
CPU time 25.72 seconds
Started Mar 07 02:45:24 PM PST 24
Finished Mar 07 02:45:50 PM PST 24
Peak memory 215648 kb
Host smart-40f6e513-27a9-4d87-b322-30094ea5c571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467272697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.467272697
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2748233137
Short name T578
Test name
Test status
Simulation time 25567101478 ps
CPU time 20.55 seconds
Started Mar 07 02:45:15 PM PST 24
Finished Mar 07 02:45:35 PM PST 24
Peak memory 215848 kb
Host smart-4c08005e-da7b-4d4b-afd5-046e83e01d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748233137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2748233137
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3333972261
Short name T484
Test name
Test status
Simulation time 7637430382 ps
CPU time 22.41 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 216188 kb
Host smart-ded5b779-25f1-4097-9f96-b3c6dcba3fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333972261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3333972261
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1287957773
Short name T993
Test name
Test status
Simulation time 722974737 ps
CPU time 3.09 seconds
Started Mar 07 12:43:11 PM PST 24
Finished Mar 07 12:43:14 PM PST 24
Peak memory 216188 kb
Host smart-9f44c621-330b-4549-a393-1ffc93b0e2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287957773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1287957773
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2201428004
Short name T1345
Test name
Test status
Simulation time 232146482 ps
CPU time 7.27 seconds
Started Mar 07 02:45:23 PM PST 24
Finished Mar 07 02:45:31 PM PST 24
Peak memory 215792 kb
Host smart-0e6cb5a2-8bc4-4d9d-a21f-fa7357a55b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201428004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2201428004
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4051685749
Short name T1824
Test name
Test status
Simulation time 74593215 ps
CPU time 0.7 seconds
Started Mar 07 02:45:25 PM PST 24
Finished Mar 07 02:45:25 PM PST 24
Peak memory 204920 kb
Host smart-bb24be9b-64a1-4238-a5b2-246d8b01b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051685749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4051685749
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.733199464
Short name T1282
Test name
Test status
Simulation time 43777350 ps
CPU time 0.86 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:11 PM PST 24
Peak memory 205412 kb
Host smart-02501bc0-b032-471b-a0b2-9df010ab8e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733199464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.733199464
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.255477087
Short name T1811
Test name
Test status
Simulation time 8910686008 ps
CPU time 9.16 seconds
Started Mar 07 12:43:12 PM PST 24
Finished Mar 07 12:43:22 PM PST 24
Peak memory 235600 kb
Host smart-6b08ef5f-6e90-44de-8464-f14e22e3884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255477087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.255477087
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_upload.3322567203
Short name T1008
Test name
Test status
Simulation time 1493494572 ps
CPU time 12.76 seconds
Started Mar 07 02:45:23 PM PST 24
Finished Mar 07 02:45:36 PM PST 24
Peak memory 248444 kb
Host smart-38e4bf21-e171-40c1-9cee-5312bc060ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322567203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3322567203
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4261741404
Short name T681
Test name
Test status
Simulation time 21492881 ps
CPU time 0.69 seconds
Started Mar 07 12:43:11 PM PST 24
Finished Mar 07 12:43:12 PM PST 24
Peak memory 205484 kb
Host smart-c58be3e6-42c5-4485-8fe9-767b7f9f1983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261741404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4261741404
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.921688758
Short name T1821
Test name
Test status
Simulation time 13439152 ps
CPU time 0.72 seconds
Started Mar 07 02:45:28 PM PST 24
Finished Mar 07 02:45:29 PM PST 24
Peak memory 203860 kb
Host smart-2d7c4b6d-34e7-448f-8e95-b2e2acc4cd54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921688758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.921688758
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3126072404
Short name T332
Test name
Test status
Simulation time 49485986 ps
CPU time 2.51 seconds
Started Mar 07 02:45:25 PM PST 24
Finished Mar 07 02:45:28 PM PST 24
Peak memory 233796 kb
Host smart-360c209d-e149-433d-8191-de0fb97374b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126072404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3126072404
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3971053663
Short name T262
Test name
Test status
Simulation time 4221364898 ps
CPU time 3.61 seconds
Started Mar 07 12:43:13 PM PST 24
Finished Mar 07 12:43:16 PM PST 24
Peak memory 219476 kb
Host smart-27aa7236-06de-4ca8-b5a6-6586312ecc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971053663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3971053663
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1349606776
Short name T729
Test name
Test status
Simulation time 27238083 ps
CPU time 0.78 seconds
Started Mar 07 12:43:08 PM PST 24
Finished Mar 07 12:43:09 PM PST 24
Peak memory 206272 kb
Host smart-45237193-3290-4daf-adbc-743536a74623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349606776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1349606776
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.664898850
Short name T410
Test name
Test status
Simulation time 56361145 ps
CPU time 0.77 seconds
Started Mar 07 02:45:27 PM PST 24
Finished Mar 07 02:45:28 PM PST 24
Peak memory 205828 kb
Host smart-73e39bb6-f195-4721-b96c-4298bc3a0923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664898850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.664898850
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2461725516
Short name T1687
Test name
Test status
Simulation time 5792885125 ps
CPU time 61.77 seconds
Started Mar 07 02:45:26 PM PST 24
Finished Mar 07 02:46:28 PM PST 24
Peak memory 256672 kb
Host smart-4d334cff-3ce3-4b54-b8f9-4c581174ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461725516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2461725516
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3046093525
Short name T552
Test name
Test status
Simulation time 14361069241 ps
CPU time 43.87 seconds
Started Mar 07 12:43:09 PM PST 24
Finished Mar 07 12:43:53 PM PST 24
Peak memory 250068 kb
Host smart-8a4bde29-e358-45a0-b486-ae7c84750de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046093525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3046093525
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1783443420
Short name T31
Test name
Test status
Simulation time 38422906059 ps
CPU time 284.26 seconds
Started Mar 07 02:45:25 PM PST 24
Finished Mar 07 02:50:09 PM PST 24
Peak memory 253756 kb
Host smart-64229546-3e9d-43aa-a206-f94be493aec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783443420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1783443420
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2669394374
Short name T819
Test name
Test status
Simulation time 25365671203 ps
CPU time 186 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:46:16 PM PST 24
Peak memory 257304 kb
Host smart-679ae1dd-9ca0-4728-b4d5-5f530e31408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669394374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2669394374
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1260696740
Short name T268
Test name
Test status
Simulation time 26465326063 ps
CPU time 145.11 seconds
Started Mar 07 02:45:28 PM PST 24
Finished Mar 07 02:47:53 PM PST 24
Peak memory 256360 kb
Host smart-d59d0040-abc3-4ad8-8153-34f310de071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260696740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1260696740
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.561161194
Short name T945
Test name
Test status
Simulation time 5719903391 ps
CPU time 26.1 seconds
Started Mar 07 12:43:13 PM PST 24
Finished Mar 07 12:43:39 PM PST 24
Peak memory 240904 kb
Host smart-de260f58-79a9-4271-a144-ab3df2ee88e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561161194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.561161194
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1959517318
Short name T884
Test name
Test status
Simulation time 313825921 ps
CPU time 3.26 seconds
Started Mar 07 02:45:24 PM PST 24
Finished Mar 07 02:45:28 PM PST 24
Peak memory 233024 kb
Host smart-c343283d-ed76-493d-b11d-e5e23ccbe6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959517318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1959517318
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3940767997
Short name T1283
Test name
Test status
Simulation time 6071610462 ps
CPU time 10.88 seconds
Started Mar 07 12:43:13 PM PST 24
Finished Mar 07 12:43:24 PM PST 24
Peak memory 217808 kb
Host smart-f5c70072-0422-45ad-a0d7-6f9d0523ad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940767997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3940767997
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.364674135
Short name T864
Test name
Test status
Simulation time 4163931245 ps
CPU time 7.87 seconds
Started Mar 07 02:45:27 PM PST 24
Finished Mar 07 02:45:35 PM PST 24
Peak memory 217828 kb
Host smart-a2e039e9-fc0d-44f8-b300-717d65835cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364674135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.364674135
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.599619076
Short name T1322
Test name
Test status
Simulation time 1929642507 ps
CPU time 7.69 seconds
Started Mar 07 12:43:12 PM PST 24
Finished Mar 07 12:43:20 PM PST 24
Peak memory 230156 kb
Host smart-0cb6431e-3a7a-4b76-9460-ecc2dd02829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599619076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.599619076
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2090254416
Short name T719
Test name
Test status
Simulation time 42045145 ps
CPU time 2.53 seconds
Started Mar 07 02:45:27 PM PST 24
Finished Mar 07 02:45:30 PM PST 24
Peak memory 232084 kb
Host smart-bfafb509-e8c0-4c7a-adac-bb69e03dea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090254416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2090254416
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2938971044
Short name T261
Test name
Test status
Simulation time 1153988571 ps
CPU time 12.46 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:43:23 PM PST 24
Peak memory 240828 kb
Host smart-69e1f3f9-cd24-4819-910a-997b5b3ac761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938971044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2938971044
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1633748164
Short name T1302
Test name
Test status
Simulation time 39857128697 ps
CPU time 32.53 seconds
Started Mar 07 12:43:12 PM PST 24
Finished Mar 07 12:43:45 PM PST 24
Peak memory 246100 kb
Host smart-d8558c3d-74c8-4041-92cf-ed5447720089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633748164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1633748164
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3204146965
Short name T531
Test name
Test status
Simulation time 367094700 ps
CPU time 5.74 seconds
Started Mar 07 02:45:26 PM PST 24
Finished Mar 07 02:45:32 PM PST 24
Peak memory 234364 kb
Host smart-be4c4441-c310-493c-bd34-a3f3341c5066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204146965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3204146965
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3642875015
Short name T1903
Test name
Test status
Simulation time 198725770 ps
CPU time 3.41 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:43:14 PM PST 24
Peak memory 219832 kb
Host smart-82832467-0fca-4528-b85d-38a22e3f7eba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3642875015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3642875015
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3684317651
Short name T1115
Test name
Test status
Simulation time 1871867478 ps
CPU time 7.44 seconds
Started Mar 07 02:45:28 PM PST 24
Finished Mar 07 02:45:36 PM PST 24
Peak memory 220908 kb
Host smart-c34f8d78-5190-4f7f-b4d5-1c8686368f1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3684317651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3684317651
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1522910233
Short name T1467
Test name
Test status
Simulation time 122634419980 ps
CPU time 636.8 seconds
Started Mar 07 12:43:11 PM PST 24
Finished Mar 07 12:53:48 PM PST 24
Peak memory 268532 kb
Host smart-329b1726-9716-46d1-9efe-e53e4bd002ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522910233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1522910233
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1713253066
Short name T292
Test name
Test status
Simulation time 194801407937 ps
CPU time 577.4 seconds
Started Mar 07 02:45:39 PM PST 24
Finished Mar 07 02:55:17 PM PST 24
Peak memory 283532 kb
Host smart-2fee5118-f81d-43e9-8fae-3d59516fff7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713253066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1713253066
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1577828390
Short name T387
Test name
Test status
Simulation time 19352432401 ps
CPU time 51.2 seconds
Started Mar 07 12:43:08 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 216276 kb
Host smart-d8a0e3c3-b4a9-445c-b2e2-e27adf0bab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577828390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1577828390
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.703224236
Short name T1332
Test name
Test status
Simulation time 6425961644 ps
CPU time 31.06 seconds
Started Mar 07 02:45:23 PM PST 24
Finished Mar 07 02:45:54 PM PST 24
Peak memory 215840 kb
Host smart-f3418f0d-4445-46cd-a753-c35cf725a92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703224236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.703224236
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1596752348
Short name T1245
Test name
Test status
Simulation time 1324924414 ps
CPU time 4.66 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:43:15 PM PST 24
Peak memory 216192 kb
Host smart-0e46fbb3-d6d9-461f-96d5-e0a33513bf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596752348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1596752348
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.903392278
Short name T1617
Test name
Test status
Simulation time 2594774011 ps
CPU time 9.2 seconds
Started Mar 07 02:45:25 PM PST 24
Finished Mar 07 02:45:34 PM PST 24
Peak memory 215864 kb
Host smart-5514aeb8-bde7-4fab-a6f9-b2d8c04c5982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903392278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.903392278
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1165314982
Short name T1870
Test name
Test status
Simulation time 1761951424 ps
CPU time 5.68 seconds
Started Mar 07 12:43:08 PM PST 24
Finished Mar 07 12:43:14 PM PST 24
Peak memory 216224 kb
Host smart-1afd1640-3436-402a-9425-bee8bb6b3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165314982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1165314982
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4065694371
Short name T555
Test name
Test status
Simulation time 151783961 ps
CPU time 7.12 seconds
Started Mar 07 02:45:24 PM PST 24
Finished Mar 07 02:45:31 PM PST 24
Peak memory 215852 kb
Host smart-05f403db-fd12-4854-a2e4-f1b3fc510e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065694371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4065694371
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2405439505
Short name T1591
Test name
Test status
Simulation time 165966117 ps
CPU time 1.23 seconds
Started Mar 07 02:45:26 PM PST 24
Finished Mar 07 02:45:27 PM PST 24
Peak memory 205944 kb
Host smart-f10d3810-450e-4f4b-84a7-e1c2d082bd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405439505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2405439505
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3093171613
Short name T1819
Test name
Test status
Simulation time 123529116 ps
CPU time 0.86 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:16 PM PST 24
Peak memory 205440 kb
Host smart-37399c5d-e874-4334-b7ee-201cf15326ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093171613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3093171613
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1564699331
Short name T235
Test name
Test status
Simulation time 181678036 ps
CPU time 2.47 seconds
Started Mar 07 12:43:10 PM PST 24
Finished Mar 07 12:43:13 PM PST 24
Peak memory 224444 kb
Host smart-ae5b88e5-3004-4b88-853a-69ae0eb70579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564699331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1564699331
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_upload.647320757
Short name T465
Test name
Test status
Simulation time 9932798248 ps
CPU time 8.22 seconds
Started Mar 07 02:45:26 PM PST 24
Finished Mar 07 02:45:34 PM PST 24
Peak memory 237336 kb
Host smart-2473c390-6078-4606-b48e-edf7bd556599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647320757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.647320757
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1378688008
Short name T1287
Test name
Test status
Simulation time 18401148 ps
CPU time 0.69 seconds
Started Mar 07 12:43:17 PM PST 24
Finished Mar 07 12:43:18 PM PST 24
Peak memory 205464 kb
Host smart-174f6abb-fcde-4615-bf9c-c12cc92ae03b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378688008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1378688008
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1522309977
Short name T652
Test name
Test status
Simulation time 14173647 ps
CPU time 0.71 seconds
Started Mar 07 02:45:34 PM PST 24
Finished Mar 07 02:45:35 PM PST 24
Peak memory 204416 kb
Host smart-36a5ff9e-7a37-480d-a520-9d795354ca97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522309977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1522309977
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1129781323
Short name T1217
Test name
Test status
Simulation time 745670965 ps
CPU time 4.99 seconds
Started Mar 07 12:43:18 PM PST 24
Finished Mar 07 12:43:23 PM PST 24
Peak memory 233672 kb
Host smart-603b2173-f083-483d-aa6b-63141d4099fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129781323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1129781323
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4265285123
Short name T1406
Test name
Test status
Simulation time 85594720 ps
CPU time 2.99 seconds
Started Mar 07 02:45:38 PM PST 24
Finished Mar 07 02:45:41 PM PST 24
Peak memory 232680 kb
Host smart-78bcaa68-2745-4cbd-b95b-33eda6ddb4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265285123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4265285123
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1800813028
Short name T1642
Test name
Test status
Simulation time 56824543 ps
CPU time 0.77 seconds
Started Mar 07 02:45:29 PM PST 24
Finished Mar 07 02:45:30 PM PST 24
Peak memory 205456 kb
Host smart-ecff08db-bcac-42ce-9860-bd131997ddd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800813028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1800813028
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2444679571
Short name T868
Test name
Test status
Simulation time 68420918 ps
CPU time 0.83 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:16 PM PST 24
Peak memory 206176 kb
Host smart-ca04df3d-12d4-4720-b4ac-1a922846ff97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444679571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2444679571
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1917177062
Short name T811
Test name
Test status
Simulation time 3718893776 ps
CPU time 35.16 seconds
Started Mar 07 12:43:17 PM PST 24
Finished Mar 07 12:43:53 PM PST 24
Peak memory 238972 kb
Host smart-ce801058-50d0-4832-9534-9139d97342fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917177062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1917177062
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3675212835
Short name T1194
Test name
Test status
Simulation time 44969197877 ps
CPU time 70.65 seconds
Started Mar 07 02:45:35 PM PST 24
Finished Mar 07 02:46:46 PM PST 24
Peak memory 249576 kb
Host smart-047c950b-3a82-41b9-a511-557c376e8619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675212835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3675212835
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1210474850
Short name T1162
Test name
Test status
Simulation time 17376736129 ps
CPU time 71.01 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:44:39 PM PST 24
Peak memory 257404 kb
Host smart-f7ab4c89-803f-4c28-88a9-9f3c40da622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210474850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1210474850
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2120611587
Short name T1381
Test name
Test status
Simulation time 11899091706 ps
CPU time 71.83 seconds
Started Mar 07 02:45:37 PM PST 24
Finished Mar 07 02:46:49 PM PST 24
Peak memory 248696 kb
Host smart-cdc32eaf-6d45-4399-aba3-cfcdeec261cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120611587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2120611587
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2574903797
Short name T321
Test name
Test status
Simulation time 13376714086 ps
CPU time 97.38 seconds
Started Mar 07 02:45:39 PM PST 24
Finished Mar 07 02:47:17 PM PST 24
Peak memory 232448 kb
Host smart-49799c85-cfaa-462d-9773-49f1343503e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574903797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2574903797
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.28712216
Short name T382
Test name
Test status
Simulation time 196131800 ps
CPU time 5.26 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 235000 kb
Host smart-b7a6af06-c126-4f34-b229-1d27bcc136a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28712216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.28712216
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4059555547
Short name T653
Test name
Test status
Simulation time 911320751 ps
CPU time 11.86 seconds
Started Mar 07 02:45:38 PM PST 24
Finished Mar 07 02:45:50 PM PST 24
Peak memory 223852 kb
Host smart-d5b8a3fd-ad49-4f8b-acb8-921b61840f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059555547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4059555547
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1933905484
Short name T1869
Test name
Test status
Simulation time 32081906946 ps
CPU time 21.61 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:38 PM PST 24
Peak memory 233580 kb
Host smart-1154cc11-6cdc-4735-af60-acb2332b2c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933905484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1933905484
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3048442276
Short name T1410
Test name
Test status
Simulation time 202665577 ps
CPU time 3.37 seconds
Started Mar 07 02:45:28 PM PST 24
Finished Mar 07 02:45:31 PM PST 24
Peak memory 233028 kb
Host smart-37117d92-39af-4eca-80a6-fcd1a6f421e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048442276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3048442276
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3388534765
Short name T13
Test name
Test status
Simulation time 311191066 ps
CPU time 4.52 seconds
Started Mar 07 02:45:34 PM PST 24
Finished Mar 07 02:45:38 PM PST 24
Peak memory 223840 kb
Host smart-fc7b4e81-49b6-44a3-a2e6-e3e111c4f4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388534765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3388534765
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3399361639
Short name T442
Test name
Test status
Simulation time 2971065785 ps
CPU time 10.01 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:26 PM PST 24
Peak memory 239808 kb
Host smart-d34e9a22-2938-4253-a947-b221b0f3573b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399361639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3399361639
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.299800105
Short name T688
Test name
Test status
Simulation time 1566680903 ps
CPU time 7.2 seconds
Started Mar 07 12:43:18 PM PST 24
Finished Mar 07 12:43:25 PM PST 24
Peak memory 238276 kb
Host smart-a722a580-43c3-4dc6-b609-3260a88e44a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299800105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.299800105
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3099723849
Short name T1111
Test name
Test status
Simulation time 1564803574 ps
CPU time 4.4 seconds
Started Mar 07 02:45:29 PM PST 24
Finished Mar 07 02:45:33 PM PST 24
Peak memory 215868 kb
Host smart-272db7e0-1e56-4366-8760-8a8eae929005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099723849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3099723849
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3400091728
Short name T1117
Test name
Test status
Simulation time 15025057469 ps
CPU time 8.05 seconds
Started Mar 07 12:43:19 PM PST 24
Finished Mar 07 12:43:28 PM PST 24
Peak memory 222608 kb
Host smart-d9342578-983e-4c9f-af70-639e46050785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400091728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3400091728
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3424878849
Short name T1359
Test name
Test status
Simulation time 3186936968 ps
CPU time 11.75 seconds
Started Mar 07 02:45:26 PM PST 24
Finished Mar 07 02:45:38 PM PST 24
Peak memory 232908 kb
Host smart-8019e530-a49e-451d-9896-aa97e55ed2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424878849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3424878849
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.130902912
Short name T411
Test name
Test status
Simulation time 1010186849 ps
CPU time 4.61 seconds
Started Mar 07 02:45:39 PM PST 24
Finished Mar 07 02:45:44 PM PST 24
Peak memory 222068 kb
Host smart-4cf75034-9fe5-43db-802c-d65bc126488b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=130902912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.130902912
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2630321498
Short name T684
Test name
Test status
Simulation time 402081532 ps
CPU time 3.36 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:19 PM PST 24
Peak memory 219024 kb
Host smart-4f06e1d8-3460-4104-bd65-11435a09f86a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2630321498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2630321498
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3299436002
Short name T957
Test name
Test status
Simulation time 51613758887 ps
CPU time 278.56 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:48:07 PM PST 24
Peak memory 250260 kb
Host smart-190cf4d8-95d5-437d-aa1e-fb49948f499f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299436002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3299436002
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1117443008
Short name T362
Test name
Test status
Simulation time 8346254040 ps
CPU time 29.87 seconds
Started Mar 07 02:45:31 PM PST 24
Finished Mar 07 02:46:01 PM PST 24
Peak memory 215812 kb
Host smart-bfa8c46b-5b5a-441c-a171-3ff4fb37bdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117443008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1117443008
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3713666054
Short name T1274
Test name
Test status
Simulation time 9856686512 ps
CPU time 34.2 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:50 PM PST 24
Peak memory 216220 kb
Host smart-963ca879-9085-4d5f-98e5-fd21a4f30161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713666054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3713666054
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3013861382
Short name T777
Test name
Test status
Simulation time 3040837406 ps
CPU time 4.06 seconds
Started Mar 07 02:45:28 PM PST 24
Finished Mar 07 02:45:32 PM PST 24
Peak memory 215816 kb
Host smart-997d407b-829b-4f96-a320-ba0e72471ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013861382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3013861382
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.777303422
Short name T844
Test name
Test status
Simulation time 605643204 ps
CPU time 3.96 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:20 PM PST 24
Peak memory 216240 kb
Host smart-e04b8907-99f2-4d90-bec9-6eb171000e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777303422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.777303422
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1599330649
Short name T347
Test name
Test status
Simulation time 163503467 ps
CPU time 1.54 seconds
Started Mar 07 12:43:17 PM PST 24
Finished Mar 07 12:43:18 PM PST 24
Peak memory 216200 kb
Host smart-d756fd26-4e3f-430b-a6a7-7f6fe5f62609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599330649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1599330649
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2559838365
Short name T338
Test name
Test status
Simulation time 1049531887 ps
CPU time 2.27 seconds
Started Mar 07 02:45:31 PM PST 24
Finished Mar 07 02:45:33 PM PST 24
Peak memory 215780 kb
Host smart-7bbd8be8-6a8e-44ea-88fe-8a8f08e88b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559838365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2559838365
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2122031436
Short name T1540
Test name
Test status
Simulation time 504755158 ps
CPU time 1.1 seconds
Started Mar 07 02:45:30 PM PST 24
Finished Mar 07 02:45:32 PM PST 24
Peak memory 205848 kb
Host smart-ecba2528-a39b-425a-9b2c-6721826dea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122031436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2122031436
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2217415543
Short name T438
Test name
Test status
Simulation time 12255380 ps
CPU time 0.69 seconds
Started Mar 07 12:43:18 PM PST 24
Finished Mar 07 12:43:19 PM PST 24
Peak memory 205444 kb
Host smart-2602c081-b88c-4b04-8ff1-82d92ccdab11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217415543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2217415543
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2495295652
Short name T606
Test name
Test status
Simulation time 23481105194 ps
CPU time 7.81 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:24 PM PST 24
Peak memory 218516 kb
Host smart-e1454e42-eca7-46ba-a856-fd715d58a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495295652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2495295652
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_upload.3797318311
Short name T57
Test name
Test status
Simulation time 8150595344 ps
CPU time 7.53 seconds
Started Mar 07 02:45:34 PM PST 24
Finished Mar 07 02:45:42 PM PST 24
Peak memory 233308 kb
Host smart-f698437c-a5b0-498c-9ffa-370f8b824bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797318311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3797318311
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1158730519
Short name T1865
Test name
Test status
Simulation time 19960123 ps
CPU time 0.72 seconds
Started Mar 07 02:45:37 PM PST 24
Finished Mar 07 02:45:38 PM PST 24
Peak memory 204488 kb
Host smart-325002cb-7573-452e-bb6a-05df4e7206c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158730519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1158730519
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.895488737
Short name T944
Test name
Test status
Simulation time 14197039 ps
CPU time 0.73 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:29 PM PST 24
Peak memory 205460 kb
Host smart-3ae5b798-a7f6-47bb-8e14-1f554f9f0276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895488737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.895488737
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3660990453
Short name T416
Test name
Test status
Simulation time 2925535144 ps
CPU time 3.61 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:20 PM PST 24
Peak memory 216708 kb
Host smart-41838fd3-c8b9-4f6d-a8e9-1730cc75aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660990453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3660990453
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4212634769
Short name T1639
Test name
Test status
Simulation time 1664530070 ps
CPU time 6.77 seconds
Started Mar 07 02:45:39 PM PST 24
Finished Mar 07 02:45:46 PM PST 24
Peak memory 233748 kb
Host smart-2ec588ec-287f-4f8d-a748-aa763fafde34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212634769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4212634769
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.106850079
Short name T743
Test name
Test status
Simulation time 17095853 ps
CPU time 0.76 seconds
Started Mar 07 02:45:33 PM PST 24
Finished Mar 07 02:45:34 PM PST 24
Peak memory 205516 kb
Host smart-f8478a49-d004-4415-9eaa-a5b3c39d92c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106850079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.106850079
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1097647306
Short name T609
Test name
Test status
Simulation time 21717796 ps
CPU time 0.71 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:28 PM PST 24
Peak memory 205568 kb
Host smart-365f6946-d330-4342-93c0-29121f7028ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097647306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1097647306
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1128173961
Short name T533
Test name
Test status
Simulation time 132520114571 ps
CPU time 187.28 seconds
Started Mar 07 02:45:35 PM PST 24
Finished Mar 07 02:48:43 PM PST 24
Peak memory 256788 kb
Host smart-bfa32698-492f-42ff-afe3-17786fc6b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128173961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1128173961
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2777222117
Short name T294
Test name
Test status
Simulation time 124283197351 ps
CPU time 312.49 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:48:41 PM PST 24
Peak memory 257276 kb
Host smart-92132170-07ec-4111-9b01-cb10a1318ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777222117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2777222117
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3589746510
Short name T1873
Test name
Test status
Simulation time 1256570978 ps
CPU time 15.78 seconds
Started Mar 07 02:45:35 PM PST 24
Finished Mar 07 02:45:50 PM PST 24
Peak memory 220152 kb
Host smart-fed2a06a-34a7-45fb-b128-ee22e77a7258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589746510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3589746510
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1048813702
Short name T469
Test name
Test status
Simulation time 33985311951 ps
CPU time 231.94 seconds
Started Mar 07 02:45:33 PM PST 24
Finished Mar 07 02:49:25 PM PST 24
Peak memory 240460 kb
Host smart-c21b956b-c92a-4701-9551-2390e683a157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048813702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1048813702
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.230229233
Short name T470
Test name
Test status
Simulation time 1752334332 ps
CPU time 14.98 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 239660 kb
Host smart-01840a5e-7d76-450b-85d4-796dc56117e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230229233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.230229233
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1751081145
Short name T1333
Test name
Test status
Simulation time 2197937748 ps
CPU time 17.36 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:34 PM PST 24
Peak memory 240376 kb
Host smart-8c1c7a6e-dd07-45e0-b7bd-021d3ab6e58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751081145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1751081145
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.678901660
Short name T734
Test name
Test status
Simulation time 688343577 ps
CPU time 6.6 seconds
Started Mar 07 02:45:35 PM PST 24
Finished Mar 07 02:45:42 PM PST 24
Peak memory 231392 kb
Host smart-cd8feb4c-ddec-463f-8672-7953a5f056ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678901660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.678901660
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1245448523
Short name T977
Test name
Test status
Simulation time 47375071 ps
CPU time 2.37 seconds
Started Mar 07 12:43:19 PM PST 24
Finished Mar 07 12:43:22 PM PST 24
Peak memory 224348 kb
Host smart-c35899f2-7d44-4384-8349-76779564e2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245448523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1245448523
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2697355170
Short name T952
Test name
Test status
Simulation time 148901180 ps
CPU time 2.67 seconds
Started Mar 07 02:45:34 PM PST 24
Finished Mar 07 02:45:37 PM PST 24
Peak memory 223928 kb
Host smart-83df469e-a601-4396-bfee-ce16d41c1ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697355170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2697355170
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2400513799
Short name T1828
Test name
Test status
Simulation time 13730050395 ps
CPU time 19.87 seconds
Started Mar 07 02:45:35 PM PST 24
Finished Mar 07 02:45:55 PM PST 24
Peak memory 232748 kb
Host smart-6e09d0bd-ca5b-44b7-94a8-c5ee75a19677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400513799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2400513799
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.687528098
Short name T1688
Test name
Test status
Simulation time 79731088214 ps
CPU time 50.57 seconds
Started Mar 07 12:43:17 PM PST 24
Finished Mar 07 12:44:08 PM PST 24
Peak memory 232620 kb
Host smart-23770a60-09bc-441a-b568-8c6f18a3d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687528098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.687528098
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1546887012
Short name T55
Test name
Test status
Simulation time 172178859007 ps
CPU time 30.29 seconds
Started Mar 07 02:45:37 PM PST 24
Finished Mar 07 02:46:07 PM PST 24
Peak memory 240284 kb
Host smart-4600dda9-174e-4919-bdec-31d76ce74078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546887012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1546887012
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.41291657
Short name T663
Test name
Test status
Simulation time 691168962 ps
CPU time 3.03 seconds
Started Mar 07 12:43:13 PM PST 24
Finished Mar 07 12:43:16 PM PST 24
Peak memory 216680 kb
Host smart-8efda508-5786-49ba-bd4a-6bee4d8019f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41291657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.41291657
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1622205437
Short name T1624
Test name
Test status
Simulation time 80008043000 ps
CPU time 12.14 seconds
Started Mar 07 12:43:19 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 224512 kb
Host smart-811f04e6-fe00-456e-b6b3-e3d80da7c283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622205437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1622205437
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.412943980
Short name T800
Test name
Test status
Simulation time 4961303247 ps
CPU time 6.28 seconds
Started Mar 07 02:45:36 PM PST 24
Finished Mar 07 02:45:43 PM PST 24
Peak memory 220632 kb
Host smart-d357cd03-0629-437c-9878-83912b40f61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412943980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.412943980
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.270979209
Short name T619
Test name
Test status
Simulation time 2278554138 ps
CPU time 4.84 seconds
Started Mar 07 02:45:39 PM PST 24
Finished Mar 07 02:45:44 PM PST 24
Peak memory 221544 kb
Host smart-c178e076-0a60-4c07-be7c-abcf046f3ce4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=270979209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.270979209
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3956875827
Short name T1084
Test name
Test status
Simulation time 3630691670 ps
CPU time 7.27 seconds
Started Mar 07 12:43:18 PM PST 24
Finished Mar 07 12:43:25 PM PST 24
Peak memory 219168 kb
Host smart-4a780092-1412-480d-8955-30d535407fee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3956875827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3956875827
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1727629939
Short name T162
Test name
Test status
Simulation time 56212436 ps
CPU time 1.02 seconds
Started Mar 07 12:43:17 PM PST 24
Finished Mar 07 12:43:18 PM PST 24
Peak memory 206616 kb
Host smart-a2c594b8-7b74-450d-91aa-3e92379dbbca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727629939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1727629939
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.297641682
Short name T1156
Test name
Test status
Simulation time 205369607088 ps
CPU time 675.1 seconds
Started Mar 07 02:45:39 PM PST 24
Finished Mar 07 02:56:54 PM PST 24
Peak memory 263992 kb
Host smart-5f0e3d21-e3d9-46b4-aa1e-0cdd6f385334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297641682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.297641682
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3427831720
Short name T579
Test name
Test status
Simulation time 2267634206 ps
CPU time 21.77 seconds
Started Mar 07 02:45:37 PM PST 24
Finished Mar 07 02:45:58 PM PST 24
Peak memory 215784 kb
Host smart-2fb3d746-02aa-404d-b904-17861563a35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427831720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3427831720
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4028737761
Short name T433
Test name
Test status
Simulation time 495554909 ps
CPU time 3.1 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 216216 kb
Host smart-230f5c5e-e5c9-4937-b932-d980c4ae8fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028737761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4028737761
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2073432201
Short name T1729
Test name
Test status
Simulation time 53302633028 ps
CPU time 19.09 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:34 PM PST 24
Peak memory 216220 kb
Host smart-85434ba0-c7af-4f81-b110-a37791087214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073432201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2073432201
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3742570588
Short name T1246
Test name
Test status
Simulation time 1636652876 ps
CPU time 7.54 seconds
Started Mar 07 02:45:41 PM PST 24
Finished Mar 07 02:45:49 PM PST 24
Peak memory 215736 kb
Host smart-38e80c13-e07c-4747-b08d-661426ae97f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742570588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3742570588
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1376554938
Short name T1310
Test name
Test status
Simulation time 104833402 ps
CPU time 0.85 seconds
Started Mar 07 02:45:38 PM PST 24
Finished Mar 07 02:45:39 PM PST 24
Peak memory 204900 kb
Host smart-17b05231-b36f-4a89-98b6-f958edc4ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376554938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1376554938
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.347197560
Short name T1125
Test name
Test status
Simulation time 170469680 ps
CPU time 1 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:16 PM PST 24
Peak memory 206712 kb
Host smart-fb303c42-873f-4076-8884-6bbd8812c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347197560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.347197560
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1590239769
Short name T784
Test name
Test status
Simulation time 37303797 ps
CPU time 0.84 seconds
Started Mar 07 02:45:41 PM PST 24
Finished Mar 07 02:45:42 PM PST 24
Peak memory 204888 kb
Host smart-734dc7dd-b132-49e8-9e42-ca9bb66a0519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590239769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1590239769
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.215366934
Short name T921
Test name
Test status
Simulation time 21477776 ps
CPU time 0.73 seconds
Started Mar 07 12:43:18 PM PST 24
Finished Mar 07 12:43:19 PM PST 24
Peak memory 205452 kb
Host smart-ca022ead-3954-46a1-9389-a8e682c35d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215366934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.215366934
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1052183116
Short name T10
Test name
Test status
Simulation time 1481086531 ps
CPU time 10.67 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:26 PM PST 24
Peak memory 235116 kb
Host smart-54c90a0d-faf8-499d-b4ca-e803f620ac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052183116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1052183116
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_upload.1077724057
Short name T1887
Test name
Test status
Simulation time 309169430 ps
CPU time 2.8 seconds
Started Mar 07 02:45:33 PM PST 24
Finished Mar 07 02:45:36 PM PST 24
Peak memory 216148 kb
Host smart-cae7b47c-81ee-4db8-a829-5d8e16fecd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077724057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1077724057
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1524350441
Short name T370
Test name
Test status
Simulation time 31431929 ps
CPU time 0.73 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:43:28 PM PST 24
Peak memory 205416 kb
Host smart-7873584d-807c-448a-b9c9-d0e5bfe8e073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524350441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1524350441
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.227036321
Short name T1424
Test name
Test status
Simulation time 12047963 ps
CPU time 0.7 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:45:47 PM PST 24
Peak memory 204396 kb
Host smart-207f2bfa-f942-42a0-9744-133080f64ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227036321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.227036321
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1718906475
Short name T1554
Test name
Test status
Simulation time 1180296806 ps
CPU time 4.1 seconds
Started Mar 07 12:43:16 PM PST 24
Finished Mar 07 12:43:20 PM PST 24
Peak memory 234108 kb
Host smart-f04683f6-f098-4ace-b370-1a56ccf334f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718906475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1718906475
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2613887271
Short name T1567
Test name
Test status
Simulation time 1736610258 ps
CPU time 6.39 seconds
Started Mar 07 02:45:43 PM PST 24
Finished Mar 07 02:45:50 PM PST 24
Peak memory 233120 kb
Host smart-ef0aaea5-af46-42fd-ad54-cc671cfdc1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613887271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2613887271
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1782573845
Short name T1682
Test name
Test status
Simulation time 25852107 ps
CPU time 0.85 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:29 PM PST 24
Peak memory 206224 kb
Host smart-3967a138-7886-48c9-ab12-d78d332fd1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782573845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1782573845
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3703071442
Short name T1061
Test name
Test status
Simulation time 179108386 ps
CPU time 0.8 seconds
Started Mar 07 02:45:39 PM PST 24
Finished Mar 07 02:45:40 PM PST 24
Peak memory 205496 kb
Host smart-c2c2a4ed-7a2f-4acf-8f96-4f3e0e75d365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703071442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3703071442
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2017804842
Short name T1458
Test name
Test status
Simulation time 7473098438 ps
CPU time 25.76 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:43:53 PM PST 24
Peak memory 233744 kb
Host smart-ec19ac72-3d9c-423b-b6dc-8d93f994a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017804842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2017804842
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.743486527
Short name T288
Test name
Test status
Simulation time 28197143600 ps
CPU time 130.2 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:47:56 PM PST 24
Peak memory 270304 kb
Host smart-8b86def5-0552-4ad9-b55c-ae2c02931978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743486527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.743486527
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1468795102
Short name T1808
Test name
Test status
Simulation time 1218113058 ps
CPU time 15.61 seconds
Started Mar 07 12:43:33 PM PST 24
Finished Mar 07 12:43:49 PM PST 24
Peak memory 232796 kb
Host smart-053848da-ec1b-4fbe-870f-186f4af3adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468795102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1468795102
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1557108331
Short name T1474
Test name
Test status
Simulation time 8958705490 ps
CPU time 122.98 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:47:49 PM PST 24
Peak memory 253036 kb
Host smart-ac8c4331-7f85-4fc7-b334-5167199dadb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557108331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1557108331
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2743104066
Short name T936
Test name
Test status
Simulation time 5082541339 ps
CPU time 56.17 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:46:43 PM PST 24
Peak memory 252552 kb
Host smart-e6304ea5-51b2-4881-8b61-977d3ad3ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743104066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2743104066
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.236500659
Short name T1506
Test name
Test status
Simulation time 14273582311 ps
CPU time 64.29 seconds
Started Mar 07 02:45:49 PM PST 24
Finished Mar 07 02:46:54 PM PST 24
Peak memory 236108 kb
Host smart-b60a0123-6179-4a2a-b7e0-73cc00f0126a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236500659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.236500659
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3918910337
Short name T967
Test name
Test status
Simulation time 569326626 ps
CPU time 9.43 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:38 PM PST 24
Peak memory 234104 kb
Host smart-c98eb239-c183-4533-8518-af61d976eced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918910337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3918910337
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1202079640
Short name T998
Test name
Test status
Simulation time 4134698999 ps
CPU time 6.43 seconds
Started Mar 07 02:45:47 PM PST 24
Finished Mar 07 02:45:54 PM PST 24
Peak memory 233064 kb
Host smart-ee854f36-ed9a-4a5d-b992-6396a57c69e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202079640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1202079640
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3472340832
Short name T1532
Test name
Test status
Simulation time 1516930323 ps
CPU time 9.02 seconds
Started Mar 07 12:43:17 PM PST 24
Finished Mar 07 12:43:26 PM PST 24
Peak memory 218584 kb
Host smart-e0426d79-fa14-4a20-8026-d4d840b44f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472340832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3472340832
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3192230014
Short name T1017
Test name
Test status
Simulation time 887416492 ps
CPU time 8.58 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:45:54 PM PST 24
Peak memory 223336 kb
Host smart-763119eb-0e97-4ea5-92f5-4a906bc41d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192230014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3192230014
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4162378622
Short name T1871
Test name
Test status
Simulation time 1475006163 ps
CPU time 10.31 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:43:38 PM PST 24
Peak memory 219404 kb
Host smart-c335d87c-e5cc-4b14-88e4-c8d8f8bb544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162378622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4162378622
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1640093875
Short name T272
Test name
Test status
Simulation time 37191953680 ps
CPU time 46.56 seconds
Started Mar 07 02:45:45 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 240340 kb
Host smart-087943ad-767a-4d36-993f-1b37320738b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640093875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1640093875
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2797877506
Short name T1280
Test name
Test status
Simulation time 27272091844 ps
CPU time 21.24 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:49 PM PST 24
Peak memory 227876 kb
Host smart-fd03d62e-e5aa-44a5-ac76-50c8a506f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797877506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2797877506
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1427793248
Short name T1477
Test name
Test status
Simulation time 548725335 ps
CPU time 3.26 seconds
Started Mar 07 02:45:44 PM PST 24
Finished Mar 07 02:45:47 PM PST 24
Peak memory 223848 kb
Host smart-13930c73-035e-4c93-a0bf-19b5952d0fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427793248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1427793248
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3091277000
Short name T567
Test name
Test status
Simulation time 16776814606 ps
CPU time 15.78 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:44 PM PST 24
Peak memory 248784 kb
Host smart-3270d03d-b028-4985-b542-c1e285fdadc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091277000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3091277000
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2641345649
Short name T736
Test name
Test status
Simulation time 282501482 ps
CPU time 3.44 seconds
Started Mar 07 02:45:47 PM PST 24
Finished Mar 07 02:45:50 PM PST 24
Peak memory 222000 kb
Host smart-db44632c-3b1b-4f89-a8eb-c12ebb79ad28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2641345649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2641345649
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2668802149
Short name T1102
Test name
Test status
Simulation time 392135380 ps
CPU time 3.94 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 222792 kb
Host smart-f58cf2f2-ac54-4181-b805-e07a70e54463
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2668802149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2668802149
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4286132407
Short name T1529
Test name
Test status
Simulation time 54320222 ps
CPU time 1.09 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:29 PM PST 24
Peak memory 206732 kb
Host smart-ce04f1f4-45a8-45dd-ae41-987a85b4950a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286132407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4286132407
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.993668667
Short name T838
Test name
Test status
Simulation time 278163681166 ps
CPU time 218.04 seconds
Started Mar 07 02:45:48 PM PST 24
Finished Mar 07 02:49:26 PM PST 24
Peak memory 252860 kb
Host smart-c287a042-c67f-432d-8aa1-7417f36bb351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993668667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.993668667
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1143541260
Short name T1823
Test name
Test status
Simulation time 4938857887 ps
CPU time 26.93 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:42 PM PST 24
Peak memory 216236 kb
Host smart-6d5ee5f7-4c8a-456b-8d39-45b21cbc5c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143541260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1143541260
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2588257491
Short name T1543
Test name
Test status
Simulation time 41358113887 ps
CPU time 37.69 seconds
Started Mar 07 02:45:44 PM PST 24
Finished Mar 07 02:46:22 PM PST 24
Peak memory 215896 kb
Host smart-f468f3d1-901b-4fab-af97-2adee7bf8bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588257491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2588257491
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.137317369
Short name T1547
Test name
Test status
Simulation time 13485259644 ps
CPU time 15.19 seconds
Started Mar 07 12:43:15 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 216184 kb
Host smart-0d7b5d90-8986-4edb-8d77-06d937d0ea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137317369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.137317369
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3073287005
Short name T1784
Test name
Test status
Simulation time 44670696529 ps
CPU time 21.14 seconds
Started Mar 07 02:45:38 PM PST 24
Finished Mar 07 02:46:00 PM PST 24
Peak memory 215844 kb
Host smart-5ab6705f-e36c-4585-8d5c-a372a5952278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073287005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3073287005
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3970838715
Short name T406
Test name
Test status
Simulation time 50378960 ps
CPU time 0.93 seconds
Started Mar 07 12:43:19 PM PST 24
Finished Mar 07 12:43:20 PM PST 24
Peak memory 206684 kb
Host smart-b68a40a1-0698-439e-a6cd-fbd9fe2c5cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970838715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3970838715
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.623439007
Short name T1684
Test name
Test status
Simulation time 56993965 ps
CPU time 1.48 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:45:47 PM PST 24
Peak memory 215764 kb
Host smart-83c86ebc-5c4a-4098-abe1-f6993ddb7f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623439007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.623439007
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3494462790
Short name T1266
Test name
Test status
Simulation time 12966573 ps
CPU time 0.7 seconds
Started Mar 07 02:45:51 PM PST 24
Finished Mar 07 02:45:52 PM PST 24
Peak memory 204904 kb
Host smart-ccb59587-ea83-4418-90f9-f36587ec5b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494462790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3494462790
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4214027677
Short name T1393
Test name
Test status
Simulation time 128933210 ps
CPU time 0.74 seconds
Started Mar 07 12:43:19 PM PST 24
Finished Mar 07 12:43:20 PM PST 24
Peak memory 205444 kb
Host smart-bb9ac379-3652-4237-814e-757017388bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214027677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4214027677
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2316928709
Short name T674
Test name
Test status
Simulation time 860291479 ps
CPU time 7.01 seconds
Started Mar 07 12:43:19 PM PST 24
Finished Mar 07 12:43:27 PM PST 24
Peak memory 238136 kb
Host smart-78942fff-b33a-42f2-a3ef-913013f85622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316928709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2316928709
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_upload.2421695643
Short name T832
Test name
Test status
Simulation time 3096306360 ps
CPU time 7.82 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:45:54 PM PST 24
Peak memory 232840 kb
Host smart-7447eddb-b038-4e69-81a1-778d5ac7a51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421695643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2421695643
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1787492795
Short name T1836
Test name
Test status
Simulation time 14542003 ps
CPU time 0.75 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 205168 kb
Host smart-33930f0a-7e81-4c0a-8908-e879abcda966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787492795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1787492795
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4076586280
Short name T1495
Test name
Test status
Simulation time 30852318 ps
CPU time 0.7 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:45:57 PM PST 24
Peak memory 204372 kb
Host smart-5b5b76d1-1356-4aa8-b42d-0bd8d85c642f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076586280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4076586280
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3596018609
Short name T558
Test name
Test status
Simulation time 116538430 ps
CPU time 2.45 seconds
Started Mar 07 02:45:49 PM PST 24
Finished Mar 07 02:45:52 PM PST 24
Peak memory 223720 kb
Host smart-fb499be8-417f-4ed8-bf5c-5de54394c863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596018609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3596018609
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.457729233
Short name T1053
Test name
Test status
Simulation time 293936072 ps
CPU time 3.39 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:34 PM PST 24
Peak memory 234008 kb
Host smart-b6846d6a-018f-4fb7-aa59-5d1fe1d7638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457729233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.457729233
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2133352520
Short name T1574
Test name
Test status
Simulation time 14025225 ps
CPU time 0.77 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:45:47 PM PST 24
Peak memory 205872 kb
Host smart-cbb55b02-3294-4df9-bc48-67af81707fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133352520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2133352520
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3460028701
Short name T550
Test name
Test status
Simulation time 15369691 ps
CPU time 0.75 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:43:28 PM PST 24
Peak memory 205272 kb
Host smart-84fa4b41-16e2-498d-8d48-175b65594845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460028701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3460028701
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1144066428
Short name T1052
Test name
Test status
Simulation time 10658727330 ps
CPU time 34.41 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:44:01 PM PST 24
Peak memory 249080 kb
Host smart-ae979733-2db5-4972-92c7-027e15c0a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144066428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1144066428
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3467957386
Short name T1173
Test name
Test status
Simulation time 204423726 ps
CPU time 3.64 seconds
Started Mar 07 02:45:49 PM PST 24
Finished Mar 07 02:45:53 PM PST 24
Peak memory 232060 kb
Host smart-a8c3984b-64cf-406f-bc06-ec252f221805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467957386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3467957386
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1067988940
Short name T184
Test name
Test status
Simulation time 29763860237 ps
CPU time 173.96 seconds
Started Mar 07 02:45:52 PM PST 24
Finished Mar 07 02:48:46 PM PST 24
Peak memory 252120 kb
Host smart-603c0192-159d-464a-beaf-7036b2b23849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067988940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1067988940
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2184456114
Short name T623
Test name
Test status
Simulation time 546468319750 ps
CPU time 333.54 seconds
Started Mar 07 12:43:32 PM PST 24
Finished Mar 07 12:49:06 PM PST 24
Peak memory 272864 kb
Host smart-73ff7cfb-929d-43d7-ad23-916533d6ad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184456114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2184456114
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2918223951
Short name T971
Test name
Test status
Simulation time 24660778408 ps
CPU time 72.13 seconds
Started Mar 07 02:45:55 PM PST 24
Finished Mar 07 02:47:08 PM PST 24
Peak memory 256916 kb
Host smart-a31dd718-aea5-408d-8776-cf164d71c7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918223951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2918223951
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.30634770
Short name T691
Test name
Test status
Simulation time 18443484023 ps
CPU time 68.09 seconds
Started Mar 07 12:43:32 PM PST 24
Finished Mar 07 12:44:40 PM PST 24
Peak memory 236476 kb
Host smart-bd31524c-81be-4952-a254-fdd43140bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30634770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.30634770
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2501747592
Short name T880
Test name
Test status
Simulation time 1375487684 ps
CPU time 14.21 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:45 PM PST 24
Peak memory 237832 kb
Host smart-63840a4c-2936-4242-a844-b83d5ce50095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501747592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2501747592
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.551921288
Short name T903
Test name
Test status
Simulation time 1191510017 ps
CPU time 11.29 seconds
Started Mar 07 02:45:47 PM PST 24
Finished Mar 07 02:45:59 PM PST 24
Peak memory 237968 kb
Host smart-f81b294e-a6a5-43a3-94b4-e53523dc2eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551921288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.551921288
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.83869477
Short name T1191
Test name
Test status
Simulation time 931892646 ps
CPU time 3.4 seconds
Started Mar 07 02:45:49 PM PST 24
Finished Mar 07 02:45:52 PM PST 24
Peak memory 216316 kb
Host smart-b5aacdce-43e6-444d-8caf-7ccbbeb02226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83869477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.83869477
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intercept.864933313
Short name T961
Test name
Test status
Simulation time 264678205 ps
CPU time 2.61 seconds
Started Mar 07 12:43:26 PM PST 24
Finished Mar 07 12:43:29 PM PST 24
Peak memory 235260 kb
Host smart-e3bc42ef-d4ad-4408-afe0-c40d991952e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864933313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.864933313
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1018302710
Short name T432
Test name
Test status
Simulation time 1969851705 ps
CPU time 4.93 seconds
Started Mar 07 02:45:47 PM PST 24
Finished Mar 07 02:45:53 PM PST 24
Peak memory 223844 kb
Host smart-d120b719-8f92-49af-8420-2e173a597d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018302710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1018302710
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.30038276
Short name T1652
Test name
Test status
Simulation time 3062743039 ps
CPU time 11.31 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:41 PM PST 24
Peak memory 244600 kb
Host smart-e9e82621-8807-4f1a-ab7c-48880179ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30038276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.30038276
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3892934317
Short name T1497
Test name
Test status
Simulation time 253335026 ps
CPU time 2.62 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:32 PM PST 24
Peak memory 232776 kb
Host smart-b351d534-3ffa-4c8c-bfb1-0db86d35e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892934317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3892934317
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4294308496
Short name T969
Test name
Test status
Simulation time 91620037 ps
CPU time 2.63 seconds
Started Mar 07 02:45:49 PM PST 24
Finished Mar 07 02:45:52 PM PST 24
Peak memory 232124 kb
Host smart-f13447f4-baf1-443a-b141-fd26be3bcf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294308496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4294308496
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1038855762
Short name T1545
Test name
Test status
Simulation time 14489785603 ps
CPU time 41.99 seconds
Started Mar 07 02:45:47 PM PST 24
Finished Mar 07 02:46:29 PM PST 24
Peak memory 233900 kb
Host smart-d1aca160-037b-4af0-b8b2-6619da73d763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038855762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1038855762
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3064415240
Short name T1746
Test name
Test status
Simulation time 643924685 ps
CPU time 5.48 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 217680 kb
Host smart-ba0912ec-cd57-40bf-86a8-ed6f9c69a7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064415240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3064415240
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.190071309
Short name T345
Test name
Test status
Simulation time 266276761 ps
CPU time 3.64 seconds
Started Mar 07 02:45:48 PM PST 24
Finished Mar 07 02:45:51 PM PST 24
Peak memory 222000 kb
Host smart-3d9c24e3-fa25-469a-9093-a4afd024a31f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=190071309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.190071309
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.917155600
Short name T1092
Test name
Test status
Simulation time 5602050646 ps
CPU time 6.46 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:35 PM PST 24
Peak memory 219036 kb
Host smart-11fbf64c-c348-4c95-ba41-902139df508b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=917155600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.917155600
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.186508399
Short name T1281
Test name
Test status
Simulation time 8794858332 ps
CPU time 113.66 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:45:23 PM PST 24
Peak memory 253136 kb
Host smart-753ff2fe-9d7f-4f63-a67c-9ad3c5ba3b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186508399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.186508399
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2820855969
Short name T278
Test name
Test status
Simulation time 93493913610 ps
CPU time 542.46 seconds
Started Mar 07 02:46:02 PM PST 24
Finished Mar 07 02:55:05 PM PST 24
Peak memory 266524 kb
Host smart-ab0bd701-d684-42e6-a96a-c8322286451c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820855969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2820855969
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2380351639
Short name T773
Test name
Test status
Simulation time 2396041571 ps
CPU time 16.58 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:45 PM PST 24
Peak memory 216252 kb
Host smart-aa3fea5a-52a8-4e89-bf37-02e41f43ad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380351639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2380351639
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3638590183
Short name T466
Test name
Test status
Simulation time 2030946815 ps
CPU time 15.82 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:46:02 PM PST 24
Peak memory 215812 kb
Host smart-574315d0-de39-42ed-81d9-779a0888244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638590183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3638590183
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1776297852
Short name T1387
Test name
Test status
Simulation time 1613341205 ps
CPU time 8.64 seconds
Started Mar 07 02:45:47 PM PST 24
Finished Mar 07 02:45:56 PM PST 24
Peak memory 215960 kb
Host smart-8b08be3c-9baf-45be-b5b3-23bdc0386ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776297852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1776297852
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.382063429
Short name T1855
Test name
Test status
Simulation time 5268865055 ps
CPU time 16.07 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:45 PM PST 24
Peak memory 216296 kb
Host smart-efde9f50-8860-4159-bbba-783d1550faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382063429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.382063429
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3574871400
Short name T1122
Test name
Test status
Simulation time 49165891 ps
CPU time 1.51 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 216176 kb
Host smart-5b1b9d64-0ef8-4c1e-905f-bbd70b84590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574871400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3574871400
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3870464843
Short name T1292
Test name
Test status
Simulation time 77653721 ps
CPU time 0.96 seconds
Started Mar 07 02:45:48 PM PST 24
Finished Mar 07 02:45:49 PM PST 24
Peak memory 205956 kb
Host smart-b41c484c-93cc-4719-b720-ff9728644bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870464843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3870464843
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1273356006
Short name T1206
Test name
Test status
Simulation time 42889336 ps
CPU time 0.76 seconds
Started Mar 07 12:43:25 PM PST 24
Finished Mar 07 12:43:26 PM PST 24
Peak memory 205488 kb
Host smart-14cfb96f-cc05-425b-a229-e88bd40aac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273356006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1273356006
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.668710124
Short name T1613
Test name
Test status
Simulation time 64608356 ps
CPU time 0.76 seconds
Started Mar 07 02:45:46 PM PST 24
Finished Mar 07 02:45:46 PM PST 24
Peak memory 204864 kb
Host smart-a1aae940-24bb-41b1-91ac-8412694aaa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668710124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.668710124
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2386686478
Short name T1347
Test name
Test status
Simulation time 49883687056 ps
CPU time 30.33 seconds
Started Mar 07 02:45:51 PM PST 24
Finished Mar 07 02:46:21 PM PST 24
Peak memory 218172 kb
Host smart-e0512048-c6be-4fa9-b5be-cbcbf83abe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386686478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2386686478
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_upload.3447963155
Short name T739
Test name
Test status
Simulation time 7622434701 ps
CPU time 7.27 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:43:34 PM PST 24
Peak memory 233588 kb
Host smart-2cbff5fb-6a30-43ba-bd09-6bff044c40f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447963155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3447963155
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1419579022
Short name T467
Test name
Test status
Simulation time 37202410 ps
CPU time 0.68 seconds
Started Mar 07 12:43:26 PM PST 24
Finished Mar 07 12:43:27 PM PST 24
Peak memory 205052 kb
Host smart-b139baf7-85b0-4ff3-ba4a-1ccf107d47d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419579022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1419579022
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.842357327
Short name T766
Test name
Test status
Simulation time 18081788 ps
CPU time 0.71 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:45:57 PM PST 24
Peak memory 204844 kb
Host smart-b8cf1ec0-4d52-4a71-a14c-e65a340474c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842357327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.842357327
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2561272256
Short name T537
Test name
Test status
Simulation time 101922472 ps
CPU time 2.73 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:45:59 PM PST 24
Peak memory 223820 kb
Host smart-ce505216-d8b5-4f5e-b1c6-27c2bc5fae98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561272256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2561272256
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3619815517
Short name T228
Test name
Test status
Simulation time 1069608862 ps
CPU time 5.14 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:35 PM PST 24
Peak memory 234588 kb
Host smart-d554a21c-c6dc-440d-a2a3-ad89a40993bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619815517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3619815517
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2514785267
Short name T1154
Test name
Test status
Simulation time 30255703 ps
CPU time 0.77 seconds
Started Mar 07 02:45:53 PM PST 24
Finished Mar 07 02:45:54 PM PST 24
Peak memory 204500 kb
Host smart-c6251393-4e0d-4bfc-bf60-fd6d24b5ca3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514785267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2514785267
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3438096820
Short name T1463
Test name
Test status
Simulation time 181368153 ps
CPU time 0.76 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 205292 kb
Host smart-247b52e4-89e3-499f-8bc3-770c23add4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438096820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3438096820
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1561876015
Short name T1279
Test name
Test status
Simulation time 53508301833 ps
CPU time 239.61 seconds
Started Mar 07 02:46:03 PM PST 24
Finished Mar 07 02:50:04 PM PST 24
Peak memory 252212 kb
Host smart-d0618cf6-13e4-4eb5-8244-4dcfa8dceccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561876015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1561876015
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2716721985
Short name T203
Test name
Test status
Simulation time 146608539489 ps
CPU time 166.09 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:46:13 PM PST 24
Peak memory 248668 kb
Host smart-ac45d460-ead5-4284-a901-8a42f8410ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716721985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2716721985
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1739283482
Short name T59
Test name
Test status
Simulation time 12395586979 ps
CPU time 105.27 seconds
Started Mar 07 02:46:03 PM PST 24
Finished Mar 07 02:47:49 PM PST 24
Peak memory 248708 kb
Host smart-3006fd3d-4830-441a-923c-f8aea9cb29bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739283482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1739283482
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2897484681
Short name T1905
Test name
Test status
Simulation time 15017242335 ps
CPU time 55.87 seconds
Started Mar 07 12:43:31 PM PST 24
Finished Mar 07 12:44:27 PM PST 24
Peak memory 243844 kb
Host smart-ff4d0709-a2d0-4f6f-9324-252d00ab0201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897484681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2897484681
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2662462764
Short name T1486
Test name
Test status
Simulation time 6127814617 ps
CPU time 23.38 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:52 PM PST 24
Peak memory 224584 kb
Host smart-2f424733-c8f6-417b-90ea-bb14107b271a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662462764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2662462764
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3262248411
Short name T1479
Test name
Test status
Simulation time 4639073646 ps
CPU time 89.98 seconds
Started Mar 07 02:45:54 PM PST 24
Finished Mar 07 02:47:25 PM PST 24
Peak memory 256264 kb
Host smart-6bb38fc5-14f4-43aa-803d-44224206d347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262248411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3262248411
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1326431982
Short name T1679
Test name
Test status
Simulation time 23828362684 ps
CPU time 34.93 seconds
Started Mar 07 02:45:55 PM PST 24
Finished Mar 07 02:46:31 PM PST 24
Peak memory 239944 kb
Host smart-b93436c8-b6d0-47e0-99b0-3a482d9829f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326431982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1326431982
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.921298899
Short name T768
Test name
Test status
Simulation time 17675277698 ps
CPU time 44.42 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:44:11 PM PST 24
Peak memory 236120 kb
Host smart-0021b42b-3664-4b91-9745-2ea1b0e980d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921298899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.921298899
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2600196255
Short name T111
Test name
Test status
Simulation time 760582207 ps
CPU time 3.12 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 218360 kb
Host smart-81a5e658-f59c-445b-bb16-2d9947cc7234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600196255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2600196255
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3294848819
Short name T1057
Test name
Test status
Simulation time 3086395080 ps
CPU time 5.51 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:46:02 PM PST 24
Peak memory 220296 kb
Host smart-18dc8f01-9e2c-455d-b266-68a770d83bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294848819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3294848819
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.672406315
Short name T988
Test name
Test status
Simulation time 2170270304 ps
CPU time 8.99 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:46:05 PM PST 24
Peak memory 232072 kb
Host smart-b439884d-1a3d-4ade-948a-c263f9c684f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672406315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.672406315
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.680479867
Short name T646
Test name
Test status
Simulation time 202445480 ps
CPU time 4.02 seconds
Started Mar 07 12:43:33 PM PST 24
Finished Mar 07 12:43:37 PM PST 24
Peak memory 224392 kb
Host smart-551fb63c-539b-48fb-a40a-15f99c63ec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680479867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.680479867
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.384281502
Short name T934
Test name
Test status
Simulation time 391493338 ps
CPU time 2.91 seconds
Started Mar 07 02:45:57 PM PST 24
Finished Mar 07 02:46:00 PM PST 24
Peak memory 233848 kb
Host smart-a23d44e7-f9b2-4eb1-afd0-a3b352005f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384281502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.384281502
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4291226657
Short name T1220
Test name
Test status
Simulation time 1300832908 ps
CPU time 5.4 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:35 PM PST 24
Peak memory 232864 kb
Host smart-246db2e4-4185-4ef3-8028-e4bb5ad9d356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291226657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4291226657
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1569939294
Short name T1654
Test name
Test status
Simulation time 3984606963 ps
CPU time 4.84 seconds
Started Mar 07 02:46:02 PM PST 24
Finished Mar 07 02:46:07 PM PST 24
Peak memory 232520 kb
Host smart-07ff10f0-93e3-4c98-87cd-a360df5212ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569939294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1569939294
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.957741459
Short name T1786
Test name
Test status
Simulation time 11144361599 ps
CPU time 29.43 seconds
Started Mar 07 12:44:02 PM PST 24
Finished Mar 07 12:44:32 PM PST 24
Peak memory 228932 kb
Host smart-ab83aeca-1181-435b-af3e-213aa50baadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957741459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.957741459
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1207690283
Short name T144
Test name
Test status
Simulation time 5775908194 ps
CPU time 5.33 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:35 PM PST 24
Peak memory 218552 kb
Host smart-62490991-f779-452d-bebd-11034146a0f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1207690283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1207690283
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.269497574
Short name T145
Test name
Test status
Simulation time 152052631 ps
CPU time 3.19 seconds
Started Mar 07 02:45:54 PM PST 24
Finished Mar 07 02:45:58 PM PST 24
Peak memory 219628 kb
Host smart-989ddcdf-7726-4b65-922a-c76dde04ae53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=269497574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.269497574
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1952660800
Short name T16
Test name
Test status
Simulation time 58918464 ps
CPU time 0.91 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 206288 kb
Host smart-4db0e8a5-16fe-4d43-b732-0e3f4e5d1724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952660800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1952660800
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2250814406
Short name T161
Test name
Test status
Simulation time 10671095388 ps
CPU time 110.66 seconds
Started Mar 07 02:45:53 PM PST 24
Finished Mar 07 02:47:44 PM PST 24
Peak memory 252728 kb
Host smart-1bebace8-628c-4c04-84fa-10c85854f876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250814406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2250814406
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2403157820
Short name T317
Test name
Test status
Simulation time 2920485773 ps
CPU time 17.77 seconds
Started Mar 07 12:43:26 PM PST 24
Finished Mar 07 12:43:44 PM PST 24
Peak memory 216212 kb
Host smart-9cb9fa88-ef2b-4a79-b023-f3a97f713de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403157820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2403157820
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2943823587
Short name T1314
Test name
Test status
Simulation time 2492463488 ps
CPU time 16.44 seconds
Started Mar 07 02:45:53 PM PST 24
Finished Mar 07 02:46:10 PM PST 24
Peak memory 215912 kb
Host smart-8a0814f7-a17b-4c33-afbc-9d5879742690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943823587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2943823587
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1483806286
Short name T1596
Test name
Test status
Simulation time 3956988857 ps
CPU time 5.86 seconds
Started Mar 07 02:45:55 PM PST 24
Finished Mar 07 02:46:01 PM PST 24
Peak memory 215732 kb
Host smart-32ad3a3e-8cef-4dd1-b0ad-3bcf87f78208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483806286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1483806286
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3943848099
Short name T1857
Test name
Test status
Simulation time 257468434 ps
CPU time 1.11 seconds
Started Mar 07 12:43:25 PM PST 24
Finished Mar 07 12:43:26 PM PST 24
Peak memory 207492 kb
Host smart-76795148-182c-444d-933c-7cdee6d146d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943848099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3943848099
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.185934317
Short name T1797
Test name
Test status
Simulation time 1966338885 ps
CPU time 3.95 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:34 PM PST 24
Peak memory 216308 kb
Host smart-f4d60add-be6a-4913-8cdd-bfdd7046bbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185934317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.185934317
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.194373882
Short name T523
Test name
Test status
Simulation time 424244253 ps
CPU time 2.49 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:45:59 PM PST 24
Peak memory 215728 kb
Host smart-90e16a9e-869f-4a04-9e20-bffcc7377146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194373882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.194373882
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2262667723
Short name T1858
Test name
Test status
Simulation time 115829975 ps
CPU time 1.03 seconds
Started Mar 07 02:45:59 PM PST 24
Finished Mar 07 02:46:00 PM PST 24
Peak memory 205912 kb
Host smart-84453a99-7148-4f96-8e3f-06b2e8bbb331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262667723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2262667723
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2867677180
Short name T97
Test name
Test status
Simulation time 23909336 ps
CPU time 0.74 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 205448 kb
Host smart-a47b8101-47d6-4b5a-b2c0-48183b0b44e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867677180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2867677180
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1140375725
Short name T1189
Test name
Test status
Simulation time 3345827849 ps
CPU time 16.88 seconds
Started Mar 07 02:46:00 PM PST 24
Finished Mar 07 02:46:17 PM PST 24
Peak memory 234160 kb
Host smart-d9ed3794-9a39-4ccb-b8c9-3551e514ff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140375725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1140375725
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_upload.1864652407
Short name T1275
Test name
Test status
Simulation time 2559489765 ps
CPU time 13.04 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:43 PM PST 24
Peak memory 218620 kb
Host smart-1327ff2e-49a0-4b23-b135-337fe96b59db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864652407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1864652407
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.326383170
Short name T1500
Test name
Test status
Simulation time 11730675 ps
CPU time 0.7 seconds
Started Mar 07 12:43:36 PM PST 24
Finished Mar 07 12:43:37 PM PST 24
Peak memory 205088 kb
Host smart-dc4a0055-7792-4add-a9e0-fb8892b660dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326383170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.326383170
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3968294140
Short name T1136
Test name
Test status
Simulation time 26161677 ps
CPU time 0.66 seconds
Started Mar 07 02:46:04 PM PST 24
Finished Mar 07 02:46:06 PM PST 24
Peak memory 204324 kb
Host smart-28da2f89-c167-4463-8fc5-7b2d7fdada78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968294140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3968294140
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.183213153
Short name T53
Test name
Test status
Simulation time 2973499010 ps
CPU time 4.08 seconds
Started Mar 07 02:45:55 PM PST 24
Finished Mar 07 02:46:00 PM PST 24
Peak memory 233256 kb
Host smart-82aa901a-bd3a-4161-b5df-800498ce184b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183213153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.183213153
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2202813753
Short name T1493
Test name
Test status
Simulation time 399284948 ps
CPU time 2.2 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:43:29 PM PST 24
Peak memory 216464 kb
Host smart-42d8fd8e-ed49-461d-86c7-ef9a9f284d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202813753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2202813753
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2451002215
Short name T1509
Test name
Test status
Simulation time 19224804 ps
CPU time 0.77 seconds
Started Mar 07 02:45:57 PM PST 24
Finished Mar 07 02:45:58 PM PST 24
Peak memory 204452 kb
Host smart-ca4122b7-433e-4fc9-82f3-c0c8d644b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451002215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2451002215
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.471963166
Short name T460
Test name
Test status
Simulation time 29492660 ps
CPU time 0.76 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 205296 kb
Host smart-6232d903-9616-47a3-931d-1256de1b6d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471963166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.471963166
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.309347118
Short name T290
Test name
Test status
Simulation time 31163895733 ps
CPU time 53.45 seconds
Started Mar 07 12:43:42 PM PST 24
Finished Mar 07 12:44:36 PM PST 24
Peak memory 249180 kb
Host smart-7f896074-1942-47e7-8500-d2bccbbc1ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309347118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.309347118
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.636525052
Short name T451
Test name
Test status
Simulation time 3698698701 ps
CPU time 10.22 seconds
Started Mar 07 02:45:53 PM PST 24
Finished Mar 07 02:46:03 PM PST 24
Peak memory 237620 kb
Host smart-3cff36f5-6594-4168-ad38-3cd2e9f32d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636525052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.636525052
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1366244263
Short name T481
Test name
Test status
Simulation time 14587728051 ps
CPU time 73.58 seconds
Started Mar 07 02:45:58 PM PST 24
Finished Mar 07 02:47:12 PM PST 24
Peak memory 254696 kb
Host smart-ca95adb4-823c-45d1-b1a8-c14069ac28bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366244263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1366244263
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1437367985
Short name T500
Test name
Test status
Simulation time 3930045610 ps
CPU time 75.33 seconds
Started Mar 07 12:43:35 PM PST 24
Finished Mar 07 12:44:51 PM PST 24
Peak memory 251604 kb
Host smart-2fb31108-0a10-4b41-a048-2f3eb646b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437367985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1437367985
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1970931363
Short name T886
Test name
Test status
Simulation time 25784337320 ps
CPU time 211.06 seconds
Started Mar 07 12:43:36 PM PST 24
Finished Mar 07 12:47:08 PM PST 24
Peak memory 269484 kb
Host smart-e76b2c93-a819-46aa-bb16-eaf04926a65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970931363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1970931363
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3257370995
Short name T275
Test name
Test status
Simulation time 58306241289 ps
CPU time 216.92 seconds
Started Mar 07 02:46:04 PM PST 24
Finished Mar 07 02:49:42 PM PST 24
Peak memory 253404 kb
Host smart-d1383d8d-cc45-424f-8b36-cdf907ba6827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257370995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3257370995
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3545393554
Short name T1077
Test name
Test status
Simulation time 903740971 ps
CPU time 11.98 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:46:08 PM PST 24
Peak memory 246252 kb
Host smart-6d75f909-b207-45e0-b41f-6b2ea24bed83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545393554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3545393554
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2362660367
Short name T188
Test name
Test status
Simulation time 2555735816 ps
CPU time 7.53 seconds
Started Mar 07 02:45:59 PM PST 24
Finished Mar 07 02:46:07 PM PST 24
Peak memory 232720 kb
Host smart-1577a5b0-4184-48b7-a8d8-b56dd978f39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362660367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2362660367
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2387316676
Short name T1792
Test name
Test status
Simulation time 1982046500 ps
CPU time 7.27 seconds
Started Mar 07 12:43:29 PM PST 24
Finished Mar 07 12:43:36 PM PST 24
Peak memory 224396 kb
Host smart-6f9a3abe-62ef-469f-9d7c-3901e348b29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387316676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2387316676
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2522934179
Short name T227
Test name
Test status
Simulation time 2456165667 ps
CPU time 7.49 seconds
Started Mar 07 02:45:55 PM PST 24
Finished Mar 07 02:46:03 PM PST 24
Peak memory 240304 kb
Host smart-03f183b7-2504-4c14-a63a-b0a373625847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522934179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2522934179
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.405540436
Short name T1048
Test name
Test status
Simulation time 577474286 ps
CPU time 2.73 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 216720 kb
Host smart-f75426d0-834d-4cd3-ba62-80f22fb1632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405540436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.405540436
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2316067400
Short name T780
Test name
Test status
Simulation time 2331024477 ps
CPU time 7.88 seconds
Started Mar 07 02:45:55 PM PST 24
Finished Mar 07 02:46:03 PM PST 24
Peak memory 233884 kb
Host smart-1d4f5201-951c-4ce2-9ad6-3d38a35bea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316067400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2316067400
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2697088855
Short name T1664
Test name
Test status
Simulation time 118046413 ps
CPU time 3.13 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:32 PM PST 24
Peak memory 224416 kb
Host smart-860804f7-2855-4260-8c99-5743e0e8dd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697088855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2697088855
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2805289803
Short name T1877
Test name
Test status
Simulation time 2096376799 ps
CPU time 3.73 seconds
Started Mar 07 12:43:28 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 224440 kb
Host smart-42f25138-906d-4900-8c76-2d6119f17631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805289803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2805289803
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4257740141
Short name T1461
Test name
Test status
Simulation time 50460487955 ps
CPU time 29.29 seconds
Started Mar 07 02:46:02 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 223812 kb
Host smart-29af7adc-fdba-4230-bb84-325ee032de8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257740141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4257740141
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2911078993
Short name T754
Test name
Test status
Simulation time 668213741 ps
CPU time 4.43 seconds
Started Mar 07 12:43:50 PM PST 24
Finished Mar 07 12:43:55 PM PST 24
Peak memory 217012 kb
Host smart-c97230ce-827c-4942-b02f-612f912586fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2911078993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2911078993
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.850592992
Short name T394
Test name
Test status
Simulation time 3010027355 ps
CPU time 5.38 seconds
Started Mar 07 02:45:53 PM PST 24
Finished Mar 07 02:45:59 PM PST 24
Peak memory 219696 kb
Host smart-18a0d56d-3183-455f-8b6c-73ba95f6e600
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=850592992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.850592992
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1021626918
Short name T1160
Test name
Test status
Simulation time 22692207840 ps
CPU time 72.72 seconds
Started Mar 07 12:43:35 PM PST 24
Finished Mar 07 12:44:49 PM PST 24
Peak memory 250736 kb
Host smart-1cbdec5a-3f7c-4599-87fa-5915ab8b0bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021626918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1021626918
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4291504504
Short name T525
Test name
Test status
Simulation time 67336226 ps
CPU time 1.23 seconds
Started Mar 07 02:46:04 PM PST 24
Finished Mar 07 02:46:05 PM PST 24
Peak memory 206240 kb
Host smart-46e09dbb-0119-4489-bbbc-aa908a5e28f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291504504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4291504504
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1752037884
Short name T453
Test name
Test status
Simulation time 4036808178 ps
CPU time 6 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:36 PM PST 24
Peak memory 216204 kb
Host smart-8b0c853f-fc97-4b32-9914-f659ff5156a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752037884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1752037884
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1896778430
Short name T425
Test name
Test status
Simulation time 2279006791 ps
CPU time 17.78 seconds
Started Mar 07 02:45:54 PM PST 24
Finished Mar 07 02:46:12 PM PST 24
Peak memory 215996 kb
Host smart-d976eb89-43c1-4cdd-9c46-f6fa09ebddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896778430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1896778430
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3785928906
Short name T756
Test name
Test status
Simulation time 7585244928 ps
CPU time 10.36 seconds
Started Mar 07 02:46:03 PM PST 24
Finished Mar 07 02:46:14 PM PST 24
Peak memory 215716 kb
Host smart-cdbfc417-3713-4ff6-8415-4e9df72dc058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785928906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3785928906
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.40250243
Short name T1403
Test name
Test status
Simulation time 6740443808 ps
CPU time 10.73 seconds
Started Mar 07 12:43:30 PM PST 24
Finished Mar 07 12:43:41 PM PST 24
Peak memory 216156 kb
Host smart-cb7e9a6d-9061-469b-96b6-c6a6e671a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40250243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.40250243
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1065078913
Short name T395
Test name
Test status
Simulation time 46070328 ps
CPU time 2.69 seconds
Started Mar 07 12:43:27 PM PST 24
Finished Mar 07 12:43:30 PM PST 24
Peak memory 216216 kb
Host smart-7bc9205d-d359-4a1e-89ee-8423b5051464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065078913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1065078913
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2245202707
Short name T1415
Test name
Test status
Simulation time 11157260 ps
CPU time 0.79 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:45:57 PM PST 24
Peak memory 204892 kb
Host smart-62fd23e8-b548-4c7b-bc54-9a6cd2f8802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245202707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2245202707
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2078246893
Short name T682
Test name
Test status
Simulation time 87453053 ps
CPU time 0.92 seconds
Started Mar 07 12:43:33 PM PST 24
Finished Mar 07 12:43:34 PM PST 24
Peak memory 205472 kb
Host smart-3ca5fe2c-b6c0-438d-8c29-2f969ef702f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078246893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2078246893
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2309754666
Short name T779
Test name
Test status
Simulation time 45560993 ps
CPU time 0.81 seconds
Started Mar 07 02:45:56 PM PST 24
Finished Mar 07 02:45:58 PM PST 24
Peak memory 204900 kb
Host smart-6c7427d4-5178-4ee7-a273-de063568133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309754666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2309754666
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1807123683
Short name T1893
Test name
Test status
Simulation time 1333789580 ps
CPU time 9.4 seconds
Started Mar 07 12:43:32 PM PST 24
Finished Mar 07 12:43:42 PM PST 24
Peak memory 218064 kb
Host smart-11fb92ee-3c79-4fc4-847f-9effa19afdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807123683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1807123683
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_upload.1915513690
Short name T421
Test name
Test status
Simulation time 2001986854 ps
CPU time 4.79 seconds
Started Mar 07 02:45:53 PM PST 24
Finished Mar 07 02:45:58 PM PST 24
Peak memory 218520 kb
Host smart-b55cea89-e04b-4f40-9820-fb6cd20c9b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915513690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1915513690
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1055487430
Short name T1628
Test name
Test status
Simulation time 14530418 ps
CPU time 0.71 seconds
Started Mar 07 02:45:59 PM PST 24
Finished Mar 07 02:46:01 PM PST 24
Peak memory 204464 kb
Host smart-7aa271d1-e444-4bcf-83db-c33d0a2ef902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055487430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1055487430
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.624274096
Short name T1307
Test name
Test status
Simulation time 30903689 ps
CPU time 0.86 seconds
Started Mar 07 12:43:50 PM PST 24
Finished Mar 07 12:43:52 PM PST 24
Peak memory 205048 kb
Host smart-c4e11f96-cbce-442a-94bd-02cda46dd1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624274096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.624274096
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2080853465
Short name T393
Test name
Test status
Simulation time 304853578 ps
CPU time 3.81 seconds
Started Mar 07 02:46:02 PM PST 24
Finished Mar 07 02:46:06 PM PST 24
Peak memory 223840 kb
Host smart-7a4f7b21-50cd-4498-aed8-c3639548a4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080853465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2080853465
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3170578893
Short name T471
Test name
Test status
Simulation time 390906032 ps
CPU time 3.48 seconds
Started Mar 07 12:43:34 PM PST 24
Finished Mar 07 12:43:38 PM PST 24
Peak memory 217808 kb
Host smart-4696ecc9-97a2-4114-a476-18a0cc3429dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170578893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3170578893
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1156165187
Short name T1674
Test name
Test status
Simulation time 24052835 ps
CPU time 0.74 seconds
Started Mar 07 12:43:39 PM PST 24
Finished Mar 07 12:43:40 PM PST 24
Peak memory 205228 kb
Host smart-cc6a5f8e-a7e3-4099-a149-e0afa257c704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156165187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1156165187
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.366774939
Short name T1878
Test name
Test status
Simulation time 156199048 ps
CPU time 0.75 seconds
Started Mar 07 02:46:04 PM PST 24
Finished Mar 07 02:46:06 PM PST 24
Peak memory 205464 kb
Host smart-bf04cb6e-df53-4b29-864a-693e42ce1ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366774939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.366774939
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1407898180
Short name T1553
Test name
Test status
Simulation time 5191521402 ps
CPU time 23.76 seconds
Started Mar 07 02:46:02 PM PST 24
Finished Mar 07 02:46:26 PM PST 24
Peak memory 248556 kb
Host smart-ab7b84ed-e300-4c82-977f-02fe48eaa63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407898180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1407898180
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3801944564
Short name T837
Test name
Test status
Simulation time 39369885080 ps
CPU time 176.48 seconds
Started Mar 07 12:43:37 PM PST 24
Finished Mar 07 12:46:34 PM PST 24
Peak memory 236196 kb
Host smart-f384d35d-7f91-45fa-807d-2eec309be590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801944564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3801944564
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1242950326
Short name T22
Test name
Test status
Simulation time 129033511028 ps
CPU time 240.91 seconds
Started Mar 07 02:46:03 PM PST 24
Finished Mar 07 02:50:04 PM PST 24
Peak memory 251324 kb
Host smart-714bbc07-e2a3-4750-80c9-1300a76c12e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242950326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1242950326
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2528915146
Short name T1251
Test name
Test status
Simulation time 255656634511 ps
CPU time 379.93 seconds
Started Mar 07 12:43:50 PM PST 24
Finished Mar 07 12:50:11 PM PST 24
Peak memory 272916 kb
Host smart-4aeb15d7-9b2f-44ec-b00d-e2ef9e1648f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528915146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2528915146
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2341842822
Short name T1198
Test name
Test status
Simulation time 3126180233 ps
CPU time 46.37 seconds
Started Mar 07 12:43:35 PM PST 24
Finished Mar 07 12:44:22 PM PST 24
Peak memory 240764 kb
Host smart-6a79144c-13ec-40a0-8426-ca1f1b96049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341842822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2341842822
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.938224590
Short name T893
Test name
Test status
Simulation time 57594905693 ps
CPU time 273.81 seconds
Started Mar 07 02:46:05 PM PST 24
Finished Mar 07 02:50:39 PM PST 24
Peak memory 248620 kb
Host smart-4c69957d-8afc-472f-85aa-9384ab802c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938224590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.938224590
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3363588632
Short name T1073
Test name
Test status
Simulation time 422307368 ps
CPU time 11.05 seconds
Started Mar 07 12:43:36 PM PST 24
Finished Mar 07 12:43:48 PM PST 24
Peak memory 236552 kb
Host smart-879c72cf-26a0-4513-b0eb-4b0062c37295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363588632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3363588632
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.597833630
Short name T1660
Test name
Test status
Simulation time 3283417291 ps
CPU time 15.11 seconds
Started Mar 07 02:46:04 PM PST 24
Finished Mar 07 02:46:20 PM PST 24
Peak memory 233400 kb
Host smart-6d0acbad-bbd1-4ac7-add8-83f98f7acc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597833630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.597833630
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3728733714
Short name T824
Test name
Test status
Simulation time 1627954294 ps
CPU time 4.41 seconds
Started Mar 07 12:43:42 PM PST 24
Finished Mar 07 12:43:46 PM PST 24
Peak memory 218600 kb
Host smart-0c58e5f5-21dc-4666-a602-312388f68740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728733714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3728733714
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intercept.658514277
Short name T1513
Test name
Test status
Simulation time 1004587793 ps
CPU time 4 seconds
Started Mar 07 02:46:04 PM PST 24
Finished Mar 07 02:46:08 PM PST 24
Peak memory 223816 kb
Host smart-b6af763e-e6a9-4a66-b478-b26563f25048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658514277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.658514277
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3727728955
Short name T1859
Test name
Test status
Simulation time 992590493 ps
CPU time 8.36 seconds
Started Mar 07 02:46:01 PM PST 24
Finished Mar 07 02:46:10 PM PST 24
Peak memory 223884 kb
Host smart-7c8a058e-3bba-40d5-a773-28b1d0cf659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727728955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3727728955
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.635746678
Short name T799
Test name
Test status
Simulation time 3182536435 ps
CPU time 9.13 seconds
Started Mar 07 12:43:39 PM PST 24
Finished Mar 07 12:43:48 PM PST 24
Peak memory 224384 kb
Host smart-a3c688ca-51f7-4ec7-bf91-a8094cb64ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635746678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.635746678
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3301528708
Short name T867
Test name
Test status
Simulation time 331404878 ps
CPU time 4.47 seconds
Started Mar 07 12:43:34 PM PST 24
Finished Mar 07 12:43:39 PM PST 24
Peak memory 218624 kb
Host smart-bd356ef0-467e-48a9-97b5-d8116fd5cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301528708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3301528708
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3330013949
Short name T656
Test name
Test status
Simulation time 84615903 ps
CPU time 3.18 seconds
Started Mar 07 02:46:03 PM PST 24
Finished Mar 07 02:46:07 PM PST 24
Peak memory 232460 kb
Host smart-a57eaecd-1a95-40d2-bf1b-aa3883beab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330013949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3330013949
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1277566667
Short name T211
Test name
Test status
Simulation time 2441385068 ps
CPU time 6.82 seconds
Started Mar 07 12:43:34 PM PST 24
Finished Mar 07 12:43:41 PM PST 24
Peak memory 218384 kb
Host smart-a745e885-4004-4382-be98-48545bdd4352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277566667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1277566667
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1515519426
Short name T3
Test name
Test status
Simulation time 35502757303 ps
CPU time 14.7 seconds
Started Mar 07 02:46:03 PM PST 24
Finished Mar 07 02:46:17 PM PST 24
Peak memory 232528 kb
Host smart-52720b36-e918-40b5-95ac-c76627a8f8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515519426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1515519426
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1904500177
Short name T518
Test name
Test status
Simulation time 130207051 ps
CPU time 4.1 seconds
Started Mar 07 02:46:00 PM PST 24
Finished Mar 07 02:46:05 PM PST 24
Peak memory 222048 kb
Host smart-ac6e393d-df55-48d2-8bc5-e113d80a5ec9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1904500177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1904500177
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3826843157
Short name T499
Test name
Test status
Simulation time 2944008061 ps
CPU time 4.31 seconds
Started Mar 07 12:43:42 PM PST 24
Finished Mar 07 12:43:47 PM PST 24
Peak memory 220464 kb
Host smart-b4698007-b04a-4d20-a48b-43369cf1f9aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3826843157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3826843157
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4262622020
Short name T1515
Test name
Test status
Simulation time 8727825234 ps
CPU time 53.82 seconds
Started Mar 07 02:46:05 PM PST 24
Finished Mar 07 02:46:59 PM PST 24
Peak memory 232224 kb
Host smart-d1c3ade0-3a74-479b-930b-d5c1d4102b85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262622020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4262622020
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.285979686
Short name T626
Test name
Test status
Simulation time 4015659891 ps
CPU time 39.35 seconds
Started Mar 07 02:46:03 PM PST 24
Finished Mar 07 02:46:42 PM PST 24
Peak memory 215780 kb
Host smart-68cee396-9c4a-42a0-b79e-fd4182ed84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285979686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.285979686
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2883011555
Short name T1593
Test name
Test status
Simulation time 7455117653 ps
CPU time 18.81 seconds
Started Mar 07 12:43:37 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 216296 kb
Host smart-e3223a17-65c2-4442-806b-53f2db6ac21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883011555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2883011555
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.174894292
Short name T573
Test name
Test status
Simulation time 533318084 ps
CPU time 2 seconds
Started Mar 07 02:46:02 PM PST 24
Finished Mar 07 02:46:04 PM PST 24
Peak memory 206048 kb
Host smart-17254146-81fa-4439-b37b-91c393376643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174894292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.174894292
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4064890183
Short name T485
Test name
Test status
Simulation time 12087436693 ps
CPU time 19.45 seconds
Started Mar 07 12:43:36 PM PST 24
Finished Mar 07 12:43:56 PM PST 24
Peak memory 216244 kb
Host smart-96f7a5dd-f9fa-4447-a9f4-f213b8162032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064890183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4064890183
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.228406256
Short name T1738
Test name
Test status
Simulation time 78483838 ps
CPU time 1.9 seconds
Started Mar 07 02:46:01 PM PST 24
Finished Mar 07 02:46:03 PM PST 24
Peak memory 216020 kb
Host smart-badf2321-1316-4b02-8637-21a28bcb17b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228406256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.228406256
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2945171715
Short name T850
Test name
Test status
Simulation time 152744242 ps
CPU time 2.21 seconds
Started Mar 07 12:43:33 PM PST 24
Finished Mar 07 12:43:36 PM PST 24
Peak memory 216188 kb
Host smart-edd477f8-dc8e-4dd5-9d58-957423435636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945171715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2945171715
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2215690408
Short name T1078
Test name
Test status
Simulation time 341434199 ps
CPU time 0.97 seconds
Started Mar 07 02:46:02 PM PST 24
Finished Mar 07 02:46:03 PM PST 24
Peak memory 205048 kb
Host smart-3e9e2c27-53e9-4216-95ea-d3714784cad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215690408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2215690408
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3459567886
Short name T1678
Test name
Test status
Simulation time 28344792 ps
CPU time 0.78 seconds
Started Mar 07 12:43:42 PM PST 24
Finished Mar 07 12:43:42 PM PST 24
Peak memory 205520 kb
Host smart-7dae0f6d-d393-432c-8d55-37dea7417118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459567886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3459567886
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.81785264
Short name T1100
Test name
Test status
Simulation time 1082552976 ps
CPU time 5.62 seconds
Started Mar 07 12:43:50 PM PST 24
Finished Mar 07 12:43:56 PM PST 24
Peak memory 217368 kb
Host smart-203743a8-04ae-4870-b7c0-aa2caf583944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81785264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.81785264
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_upload.861640194
Short name T1728
Test name
Test status
Simulation time 5149312167 ps
CPU time 8.15 seconds
Started Mar 07 02:46:04 PM PST 24
Finished Mar 07 02:46:13 PM PST 24
Peak memory 218312 kb
Host smart-24d8c833-c775-4178-bb99-f435398c9a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861640194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.861640194
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1332870484
Short name T1450
Test name
Test status
Simulation time 190418255 ps
CPU time 0.73 seconds
Started Mar 07 12:43:52 PM PST 24
Finished Mar 07 12:43:53 PM PST 24
Peak memory 205136 kb
Host smart-7d51880c-e777-418b-ab56-73a0b3683062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332870484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1332870484
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1399008489
Short name T1795
Test name
Test status
Simulation time 10952748 ps
CPU time 0.72 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:12 PM PST 24
Peak memory 204436 kb
Host smart-2e69a3fe-5f43-429d-bc35-baa0a8916053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399008489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1399008489
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2397759358
Short name T1520
Test name
Test status
Simulation time 705986731 ps
CPU time 2.41 seconds
Started Mar 07 12:43:45 PM PST 24
Finished Mar 07 12:43:47 PM PST 24
Peak memory 216808 kb
Host smart-0b52c809-1c71-4f72-8955-710f5b22fab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397759358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2397759358
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3749522239
Short name T1469
Test name
Test status
Simulation time 4958148530 ps
CPU time 8.32 seconds
Started Mar 07 02:46:10 PM PST 24
Finished Mar 07 02:46:18 PM PST 24
Peak memory 223980 kb
Host smart-b775661f-211d-4a97-a73a-1e61a87642a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749522239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3749522239
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3146724993
Short name T454
Test name
Test status
Simulation time 40951578 ps
CPU time 0.72 seconds
Started Mar 07 12:43:37 PM PST 24
Finished Mar 07 12:43:38 PM PST 24
Peak memory 205220 kb
Host smart-4075244d-ba7e-4968-9f6b-d229b630cef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146724993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3146724993
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.317917318
Short name T1733
Test name
Test status
Simulation time 16662063 ps
CPU time 0.87 seconds
Started Mar 07 02:46:05 PM PST 24
Finished Mar 07 02:46:06 PM PST 24
Peak memory 204740 kb
Host smart-8efd0125-49df-488e-a870-5a45ffda8a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317917318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.317917318
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.861859804
Short name T35
Test name
Test status
Simulation time 39586270027 ps
CPU time 57.77 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:44:46 PM PST 24
Peak memory 235148 kb
Host smart-ef58938b-d2c6-478a-9ec5-17fa26de1d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861859804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.861859804
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.927161285
Short name T987
Test name
Test status
Simulation time 57945458591 ps
CPU time 74.76 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:47:27 PM PST 24
Peak memory 234584 kb
Host smart-1973ceb9-65f2-45d3-a10b-b5208dcfa07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927161285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.927161285
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2334675806
Short name T1015
Test name
Test status
Simulation time 28772368782 ps
CPU time 225.51 seconds
Started Mar 07 02:46:13 PM PST 24
Finished Mar 07 02:49:59 PM PST 24
Peak memory 248696 kb
Host smart-f08e5b66-a8bc-4e90-b11f-f558c1385216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334675806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2334675806
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.180684405
Short name T624
Test name
Test status
Simulation time 6236660545 ps
CPU time 33.39 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:45 PM PST 24
Peak memory 240368 kb
Host smart-0b61dcb4-fb3f-4173-aa2f-d0ec9f336d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180684405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.180684405
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.242398391
Short name T557
Test name
Test status
Simulation time 2827732304 ps
CPU time 23.36 seconds
Started Mar 07 12:43:45 PM PST 24
Finished Mar 07 12:44:09 PM PST 24
Peak memory 240028 kb
Host smart-d7868207-78f0-4f2e-8dab-e3df243d6def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242398391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.242398391
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4073778904
Short name T1846
Test name
Test status
Simulation time 1958978200 ps
CPU time 7.57 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:19 PM PST 24
Peak memory 223888 kb
Host smart-b427f7db-6179-4f52-a322-a39fe5a68976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073778904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4073778904
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4105777121
Short name T788
Test name
Test status
Simulation time 4504153269 ps
CPU time 15.98 seconds
Started Mar 07 12:43:50 PM PST 24
Finished Mar 07 12:44:07 PM PST 24
Peak memory 231984 kb
Host smart-9d4fcab9-8bb5-4881-93b8-e9776be2dc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105777121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4105777121
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1415911540
Short name T1680
Test name
Test status
Simulation time 1088602208 ps
CPU time 6.82 seconds
Started Mar 07 02:46:12 PM PST 24
Finished Mar 07 02:46:19 PM PST 24
Peak memory 235260 kb
Host smart-9b9408be-8833-4c85-b909-d2fd65d4534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415911540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1415911540
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3516184220
Short name T255
Test name
Test status
Simulation time 23956101301 ps
CPU time 24.97 seconds
Started Mar 07 12:43:39 PM PST 24
Finished Mar 07 12:44:04 PM PST 24
Peak memory 231952 kb
Host smart-4469bec5-a3e3-4765-b142-9c6675e723c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516184220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3516184220
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2536089267
Short name T283
Test name
Test status
Simulation time 385172556 ps
CPU time 2.65 seconds
Started Mar 07 12:43:35 PM PST 24
Finished Mar 07 12:43:38 PM PST 24
Peak memory 218524 kb
Host smart-a3a16133-37c0-4dac-a3f3-a6baf9654847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536089267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2536089267
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2998910756
Short name T303
Test name
Test status
Simulation time 419041983 ps
CPU time 8.59 seconds
Started Mar 07 02:46:14 PM PST 24
Finished Mar 07 02:46:22 PM PST 24
Peak memory 239876 kb
Host smart-12f3c45d-e745-40e6-9f88-7b0c1d6c28ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998910756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2998910756
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2732074288
Short name T787
Test name
Test status
Simulation time 238129074 ps
CPU time 3.97 seconds
Started Mar 07 12:43:39 PM PST 24
Finished Mar 07 12:43:43 PM PST 24
Peak memory 232604 kb
Host smart-0a6eb989-cab6-41d4-b005-b547b72fc76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732074288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2732074288
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.979954777
Short name T1620
Test name
Test status
Simulation time 18093633597 ps
CPU time 26.63 seconds
Started Mar 07 02:46:14 PM PST 24
Finished Mar 07 02:46:41 PM PST 24
Peak memory 238432 kb
Host smart-d34612bd-5370-4028-83a6-0ff2db0ffb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979954777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.979954777
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2642047633
Short name T632
Test name
Test status
Simulation time 799889305 ps
CPU time 3.79 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:43:51 PM PST 24
Peak memory 218888 kb
Host smart-79054d9e-d8b1-4b7e-bedf-d497e20420f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2642047633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2642047633
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4045758326
Short name T1069
Test name
Test status
Simulation time 282926433 ps
CPU time 3 seconds
Started Mar 07 02:46:13 PM PST 24
Finished Mar 07 02:46:17 PM PST 24
Peak memory 221000 kb
Host smart-2ea11d71-d764-47dc-9482-da41b2cc4b92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4045758326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4045758326
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1039938427
Short name T281
Test name
Test status
Simulation time 32622919167 ps
CPU time 179.19 seconds
Started Mar 07 02:46:12 PM PST 24
Finished Mar 07 02:49:11 PM PST 24
Peak memory 281328 kb
Host smart-f5c638ba-efa6-4803-a76e-c7959a4bc856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039938427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1039938427
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1712658419
Short name T1565
Test name
Test status
Simulation time 15464087705 ps
CPU time 57.51 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:44:46 PM PST 24
Peak memory 240880 kb
Host smart-e8f4d081-7b8d-4b53-9a83-552afcb51022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712658419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1712658419
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1461197766
Short name T1326
Test name
Test status
Simulation time 3069221335 ps
CPU time 30.32 seconds
Started Mar 07 02:46:01 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 215840 kb
Host smart-37417229-fa3d-43d2-a2ae-ceb93cd58ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461197766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1461197766
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1767322665
Short name T914
Test name
Test status
Simulation time 3202877573 ps
CPU time 11.2 seconds
Started Mar 07 12:43:35 PM PST 24
Finished Mar 07 12:43:47 PM PST 24
Peak memory 216340 kb
Host smart-be1e59b1-3592-4206-9662-6ee4d6695950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767322665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1767322665
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3425570693
Short name T752
Test name
Test status
Simulation time 5892656124 ps
CPU time 18.51 seconds
Started Mar 07 02:46:04 PM PST 24
Finished Mar 07 02:46:23 PM PST 24
Peak memory 216212 kb
Host smart-ba32d5eb-4c05-4bd1-8d3c-5b40904dd8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425570693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3425570693
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.497788640
Short name T1663
Test name
Test status
Simulation time 1242832094 ps
CPU time 8.43 seconds
Started Mar 07 12:43:50 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 216048 kb
Host smart-c2a1ebe3-4e6d-4b6f-a8bd-f65c2e7aaf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497788640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.497788640
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1119294140
Short name T54
Test name
Test status
Simulation time 1140045151 ps
CPU time 2.33 seconds
Started Mar 07 12:43:36 PM PST 24
Finished Mar 07 12:43:39 PM PST 24
Peak memory 216196 kb
Host smart-c64e2489-783e-4b8e-9196-9a339495b9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119294140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1119294140
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1370490911
Short name T1075
Test name
Test status
Simulation time 177002716 ps
CPU time 1.39 seconds
Started Mar 07 02:46:10 PM PST 24
Finished Mar 07 02:46:11 PM PST 24
Peak memory 215768 kb
Host smart-24da2832-8d08-48d9-92b5-e17c40ce272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370490911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1370490911
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1354595692
Short name T882
Test name
Test status
Simulation time 67530518 ps
CPU time 0.71 seconds
Started Mar 07 02:46:03 PM PST 24
Finished Mar 07 02:46:04 PM PST 24
Peak memory 204816 kb
Host smart-99892ca8-1bf6-436e-9fd9-a8d37689fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354595692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1354595692
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2485779227
Short name T763
Test name
Test status
Simulation time 37544753 ps
CPU time 0.85 seconds
Started Mar 07 12:43:38 PM PST 24
Finished Mar 07 12:43:39 PM PST 24
Peak memory 205388 kb
Host smart-cd898372-e971-4388-bf27-ab4fff157cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485779227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2485779227
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3258328064
Short name T1054
Test name
Test status
Simulation time 9974205688 ps
CPU time 14.81 seconds
Started Mar 07 02:46:14 PM PST 24
Finished Mar 07 02:46:29 PM PST 24
Peak memory 240240 kb
Host smart-64fd65d5-74f7-453d-86cf-1fe38f016357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258328064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3258328064
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_upload.3901663610
Short name T1876
Test name
Test status
Simulation time 492566544 ps
CPU time 7.51 seconds
Started Mar 07 12:43:42 PM PST 24
Finished Mar 07 12:43:50 PM PST 24
Peak memory 234804 kb
Host smart-7c3d92b1-1972-4de7-b8f0-9ded029de4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901663610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3901663610
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3934775748
Short name T1184
Test name
Test status
Simulation time 21699982 ps
CPU time 0.75 seconds
Started Mar 07 02:43:17 PM PST 24
Finished Mar 07 02:43:18 PM PST 24
Peak memory 204652 kb
Host smart-e7db01d9-3ff4-4033-8786-464174334a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934775748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
934775748
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.807164198
Short name T396
Test name
Test status
Simulation time 45794247 ps
CPU time 0.79 seconds
Started Mar 07 12:41:10 PM PST 24
Finished Mar 07 12:41:11 PM PST 24
Peak memory 205044 kb
Host smart-4b84b29e-4f54-4c95-a9cf-7465147c4a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807164198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.807164198
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1941366875
Short name T871
Test name
Test status
Simulation time 1006865608 ps
CPU time 3.86 seconds
Started Mar 07 12:41:07 PM PST 24
Finished Mar 07 12:41:11 PM PST 24
Peak memory 237900 kb
Host smart-82d6b2ef-6c82-435e-be36-b79468c0258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941366875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1941366875
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2592573768
Short name T675
Test name
Test status
Simulation time 257903809 ps
CPU time 3.65 seconds
Started Mar 07 02:43:07 PM PST 24
Finished Mar 07 02:43:11 PM PST 24
Peak memory 233116 kb
Host smart-bd4d34f9-f2ee-49a6-87a6-22cf0a5a0f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592573768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2592573768
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1418400489
Short name T757
Test name
Test status
Simulation time 15625894 ps
CPU time 0.72 seconds
Started Mar 07 12:40:55 PM PST 24
Finished Mar 07 12:40:56 PM PST 24
Peak memory 206628 kb
Host smart-e687896f-3a7c-4575-9cac-b597a7ed3073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418400489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1418400489
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1786716861
Short name T774
Test name
Test status
Simulation time 23502251 ps
CPU time 0.81 seconds
Started Mar 07 02:43:11 PM PST 24
Finished Mar 07 02:43:12 PM PST 24
Peak memory 205480 kb
Host smart-13482cac-c356-4057-9389-e54c4e4f0cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786716861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1786716861
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2725233568
Short name T271
Test name
Test status
Simulation time 199293684516 ps
CPU time 403.1 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:49:57 PM PST 24
Peak memory 255184 kb
Host smart-34538d7d-2e70-4f57-80a7-0fd59af9ba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725233568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2725233568
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3585039735
Short name T29
Test name
Test status
Simulation time 74457662667 ps
CPU time 131.73 seconds
Started Mar 07 12:41:11 PM PST 24
Finished Mar 07 12:43:23 PM PST 24
Peak memory 250068 kb
Host smart-8e73e63e-142a-4a9b-888a-48bd03ebb801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585039735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3585039735
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1116755564
Short name T822
Test name
Test status
Simulation time 306151712489 ps
CPU time 141.52 seconds
Started Mar 07 12:41:13 PM PST 24
Finished Mar 07 12:43:35 PM PST 24
Peak memory 252040 kb
Host smart-476c8a46-5542-404a-9b17-22cada1c6703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116755564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1116755564
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3742683526
Short name T1293
Test name
Test status
Simulation time 316550428744 ps
CPU time 443.38 seconds
Started Mar 07 02:43:05 PM PST 24
Finished Mar 07 02:50:29 PM PST 24
Peak memory 258184 kb
Host smart-3a82fb25-400b-4e6c-8fc3-465644f05f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742683526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3742683526
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2760925890
Short name T270
Test name
Test status
Simulation time 466594110908 ps
CPU time 731.78 seconds
Started Mar 07 12:41:13 PM PST 24
Finished Mar 07 12:53:25 PM PST 24
Peak memory 256816 kb
Host smart-9938b5dd-ddb0-482d-8539-814a98f6e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760925890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2760925890
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4277310507
Short name T319
Test name
Test status
Simulation time 14260829243 ps
CPU time 88.9 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:44:43 PM PST 24
Peak memory 250852 kb
Host smart-18a2852d-0f18-495b-98a9-9b137adc7172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277310507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4277310507
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3990837055
Short name T310
Test name
Test status
Simulation time 421591802 ps
CPU time 8.17 seconds
Started Mar 07 02:43:07 PM PST 24
Finished Mar 07 02:43:16 PM PST 24
Peak memory 223280 kb
Host smart-c58f4526-cd6d-4926-aecb-969fb7760625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990837055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3990837055
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4063207869
Short name T1916
Test name
Test status
Simulation time 4649386980 ps
CPU time 25.35 seconds
Started Mar 07 12:41:13 PM PST 24
Finished Mar 07 12:41:38 PM PST 24
Peak memory 233968 kb
Host smart-1933b1b8-04e5-4cff-bf75-7b156cbe203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063207869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4063207869
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1727784072
Short name T1744
Test name
Test status
Simulation time 3259727768 ps
CPU time 8.63 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:13 PM PST 24
Peak memory 217468 kb
Host smart-33faa005-9ac1-4601-ab7d-9b277692b83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727784072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1727784072
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3577547051
Short name T1366
Test name
Test status
Simulation time 141617967 ps
CPU time 2.69 seconds
Started Mar 07 12:41:08 PM PST 24
Finished Mar 07 12:41:11 PM PST 24
Peak memory 224440 kb
Host smart-19a40228-93e3-4a37-85e1-6bfef4dbae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577547051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3577547051
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2176361754
Short name T199
Test name
Test status
Simulation time 8264093701 ps
CPU time 18.81 seconds
Started Mar 07 02:43:11 PM PST 24
Finished Mar 07 02:43:30 PM PST 24
Peak memory 239772 kb
Host smart-cff62e84-5dec-4158-ad40-0098c78138e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176361754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2176361754
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.738193727
Short name T1689
Test name
Test status
Simulation time 24502047628 ps
CPU time 43.63 seconds
Started Mar 07 12:41:12 PM PST 24
Finished Mar 07 12:41:55 PM PST 24
Peak memory 235612 kb
Host smart-c4a7fefe-c2d6-4303-8546-8a9812a4a83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738193727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.738193727
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.847417177
Short name T1238
Test name
Test status
Simulation time 109302961 ps
CPU time 1.1 seconds
Started Mar 07 02:43:06 PM PST 24
Finished Mar 07 02:43:08 PM PST 24
Peak memory 216072 kb
Host smart-f73d6ac4-dc22-469b-a218-415177f0b407
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847417177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.847417177
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.454765837
Short name T295
Test name
Test status
Simulation time 151202438436 ps
CPU time 25.89 seconds
Started Mar 07 12:41:12 PM PST 24
Finished Mar 07 12:41:39 PM PST 24
Peak memory 233752 kb
Host smart-2d2d3bad-03a4-46d3-a1ca-a74f40861dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454765837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
454765837
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.679867453
Short name T1892
Test name
Test status
Simulation time 482028588 ps
CPU time 5.81 seconds
Started Mar 07 02:43:06 PM PST 24
Finished Mar 07 02:43:13 PM PST 24
Peak memory 227048 kb
Host smart-36b29498-c36e-4cfd-8a1e-738d69fdf5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679867453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
679867453
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1330900685
Short name T354
Test name
Test status
Simulation time 1136393664 ps
CPU time 3.37 seconds
Started Mar 07 02:43:11 PM PST 24
Finished Mar 07 02:43:15 PM PST 24
Peak memory 218164 kb
Host smart-e5fc6ae0-bed2-4f6b-8ee9-924ecf4469c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330900685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1330900685
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.506807971
Short name T1087
Test name
Test status
Simulation time 3805340258 ps
CPU time 11.95 seconds
Started Mar 07 12:41:13 PM PST 24
Finished Mar 07 12:41:25 PM PST 24
Peak memory 227892 kb
Host smart-8e0261ff-aedc-4bac-aff5-0dd3fa000329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506807971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.506807971
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1987262244
Short name T340
Test name
Test status
Simulation time 35948042 ps
CPU time 0.76 seconds
Started Mar 07 02:43:06 PM PST 24
Finished Mar 07 02:43:08 PM PST 24
Peak memory 215624 kb
Host smart-dc84a560-803d-4202-a3c7-c25a6218a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987262244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1987262244
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3775464024
Short name T829
Test name
Test status
Simulation time 15613001 ps
CPU time 0.78 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:01 PM PST 24
Peak memory 216212 kb
Host smart-92138e45-4cdc-42b0-8b6a-04c711c0ce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775464024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3775464024
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2582640473
Short name T1524
Test name
Test status
Simulation time 2224608189 ps
CPU time 8.47 seconds
Started Mar 07 12:41:08 PM PST 24
Finished Mar 07 12:41:17 PM PST 24
Peak memory 222740 kb
Host smart-a56b49fd-f44e-4fa8-967e-5ce041936348
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2582640473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2582640473
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2615056127
Short name T149
Test name
Test status
Simulation time 488484213 ps
CPU time 3.92 seconds
Started Mar 07 02:43:03 PM PST 24
Finished Mar 07 02:43:07 PM PST 24
Peak memory 219436 kb
Host smart-a59c0046-45d1-458c-ba02-edb720d9580d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2615056127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2615056127
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2396700965
Short name T69
Test name
Test status
Simulation time 146597460 ps
CPU time 1.08 seconds
Started Mar 07 12:41:09 PM PST 24
Finished Mar 07 12:41:10 PM PST 24
Peak memory 235596 kb
Host smart-fe58eb37-c3d2-4673-8f3d-bdff5016a478
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396700965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2396700965
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3648783034
Short name T66
Test name
Test status
Simulation time 186990000 ps
CPU time 1.16 seconds
Started Mar 07 02:43:16 PM PST 24
Finished Mar 07 02:43:18 PM PST 24
Peak memory 235028 kb
Host smart-43c85b96-7a30-42d3-86c7-b6f194ba6668
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648783034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3648783034
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2724867419
Short name T160
Test name
Test status
Simulation time 164152966131 ps
CPU time 277.26 seconds
Started Mar 07 02:43:17 PM PST 24
Finished Mar 07 02:47:55 PM PST 24
Peak memory 265048 kb
Host smart-05c51f01-1c32-43fa-802e-e1344d4636da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724867419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2724867419
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3062287143
Short name T1068
Test name
Test status
Simulation time 94147340501 ps
CPU time 246.56 seconds
Started Mar 07 12:41:09 PM PST 24
Finished Mar 07 12:45:16 PM PST 24
Peak memory 284956 kb
Host smart-8cfe34e3-c8a4-4138-9652-6cc2d0d1034f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062287143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3062287143
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1629731486
Short name T318
Test name
Test status
Simulation time 44928307703 ps
CPU time 51.86 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:56 PM PST 24
Peak memory 215744 kb
Host smart-7708ebdf-379f-4494-a825-bb742fee75fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629731486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1629731486
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.460448348
Short name T655
Test name
Test status
Simulation time 2595257475 ps
CPU time 9.37 seconds
Started Mar 07 12:40:58 PM PST 24
Finished Mar 07 12:41:08 PM PST 24
Peak memory 216280 kb
Host smart-ebb52c5c-cff5-460a-9b50-e4702730f6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460448348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.460448348
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1771003218
Short name T614
Test name
Test status
Simulation time 2709719917 ps
CPU time 1.8 seconds
Started Mar 07 12:41:00 PM PST 24
Finished Mar 07 12:41:02 PM PST 24
Peak memory 207680 kb
Host smart-dadebb44-eb9f-4a0a-bf3c-6c7002873983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771003218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1771003218
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.717721506
Short name T1799
Test name
Test status
Simulation time 48543281271 ps
CPU time 28.22 seconds
Started Mar 07 02:43:07 PM PST 24
Finished Mar 07 02:43:36 PM PST 24
Peak memory 215904 kb
Host smart-381dbdfe-37c2-463a-999a-503c93ba09d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717721506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.717721506
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1528699830
Short name T514
Test name
Test status
Simulation time 34246441 ps
CPU time 0.89 seconds
Started Mar 07 02:43:04 PM PST 24
Finished Mar 07 02:43:05 PM PST 24
Peak memory 206196 kb
Host smart-54f33ac1-bca8-495e-a67a-adc99d3c383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528699830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1528699830
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2706257343
Short name T980
Test name
Test status
Simulation time 555409736 ps
CPU time 3.69 seconds
Started Mar 07 12:41:08 PM PST 24
Finished Mar 07 12:41:11 PM PST 24
Peak memory 216276 kb
Host smart-d4b00267-21d9-42a7-8895-ef605065e2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706257343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2706257343
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2087867675
Short name T339
Test name
Test status
Simulation time 265866374 ps
CPU time 0.93 seconds
Started Mar 07 02:43:03 PM PST 24
Finished Mar 07 02:43:04 PM PST 24
Peak memory 205868 kb
Host smart-ff872fea-ccd8-4f6e-b340-d2980f297646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087867675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2087867675
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2384400643
Short name T1123
Test name
Test status
Simulation time 98857403 ps
CPU time 0.73 seconds
Started Mar 07 12:41:11 PM PST 24
Finished Mar 07 12:41:12 PM PST 24
Peak memory 205400 kb
Host smart-7ada23de-5d3e-4163-bec7-94c66e135033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384400643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2384400643
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1374268339
Short name T667
Test name
Test status
Simulation time 4195245767 ps
CPU time 8.66 seconds
Started Mar 07 12:41:11 PM PST 24
Finished Mar 07 12:41:20 PM PST 24
Peak memory 238780 kb
Host smart-c5c60f28-2be9-4a3b-a114-c99e75f6e6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374268339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1374268339
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_upload.342067105
Short name T439
Test name
Test status
Simulation time 2039211354 ps
CPU time 8.92 seconds
Started Mar 07 02:43:05 PM PST 24
Finished Mar 07 02:43:14 PM PST 24
Peak memory 225032 kb
Host smart-9e7a36ee-6a7f-45ab-b050-ea185249c954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342067105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.342067105
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2018871315
Short name T710
Test name
Test status
Simulation time 15400730 ps
CPU time 0.75 seconds
Started Mar 07 02:46:13 PM PST 24
Finished Mar 07 02:46:14 PM PST 24
Peak memory 204428 kb
Host smart-8c6a9a1a-6d16-44e4-8fb3-646c916e1160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018871315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2018871315
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3514762772
Short name T452
Test name
Test status
Simulation time 21638118 ps
CPU time 0.7 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:43:49 PM PST 24
Peak memory 204536 kb
Host smart-e4a01341-e8ef-4a2a-9108-b4fee1c944a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514762772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3514762772
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3074137198
Short name T843
Test name
Test status
Simulation time 1156548464 ps
CPU time 3.79 seconds
Started Mar 07 02:46:17 PM PST 24
Finished Mar 07 02:46:21 PM PST 24
Peak memory 218328 kb
Host smart-6bb6246c-8aab-4168-936c-395cc5a8bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074137198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3074137198
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3538423564
Short name T1761
Test name
Test status
Simulation time 355783051 ps
CPU time 4.35 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:43:51 PM PST 24
Peak memory 234892 kb
Host smart-46cf37ea-6640-4183-aa61-01fd8620ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538423564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3538423564
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1897446197
Short name T1638
Test name
Test status
Simulation time 60823716 ps
CPU time 0.78 seconds
Started Mar 07 12:43:45 PM PST 24
Finished Mar 07 12:43:46 PM PST 24
Peak memory 206688 kb
Host smart-0925f18b-82a7-4a0e-9870-54d4aea1e66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897446197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1897446197
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4015805681
Short name T328
Test name
Test status
Simulation time 17332771 ps
CPU time 0.78 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:12 PM PST 24
Peak memory 205480 kb
Host smart-9e7d763f-b75e-44b8-9594-275c00c7bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015805681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4015805681
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2392596499
Short name T866
Test name
Test status
Simulation time 7228939139 ps
CPU time 17.52 seconds
Started Mar 07 12:43:51 PM PST 24
Finished Mar 07 12:44:10 PM PST 24
Peak memory 234112 kb
Host smart-d0b64f6a-70ef-41a1-ba44-2b1ea3b30101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392596499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2392596499
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3049852877
Short name T956
Test name
Test status
Simulation time 114082504928 ps
CPU time 149.54 seconds
Started Mar 07 02:46:13 PM PST 24
Finished Mar 07 02:48:43 PM PST 24
Peak memory 248552 kb
Host smart-a3cfedd6-cb64-4548-b8b6-7ac2c60ad303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049852877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3049852877
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4118324535
Short name T280
Test name
Test status
Simulation time 48971805195 ps
CPU time 400.44 seconds
Started Mar 07 02:46:10 PM PST 24
Finished Mar 07 02:52:51 PM PST 24
Peak memory 268968 kb
Host smart-57198558-f41b-4e64-a9f5-ae1647212430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118324535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4118324535
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.417806869
Short name T1442
Test name
Test status
Simulation time 15266892235 ps
CPU time 162.92 seconds
Started Mar 07 12:43:45 PM PST 24
Finished Mar 07 12:46:29 PM PST 24
Peak memory 263576 kb
Host smart-c151ccb4-1493-4b57-b136-31b8505c093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417806869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.417806869
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.441068103
Short name T285
Test name
Test status
Simulation time 7734461553 ps
CPU time 43.34 seconds
Started Mar 07 02:46:13 PM PST 24
Finished Mar 07 02:46:57 PM PST 24
Peak memory 253344 kb
Host smart-26a20507-c06e-479e-b884-8fac9af745a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441068103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.441068103
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.670152497
Short name T1731
Test name
Test status
Simulation time 36228350000 ps
CPU time 247.46 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:47:55 PM PST 24
Peak memory 250840 kb
Host smart-7b14ca0b-af6a-448f-ab2a-0efdc06d0d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670152497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.670152497
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1644596841
Short name T556
Test name
Test status
Simulation time 2504740184 ps
CPU time 17.97 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:44:05 PM PST 24
Peak memory 240848 kb
Host smart-7b4f19d1-0c8d-4073-901f-8e0205d7a2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644596841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1644596841
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.274098039
Short name T1698
Test name
Test status
Simulation time 3197344161 ps
CPU time 11.77 seconds
Started Mar 07 02:46:14 PM PST 24
Finished Mar 07 02:46:26 PM PST 24
Peak memory 219220 kb
Host smart-16a44f4d-de54-4522-a283-4f567b360d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274098039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.274098039
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3966396854
Short name T583
Test name
Test status
Simulation time 1436762847 ps
CPU time 4.58 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:43:52 PM PST 24
Peak memory 224428 kb
Host smart-285ac361-2966-4d65-87b7-336caeb6e4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966396854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3966396854
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2420023717
Short name T966
Test name
Test status
Simulation time 12994909897 ps
CPU time 33.96 seconds
Started Mar 07 12:43:45 PM PST 24
Finished Mar 07 12:44:20 PM PST 24
Peak memory 232932 kb
Host smart-f910c7d8-904a-4c4b-b72c-858b7a756083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420023717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2420023717
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.758156541
Short name T883
Test name
Test status
Simulation time 5499918691 ps
CPU time 6.92 seconds
Started Mar 07 02:46:12 PM PST 24
Finished Mar 07 02:46:19 PM PST 24
Peak memory 221544 kb
Host smart-f7293d71-0100-4dd5-b7b6-b254b0c572b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758156541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.758156541
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1147141621
Short name T1131
Test name
Test status
Simulation time 5344642505 ps
CPU time 19.17 seconds
Started Mar 07 02:46:10 PM PST 24
Finished Mar 07 02:46:29 PM PST 24
Peak memory 240240 kb
Host smart-c060f7da-8bb4-4a2e-83eb-4229a12e7ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147141621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1147141621
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4020044551
Short name T803
Test name
Test status
Simulation time 5854949823 ps
CPU time 12.04 seconds
Started Mar 07 12:43:50 PM PST 24
Finished Mar 07 12:44:02 PM PST 24
Peak memory 234132 kb
Host smart-74397510-dd8b-4a44-b774-c931c81123f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020044551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4020044551
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2110516577
Short name T574
Test name
Test status
Simulation time 5078617301 ps
CPU time 14.83 seconds
Started Mar 07 12:43:45 PM PST 24
Finished Mar 07 12:44:01 PM PST 24
Peak memory 224216 kb
Host smart-59e530c5-c883-43b1-99a2-043bb5c0f771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110516577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2110516577
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.480657158
Short name T610
Test name
Test status
Simulation time 7454461719 ps
CPU time 13.86 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:25 PM PST 24
Peak memory 239960 kb
Host smart-3b8eea20-6bd3-424a-b1b2-a0a2d3f8073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480657158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.480657158
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.125729295
Short name T1005
Test name
Test status
Simulation time 1775137146 ps
CPU time 5.25 seconds
Started Mar 07 02:46:12 PM PST 24
Finished Mar 07 02:46:18 PM PST 24
Peak memory 222000 kb
Host smart-935726e8-a90c-4913-9937-17b4697f9391
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=125729295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.125729295
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3030593958
Short name T1059
Test name
Test status
Simulation time 626754458 ps
CPU time 3.25 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:43:51 PM PST 24
Peak memory 220376 kb
Host smart-cbd6a4a8-e49e-4a6b-a61a-af78bcaf0ba1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3030593958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3030593958
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3900091591
Short name T625
Test name
Test status
Simulation time 104747250445 ps
CPU time 219.71 seconds
Started Mar 07 12:43:49 PM PST 24
Finished Mar 07 12:47:29 PM PST 24
Peak memory 264600 kb
Host smart-ebd529e3-448e-435e-bf50-1364ce04f2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900091591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3900091591
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3020658055
Short name T612
Test name
Test status
Simulation time 9421231942 ps
CPU time 12.29 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:23 PM PST 24
Peak memory 216056 kb
Host smart-c80da259-04a3-4713-a68f-de402895d60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020658055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3020658055
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.929771392
Short name T571
Test name
Test status
Simulation time 2116116989 ps
CPU time 6.39 seconds
Started Mar 07 12:43:46 PM PST 24
Finished Mar 07 12:43:53 PM PST 24
Peak memory 216132 kb
Host smart-e1cd5227-d186-4df0-aa15-e4369c1ad8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929771392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.929771392
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2144335769
Short name T791
Test name
Test status
Simulation time 114685661 ps
CPU time 1.55 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:43:50 PM PST 24
Peak memory 207484 kb
Host smart-61092abe-bfc4-402a-8e1c-214d9f51caf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144335769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2144335769
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3192747910
Short name T78
Test name
Test status
Simulation time 382149609 ps
CPU time 2.43 seconds
Started Mar 07 02:46:12 PM PST 24
Finished Mar 07 02:46:15 PM PST 24
Peak memory 207340 kb
Host smart-bf1676eb-0754-4b94-a4d1-f9c119817846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192747910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3192747910
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1637418367
Short name T604
Test name
Test status
Simulation time 1074876774 ps
CPU time 3.39 seconds
Started Mar 07 02:46:12 PM PST 24
Finished Mar 07 02:46:15 PM PST 24
Peak memory 216904 kb
Host smart-bdcdf84b-2e9c-46aa-9537-5f210383003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637418367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1637418367
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2452787572
Short name T42
Test name
Test status
Simulation time 46431487 ps
CPU time 1.47 seconds
Started Mar 07 12:43:44 PM PST 24
Finished Mar 07 12:43:46 PM PST 24
Peak memory 216164 kb
Host smart-27c6ed3c-c859-4cdb-a33a-dc7a40faf3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452787572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2452787572
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1031683669
Short name T1779
Test name
Test status
Simulation time 318236895 ps
CPU time 1.19 seconds
Started Mar 07 12:43:46 PM PST 24
Finished Mar 07 12:43:48 PM PST 24
Peak memory 206560 kb
Host smart-a60bd384-470a-4371-aa74-a4ec3a6debd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031683669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1031683669
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1689733207
Short name T1420
Test name
Test status
Simulation time 175456280 ps
CPU time 0.81 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:12 PM PST 24
Peak memory 204924 kb
Host smart-3f982a17-8e07-4c0e-afc6-d4ab4079beef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689733207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1689733207
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1470857675
Short name T1566
Test name
Test status
Simulation time 3934508124 ps
CPU time 12.24 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:24 PM PST 24
Peak memory 229544 kb
Host smart-adac8c11-89e0-40ee-819a-5d8f5a378a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470857675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1470857675
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_upload.2936839347
Short name T1166
Test name
Test status
Simulation time 2116669743 ps
CPU time 9.65 seconds
Started Mar 07 12:43:46 PM PST 24
Finished Mar 07 12:43:56 PM PST 24
Peak memory 236316 kb
Host smart-ebab17eb-5cb2-436d-9302-018cf50cdacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936839347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2936839347
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.487140506
Short name T608
Test name
Test status
Simulation time 20538520 ps
CPU time 0.7 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:43:48 PM PST 24
Peak memory 204556 kb
Host smart-3c67f415-b333-42c5-a0a6-aa91fa42bbc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487140506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.487140506
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.557621894
Short name T955
Test name
Test status
Simulation time 20166795 ps
CPU time 0.68 seconds
Started Mar 07 02:46:22 PM PST 24
Finished Mar 07 02:46:23 PM PST 24
Peak memory 204416 kb
Host smart-ac025a53-4b37-44da-bba8-3d1458252de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557621894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.557621894
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2598338531
Short name T1727
Test name
Test status
Simulation time 136916108 ps
CPU time 2.84 seconds
Started Mar 07 02:46:21 PM PST 24
Finished Mar 07 02:46:24 PM PST 24
Peak memory 233092 kb
Host smart-d75f5ef6-1f97-4565-a439-688d30d6572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598338531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2598338531
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.936160707
Short name T1649
Test name
Test status
Simulation time 4708152177 ps
CPU time 10 seconds
Started Mar 07 12:43:46 PM PST 24
Finished Mar 07 12:43:56 PM PST 24
Peak memory 219424 kb
Host smart-35191a10-8b9a-4428-9d24-4a63a5a6b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936160707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.936160707
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3008238267
Short name T461
Test name
Test status
Simulation time 13137814 ps
CPU time 0.81 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:43:49 PM PST 24
Peak memory 206700 kb
Host smart-8449b1d2-3f3a-4191-a29a-2ca1475fda4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008238267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3008238267
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.644780767
Short name T959
Test name
Test status
Simulation time 60636501 ps
CPU time 0.75 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:12 PM PST 24
Peak memory 204476 kb
Host smart-1574cd88-eabb-44c3-992d-99f0f58a3218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644780767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.644780767
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3470648850
Short name T201
Test name
Test status
Simulation time 32649373175 ps
CPU time 154.29 seconds
Started Mar 07 02:46:22 PM PST 24
Finished Mar 07 02:48:57 PM PST 24
Peak memory 248660 kb
Host smart-1b0ece0f-2e60-4748-b78e-3e82af0844d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470648850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3470648850
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.713665984
Short name T195
Test name
Test status
Simulation time 24382927473 ps
CPU time 87.35 seconds
Started Mar 07 12:43:49 PM PST 24
Finished Mar 07 12:45:16 PM PST 24
Peak memory 257276 kb
Host smart-15b5f14b-aaf6-4a8b-834a-a40a4e175600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713665984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.713665984
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1005871990
Short name T1888
Test name
Test status
Simulation time 59183135870 ps
CPU time 293.96 seconds
Started Mar 07 02:46:21 PM PST 24
Finished Mar 07 02:51:16 PM PST 24
Peak memory 249736 kb
Host smart-ef98afed-a42c-461d-a679-b816e8ce4cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005871990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1005871990
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3684243165
Short name T248
Test name
Test status
Simulation time 448010383924 ps
CPU time 285.49 seconds
Started Mar 07 12:43:51 PM PST 24
Finished Mar 07 12:48:38 PM PST 24
Peak memory 268124 kb
Host smart-ec91d927-a51f-44e7-9c93-0db14580dba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684243165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3684243165
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2017482239
Short name T596
Test name
Test status
Simulation time 75160663159 ps
CPU time 527.58 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:52:36 PM PST 24
Peak memory 281944 kb
Host smart-4b526c16-3d1b-4dae-ab0c-17eb15407d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017482239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2017482239
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.604374665
Short name T1121
Test name
Test status
Simulation time 5313628615 ps
CPU time 80.06 seconds
Started Mar 07 02:46:23 PM PST 24
Finished Mar 07 02:47:43 PM PST 24
Peak memory 248304 kb
Host smart-e89a486b-5d4d-4192-8968-099736c2b6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604374665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.604374665
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1953970944
Short name T316
Test name
Test status
Simulation time 12239848375 ps
CPU time 56.56 seconds
Started Mar 07 02:46:24 PM PST 24
Finished Mar 07 02:47:21 PM PST 24
Peak memory 245644 kb
Host smart-d024d5b7-2cc5-482a-82f7-8dac2a403e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953970944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1953970944
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3003201437
Short name T315
Test name
Test status
Simulation time 12953265669 ps
CPU time 25.33 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:44:14 PM PST 24
Peak memory 232660 kb
Host smart-d0fb6997-e07b-40fd-9ddb-20a836385748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003201437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3003201437
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3297996897
Short name T170
Test name
Test status
Simulation time 1818277274 ps
CPU time 5.14 seconds
Started Mar 07 12:43:46 PM PST 24
Finished Mar 07 12:43:52 PM PST 24
Peak memory 233568 kb
Host smart-d50916b6-4938-43c6-b199-7d02939f552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297996897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3297996897
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3736897623
Short name T1231
Test name
Test status
Simulation time 232353079 ps
CPU time 2.68 seconds
Started Mar 07 02:46:20 PM PST 24
Finished Mar 07 02:46:23 PM PST 24
Peak memory 216056 kb
Host smart-6660ba82-b715-43c7-b1c0-a1498dca63e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736897623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3736897623
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3254965688
Short name T1598
Test name
Test status
Simulation time 8381677428 ps
CPU time 29.76 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:44:17 PM PST 24
Peak memory 245568 kb
Host smart-33c75080-7195-4467-a1a6-7e2fcdc63fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254965688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3254965688
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.747973491
Short name T259
Test name
Test status
Simulation time 3597974032 ps
CPU time 9.55 seconds
Started Mar 07 02:46:19 PM PST 24
Finished Mar 07 02:46:29 PM PST 24
Peak memory 233060 kb
Host smart-aa058955-77a3-41a3-8417-cd9bb8bac8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747973491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.747973491
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2382580691
Short name T1290
Test name
Test status
Simulation time 14042763910 ps
CPU time 10.41 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 217108 kb
Host smart-af8a743b-eee9-4499-a01f-09229ffa3958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382580691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2382580691
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2666869706
Short name T1530
Test name
Test status
Simulation time 530771493 ps
CPU time 6.5 seconds
Started Mar 07 02:46:22 PM PST 24
Finished Mar 07 02:46:29 PM PST 24
Peak memory 240212 kb
Host smart-54033d01-38b0-4144-834c-a875c7b0c8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666869706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2666869706
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1615125432
Short name T233
Test name
Test status
Simulation time 1092256398 ps
CPU time 5.64 seconds
Started Mar 07 02:46:20 PM PST 24
Finished Mar 07 02:46:27 PM PST 24
Peak memory 233504 kb
Host smart-45866a57-d306-4cbd-8938-d5758b9d9398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615125432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1615125432
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.206295701
Short name T487
Test name
Test status
Simulation time 15906185500 ps
CPU time 15.18 seconds
Started Mar 07 12:43:51 PM PST 24
Finished Mar 07 12:44:06 PM PST 24
Peak memory 218732 kb
Host smart-bb46a252-22b3-4fe1-8396-285457d8df77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206295701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.206295701
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1159012214
Short name T1064
Test name
Test status
Simulation time 601329248 ps
CPU time 3.91 seconds
Started Mar 07 02:46:21 PM PST 24
Finished Mar 07 02:46:25 PM PST 24
Peak memory 221444 kb
Host smart-085a033c-5126-477a-8e22-96d9c9f35de4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159012214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1159012214
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1826039717
Short name T620
Test name
Test status
Simulation time 4951103909 ps
CPU time 5.77 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:43:54 PM PST 24
Peak memory 219644 kb
Host smart-eaa7522a-b5b7-42d4-842a-2768862a4359
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1826039717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1826039717
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1350506666
Short name T164
Test name
Test status
Simulation time 13390621086 ps
CPU time 97.48 seconds
Started Mar 07 12:43:48 PM PST 24
Finished Mar 07 12:45:26 PM PST 24
Peak memory 233780 kb
Host smart-da254daa-b980-48a7-96e1-0fc979e2ff24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350506666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1350506666
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2787806902
Short name T1901
Test name
Test status
Simulation time 10854587404 ps
CPU time 48.45 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:44:36 PM PST 24
Peak memory 216292 kb
Host smart-b43b22a1-27ba-49af-821e-6f6db3483097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787806902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2787806902
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3599100609
Short name T1086
Test name
Test status
Simulation time 4820197414 ps
CPU time 9.4 seconds
Started Mar 07 02:46:11 PM PST 24
Finished Mar 07 02:46:21 PM PST 24
Peak memory 215776 kb
Host smart-fdb73bc3-9819-4cbb-9bff-d17fe809ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599100609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3599100609
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1811356681
Short name T351
Test name
Test status
Simulation time 4502961932 ps
CPU time 6.45 seconds
Started Mar 07 12:43:46 PM PST 24
Finished Mar 07 12:43:53 PM PST 24
Peak memory 216204 kb
Host smart-ca613be4-09f0-435a-8634-675468a91b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811356681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1811356681
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2584135292
Short name T38
Test name
Test status
Simulation time 26034025154 ps
CPU time 10.09 seconds
Started Mar 07 02:46:13 PM PST 24
Finished Mar 07 02:46:24 PM PST 24
Peak memory 215764 kb
Host smart-d25fa1d7-483f-4b08-a7c7-402929b6aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584135292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2584135292
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.293111969
Short name T414
Test name
Test status
Simulation time 31584437 ps
CPU time 1.83 seconds
Started Mar 07 12:43:49 PM PST 24
Finished Mar 07 12:43:51 PM PST 24
Peak memory 216468 kb
Host smart-b73cfed2-b0d2-45b7-934d-32521c2da6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293111969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.293111969
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.347389051
Short name T1896
Test name
Test status
Simulation time 30725292 ps
CPU time 0.95 seconds
Started Mar 07 02:46:27 PM PST 24
Finished Mar 07 02:46:28 PM PST 24
Peak memory 205992 kb
Host smart-fc21b5df-474b-4d9c-8cbe-c8ac40a596cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347389051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.347389051
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.273202229
Short name T1614
Test name
Test status
Simulation time 158169076 ps
CPU time 0.97 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:43:49 PM PST 24
Peak memory 205576 kb
Host smart-27398a1f-2bc5-4007-bc64-14ce22663c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273202229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.273202229
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4282580546
Short name T644
Test name
Test status
Simulation time 66201753 ps
CPU time 0.93 seconds
Started Mar 07 02:46:22 PM PST 24
Finished Mar 07 02:46:24 PM PST 24
Peak memory 204900 kb
Host smart-75860be7-e5e3-44d3-9bb3-59559d2fc8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282580546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4282580546
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1123901434
Short name T242
Test name
Test status
Simulation time 907678682 ps
CPU time 4.46 seconds
Started Mar 07 12:43:45 PM PST 24
Finished Mar 07 12:43:50 PM PST 24
Peak memory 233412 kb
Host smart-e4b0aabf-3a87-41b0-a137-33dfb347cb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123901434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1123901434
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_upload.1471398711
Short name T1094
Test name
Test status
Simulation time 7551122990 ps
CPU time 14.91 seconds
Started Mar 07 02:46:22 PM PST 24
Finished Mar 07 02:46:38 PM PST 24
Peak memory 218460 kb
Host smart-1d3dba35-a289-422b-a91f-6d0db72947d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471398711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1471398711
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2869665505
Short name T543
Test name
Test status
Simulation time 21334238 ps
CPU time 0.69 seconds
Started Mar 07 02:46:22 PM PST 24
Finished Mar 07 02:46:23 PM PST 24
Peak memory 204732 kb
Host smart-b521e5e0-9ded-4acd-9932-316adc33917b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869665505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2869665505
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3026083384
Short name T1713
Test name
Test status
Simulation time 60317698 ps
CPU time 0.72 seconds
Started Mar 07 12:43:59 PM PST 24
Finished Mar 07 12:44:00 PM PST 24
Peak memory 205088 kb
Host smart-f9a0598c-410c-42f4-b889-f2a82e5a6db4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026083384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3026083384
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2015399621
Short name T1171
Test name
Test status
Simulation time 4105618417 ps
CPU time 5.01 seconds
Started Mar 07 02:46:20 PM PST 24
Finished Mar 07 02:46:26 PM PST 24
Peak memory 233032 kb
Host smart-5720d507-95e1-436d-904c-22140ed874a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015399621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2015399621
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2725418776
Short name T397
Test name
Test status
Simulation time 260813371 ps
CPU time 2.84 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 233888 kb
Host smart-a08e3db8-a9de-4284-81c1-a0f5d1b53496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725418776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2725418776
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3506715357
Short name T1665
Test name
Test status
Simulation time 48985286 ps
CPU time 0.77 seconds
Started Mar 07 02:46:23 PM PST 24
Finished Mar 07 02:46:25 PM PST 24
Peak memory 204864 kb
Host smart-7a6ddc62-3118-4734-8434-0f026141077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506715357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3506715357
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.466509206
Short name T544
Test name
Test status
Simulation time 28308125 ps
CPU time 0.76 seconds
Started Mar 07 12:43:47 PM PST 24
Finished Mar 07 12:43:48 PM PST 24
Peak memory 205220 kb
Host smart-1f69cd1a-0b68-404c-8948-4cfeb2b68541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466509206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.466509206
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2604326433
Short name T9
Test name
Test status
Simulation time 132259783182 ps
CPU time 153.98 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:46:30 PM PST 24
Peak memory 247112 kb
Host smart-ad552248-5158-4a21-8774-120c9219614a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604326433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2604326433
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3758572093
Short name T1211
Test name
Test status
Simulation time 66696603724 ps
CPU time 90.84 seconds
Started Mar 07 02:46:24 PM PST 24
Finished Mar 07 02:47:55 PM PST 24
Peak memory 248448 kb
Host smart-d9d81156-6f27-44e7-8825-ffe9dde98e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758572093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3758572093
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.448051943
Short name T937
Test name
Test status
Simulation time 8079328582 ps
CPU time 73.63 seconds
Started Mar 07 02:46:21 PM PST 24
Finished Mar 07 02:47:35 PM PST 24
Peak memory 248336 kb
Host smart-cb5a19cd-52be-44be-8a20-1cfbb372d911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448051943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.448051943
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.675134216
Short name T1611
Test name
Test status
Simulation time 110841470494 ps
CPU time 443.74 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:51:31 PM PST 24
Peak memory 263852 kb
Host smart-51bfe2e6-5329-4e22-a8b7-4fbd5b4bdd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675134216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.675134216
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1750512593
Short name T96
Test name
Test status
Simulation time 23894793087 ps
CPU time 162.81 seconds
Started Mar 07 12:43:55 PM PST 24
Finished Mar 07 12:46:38 PM PST 24
Peak memory 241096 kb
Host smart-9cfcae75-f08a-4e2e-a7de-dc55334eb9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750512593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1750512593
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3943878907
Short name T1318
Test name
Test status
Simulation time 54476036190 ps
CPU time 140.28 seconds
Started Mar 07 02:46:20 PM PST 24
Finished Mar 07 02:48:40 PM PST 24
Peak memory 271608 kb
Host smart-325ee67a-ba3d-4b26-b460-783431b8afd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943878907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3943878907
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3800246306
Short name T963
Test name
Test status
Simulation time 12814310104 ps
CPU time 22.1 seconds
Started Mar 07 02:46:25 PM PST 24
Finished Mar 07 02:46:47 PM PST 24
Peak memory 233764 kb
Host smart-26af4234-9292-4cd9-a86f-9c1bf6edf366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800246306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3800246306
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4231398787
Short name T1806
Test name
Test status
Simulation time 8582251109 ps
CPU time 42.51 seconds
Started Mar 07 12:43:58 PM PST 24
Finished Mar 07 12:44:41 PM PST 24
Peak memory 249492 kb
Host smart-5457b104-510c-42f8-9b2d-3031c07a1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231398787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4231398787
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2417229560
Short name T1438
Test name
Test status
Simulation time 317343458 ps
CPU time 3.94 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:00 PM PST 24
Peak memory 233800 kb
Host smart-3c3088c4-f5fa-4682-8218-3a7e1d87556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417229560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2417229560
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3778462962
Short name T1025
Test name
Test status
Simulation time 1647381095 ps
CPU time 2.89 seconds
Started Mar 07 02:46:22 PM PST 24
Finished Mar 07 02:46:26 PM PST 24
Peak memory 232092 kb
Host smart-7a95f507-60f8-4b9c-a5ce-aa5b80c96dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778462962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3778462962
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2307765733
Short name T1840
Test name
Test status
Simulation time 11737118370 ps
CPU time 43.1 seconds
Started Mar 07 12:43:55 PM PST 24
Finished Mar 07 12:44:39 PM PST 24
Peak memory 248448 kb
Host smart-de2cb9b5-0eb6-47bb-926b-0df391acd667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307765733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2307765733
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4148643882
Short name T1363
Test name
Test status
Simulation time 7516472968 ps
CPU time 21.47 seconds
Started Mar 07 02:46:20 PM PST 24
Finished Mar 07 02:46:42 PM PST 24
Peak memory 217072 kb
Host smart-59337cf1-3bc5-41ad-a6e9-67ef3d8a4073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148643882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4148643882
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2861214116
Short name T1791
Test name
Test status
Simulation time 1140944384 ps
CPU time 4.62 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:01 PM PST 24
Peak memory 216740 kb
Host smart-fee1617c-1a0b-4f92-937f-aa2a152ab488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861214116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2861214116
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3245761125
Short name T1789
Test name
Test status
Simulation time 2114439456 ps
CPU time 9.27 seconds
Started Mar 07 02:46:21 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 236772 kb
Host smart-0c1917aa-edc3-4a1a-accf-e2f33d44a4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245761125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3245761125
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.163842633
Short name T1549
Test name
Test status
Simulation time 173929451 ps
CPU time 3.4 seconds
Started Mar 07 12:43:53 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 224356 kb
Host smart-c5f3e57c-0ea3-456a-bee3-c695ef8a1534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163842633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.163842633
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3006521049
Short name T226
Test name
Test status
Simulation time 13532845622 ps
CPU time 6.04 seconds
Started Mar 07 02:46:21 PM PST 24
Finished Mar 07 02:46:27 PM PST 24
Peak memory 216340 kb
Host smart-b5fa73e0-3b7c-4afd-a90b-6455bfdc3417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006521049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3006521049
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2765180049
Short name T1437
Test name
Test status
Simulation time 626235093 ps
CPU time 4.47 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 219148 kb
Host smart-056eb97a-fa1f-4c64-89e1-e2492f62b55b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2765180049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2765180049
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3360536127
Short name T713
Test name
Test status
Simulation time 383019232 ps
CPU time 3.58 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 218868 kb
Host smart-8c3560e8-5667-4274-a205-d689c4f323f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3360536127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3360536127
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3011725804
Short name T1391
Test name
Test status
Simulation time 280571228068 ps
CPU time 518.42 seconds
Started Mar 07 02:46:20 PM PST 24
Finished Mar 07 02:54:59 PM PST 24
Peak memory 278728 kb
Host smart-615a74c8-21dd-4ff8-8aca-fcc68e1c8c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011725804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3011725804
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4180454396
Short name T1372
Test name
Test status
Simulation time 62948423949 ps
CPU time 411.97 seconds
Started Mar 07 12:43:57 PM PST 24
Finished Mar 07 12:50:49 PM PST 24
Peak memory 265488 kb
Host smart-a027ce9d-6098-48fa-bb5f-9770ec0df8d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180454396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4180454396
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1948634139
Short name T1114
Test name
Test status
Simulation time 1059036490 ps
CPU time 9.88 seconds
Started Mar 07 12:43:55 PM PST 24
Finished Mar 07 12:44:05 PM PST 24
Peak memory 216200 kb
Host smart-c9b71cb6-5865-40b3-8251-2be4690700d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948634139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1948634139
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1966657863
Short name T40
Test name
Test status
Simulation time 1243469656 ps
CPU time 17.82 seconds
Started Mar 07 02:46:23 PM PST 24
Finished Mar 07 02:46:41 PM PST 24
Peak memory 215780 kb
Host smart-683876de-8347-4c16-829f-327d20f85865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966657863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1966657863
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3573386024
Short name T493
Test name
Test status
Simulation time 1499314013 ps
CPU time 4.51 seconds
Started Mar 07 02:46:22 PM PST 24
Finished Mar 07 02:46:27 PM PST 24
Peak memory 215616 kb
Host smart-2cf03eb4-b0cf-4599-8f61-b203756313b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573386024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3573386024
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4260114513
Short name T992
Test name
Test status
Simulation time 1393469003 ps
CPU time 3.71 seconds
Started Mar 07 12:43:51 PM PST 24
Finished Mar 07 12:43:55 PM PST 24
Peak memory 216124 kb
Host smart-9bccffe2-d2e0-4747-96ae-db7da1e52859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260114513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4260114513
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1753461926
Short name T636
Test name
Test status
Simulation time 381346202 ps
CPU time 14.34 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:46:42 PM PST 24
Peak memory 215788 kb
Host smart-4a8ec229-319d-4cbf-a583-984d3b6d4dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753461926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1753461926
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2526091221
Short name T4
Test name
Test status
Simulation time 218130159 ps
CPU time 3.33 seconds
Started Mar 07 12:43:57 PM PST 24
Finished Mar 07 12:44:00 PM PST 24
Peak memory 216188 kb
Host smart-e8348c6a-6ef4-4117-8c8f-b4ad6b11709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526091221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2526091221
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2548468106
Short name T1626
Test name
Test status
Simulation time 14809784 ps
CPU time 0.69 seconds
Started Mar 07 12:43:53 PM PST 24
Finished Mar 07 12:43:54 PM PST 24
Peak memory 205468 kb
Host smart-79247ca2-abcb-44c1-8b5c-9019c698ce87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548468106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2548468106
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2752381988
Short name T1748
Test name
Test status
Simulation time 225887311 ps
CPU time 0.94 seconds
Started Mar 07 02:46:19 PM PST 24
Finished Mar 07 02:46:21 PM PST 24
Peak memory 204888 kb
Host smart-afa335b3-47d4-4ad4-9396-16103e44187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752381988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2752381988
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2710353156
Short name T1457
Test name
Test status
Simulation time 543460492 ps
CPU time 8.07 seconds
Started Mar 07 02:46:21 PM PST 24
Finished Mar 07 02:46:30 PM PST 24
Peak memory 232740 kb
Host smart-3ad26d8a-0633-42d0-80f3-c35b47a270f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710353156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2710353156
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3386261827
Short name T1010
Test name
Test status
Simulation time 18478938 ps
CPU time 0.7 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:46:30 PM PST 24
Peak memory 204440 kb
Host smart-12d09481-08e2-44df-ba7f-dda3da64a035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386261827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3386261827
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.788412165
Short name T1640
Test name
Test status
Simulation time 22356231 ps
CPU time 0.72 seconds
Started Mar 07 12:43:59 PM PST 24
Finished Mar 07 12:44:00 PM PST 24
Peak memory 204556 kb
Host smart-4c854ef8-6975-4e98-a865-c34a95bdd4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788412165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.788412165
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1408209614
Short name T877
Test name
Test status
Simulation time 248956932 ps
CPU time 3.21 seconds
Started Mar 07 12:43:58 PM PST 24
Finished Mar 07 12:44:02 PM PST 24
Peak memory 233072 kb
Host smart-28593191-d051-4a5d-873b-9e240f3a521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408209614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1408209614
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.161677145
Short name T1243
Test name
Test status
Simulation time 125939405 ps
CPU time 2.66 seconds
Started Mar 07 02:46:29 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 233072 kb
Host smart-e3f7f866-b102-4f17-9b51-4a63a3d2419a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161677145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.161677145
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.372536140
Short name T331
Test name
Test status
Simulation time 40494381 ps
CPU time 0.77 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:44:07 PM PST 24
Peak memory 205192 kb
Host smart-b81e6bfd-51cc-41cc-8e22-3d661c62f195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372536140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.372536140
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4244112713
Short name T528
Test name
Test status
Simulation time 67255075 ps
CPU time 0.77 seconds
Started Mar 07 02:46:21 PM PST 24
Finished Mar 07 02:46:23 PM PST 24
Peak memory 205948 kb
Host smart-75c33127-ce49-480a-9505-e01ddb29a889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244112713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4244112713
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2283218153
Short name T1884
Test name
Test status
Simulation time 29160589254 ps
CPU time 114.53 seconds
Started Mar 07 12:43:59 PM PST 24
Finished Mar 07 12:45:54 PM PST 24
Peak memory 257240 kb
Host smart-5b93f84d-b7cd-4edc-a246-0e4b14caab67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283218153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2283218153
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3625252860
Short name T1523
Test name
Test status
Simulation time 16654000737 ps
CPU time 35.95 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:47:04 PM PST 24
Peak memory 248556 kb
Host smart-1ac63639-ef62-4087-ac72-06633a530fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625252860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3625252860
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.156566259
Short name T836
Test name
Test status
Simulation time 98007058607 ps
CPU time 390.63 seconds
Started Mar 07 02:46:30 PM PST 24
Finished Mar 07 02:53:01 PM PST 24
Peak memory 251320 kb
Host smart-73402adc-522c-4fac-b5ec-ec6830bb08d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156566259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.156566259
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2000391848
Short name T1864
Test name
Test status
Simulation time 137877193553 ps
CPU time 227.04 seconds
Started Mar 07 12:44:03 PM PST 24
Finished Mar 07 12:47:50 PM PST 24
Peak memory 256536 kb
Host smart-cef48914-af2f-4e01-8522-11a5a67d185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000391848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2000391848
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4294566496
Short name T639
Test name
Test status
Simulation time 44625098087 ps
CPU time 223.85 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:50:12 PM PST 24
Peak memory 264476 kb
Host smart-0764cc54-4713-4654-996e-f41b273f8b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294566496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4294566496
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.655011471
Short name T797
Test name
Test status
Simulation time 37559243115 ps
CPU time 79.48 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:45:13 PM PST 24
Peak memory 239484 kb
Host smart-5e4937a3-bab9-40ed-8b80-7bbbfa76257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655011471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.655011471
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2116384012
Short name T1650
Test name
Test status
Simulation time 4072391715 ps
CPU time 20.53 seconds
Started Mar 07 02:46:31 PM PST 24
Finished Mar 07 02:46:52 PM PST 24
Peak memory 232556 kb
Host smart-c5c937ed-ce64-4a73-8869-963c2954a93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116384012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2116384012
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.804378240
Short name T1265
Test name
Test status
Simulation time 183100511 ps
CPU time 7.97 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:04 PM PST 24
Peak memory 221492 kb
Host smart-babec62b-d66f-4858-81bb-c0e7de13869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804378240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.804378240
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1829644072
Short name T1745
Test name
Test status
Simulation time 4577340163 ps
CPU time 14.56 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:10 PM PST 24
Peak memory 233584 kb
Host smart-c7526c58-d640-4d6c-967c-ee2836ef8333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829644072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1829644072
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2100778722
Short name T1485
Test name
Test status
Simulation time 3092442769 ps
CPU time 4.46 seconds
Started Mar 07 02:46:29 PM PST 24
Finished Mar 07 02:46:33 PM PST 24
Peak memory 223960 kb
Host smart-58f0b66a-dec8-4a42-ae8b-f41c355ec357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100778722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2100778722
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2844363006
Short name T1240
Test name
Test status
Simulation time 9172539314 ps
CPU time 7.98 seconds
Started Mar 07 02:46:29 PM PST 24
Finished Mar 07 02:46:37 PM PST 24
Peak memory 238772 kb
Host smart-7ca2aae7-e28e-4e55-8e60-9a9628cb09fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844363006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2844363006
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4266809806
Short name T513
Test name
Test status
Simulation time 27740758277 ps
CPU time 20.17 seconds
Started Mar 07 12:43:57 PM PST 24
Finished Mar 07 12:44:17 PM PST 24
Peak memory 235484 kb
Host smart-525c798f-5b4b-41ed-848c-efea5349b708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266809806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4266809806
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2235154321
Short name T618
Test name
Test status
Simulation time 1078100305 ps
CPU time 7.34 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:03 PM PST 24
Peak memory 219820 kb
Host smart-92108ad4-d44d-41a8-b6fc-80a7c1bad70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235154321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2235154321
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3164197105
Short name T473
Test name
Test status
Simulation time 3379069754 ps
CPU time 13.49 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:46:41 PM PST 24
Peak memory 217048 kb
Host smart-9ed6b19a-0880-4f86-9bbb-18cf6fece2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164197105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3164197105
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2126481902
Short name T223
Test name
Test status
Simulation time 2338002697 ps
CPU time 10.3 seconds
Started Mar 07 12:43:55 PM PST 24
Finished Mar 07 12:44:06 PM PST 24
Peak memory 240488 kb
Host smart-1ee32711-0e49-4fe8-bfb2-661a8eca7c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126481902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2126481902
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2190924502
Short name T1137
Test name
Test status
Simulation time 12214927928 ps
CPU time 35.51 seconds
Started Mar 07 02:46:34 PM PST 24
Finished Mar 07 02:47:10 PM PST 24
Peak memory 246772 kb
Host smart-8abb6549-5b3a-49ef-8aa1-f4b983d75013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190924502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2190924502
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2342649059
Short name T435
Test name
Test status
Simulation time 235004646 ps
CPU time 3.61 seconds
Started Mar 07 12:43:57 PM PST 24
Finished Mar 07 12:44:01 PM PST 24
Peak memory 219712 kb
Host smart-a44613ff-cf93-4330-94c2-545cf2624e3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2342649059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2342649059
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4149858565
Short name T1782
Test name
Test status
Simulation time 199387889 ps
CPU time 3.91 seconds
Started Mar 07 02:46:29 PM PST 24
Finished Mar 07 02:46:33 PM PST 24
Peak memory 222200 kb
Host smart-08ea1c83-1e0f-4b1b-8f38-567548eda66a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149858565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4149858565
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4278521650
Short name T1224
Test name
Test status
Simulation time 14351611013 ps
CPU time 149.95 seconds
Started Mar 07 02:46:31 PM PST 24
Finished Mar 07 02:49:01 PM PST 24
Peak memory 253592 kb
Host smart-6c71dcde-ad21-45a6-9cda-81af98fefca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278521650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4278521650
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2353664906
Short name T1254
Test name
Test status
Simulation time 11098877084 ps
CPU time 54.45 seconds
Started Mar 07 12:44:03 PM PST 24
Finished Mar 07 12:44:58 PM PST 24
Peak memory 216272 kb
Host smart-2e73d2d8-d403-4082-b44c-ff30653a0aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353664906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2353664906
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.519039941
Short name T1305
Test name
Test status
Simulation time 4667271805 ps
CPU time 14.28 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:46:42 PM PST 24
Peak memory 215736 kb
Host smart-640ea390-5449-4509-a782-a8b5764b6193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519039941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.519039941
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3189925871
Short name T728
Test name
Test status
Simulation time 874236601 ps
CPU time 3.88 seconds
Started Mar 07 12:43:58 PM PST 24
Finished Mar 07 12:44:02 PM PST 24
Peak memory 216176 kb
Host smart-a2a20887-a81e-4277-bc50-3915e2ccf209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189925871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3189925871
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4044798393
Short name T381
Test name
Test status
Simulation time 9345304568 ps
CPU time 27.05 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:46:55 PM PST 24
Peak memory 215816 kb
Host smart-4c7468f1-d492-4d23-9b12-9fa3d04c49f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044798393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4044798393
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1644404884
Short name T437
Test name
Test status
Simulation time 224240257 ps
CPU time 10.57 seconds
Started Mar 07 02:46:32 PM PST 24
Finished Mar 07 02:46:43 PM PST 24
Peak memory 215748 kb
Host smart-af032998-fa2f-46ae-98b3-38de90ec4e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644404884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1644404884
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1721112737
Short name T1177
Test name
Test status
Simulation time 964536277 ps
CPU time 4.11 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 216256 kb
Host smart-279df7eb-da84-4480-a4a9-14d1cb824d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721112737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1721112737
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1121332808
Short name T344
Test name
Test status
Simulation time 212334735 ps
CPU time 0.87 seconds
Started Mar 07 12:43:58 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 205872 kb
Host smart-840567e8-8e0e-4e13-a9ee-03bb2f78af1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121332808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1121332808
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3283499912
Short name T1371
Test name
Test status
Simulation time 103165697 ps
CPU time 0.76 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:46:28 PM PST 24
Peak memory 204872 kb
Host smart-6fa574b8-4ac8-43d4-a4f9-c16692ea0401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283499912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3283499912
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1128455237
Short name T408
Test name
Test status
Simulation time 455195839 ps
CPU time 2.91 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 232508 kb
Host smart-2ea17039-862d-417f-864d-895988fbdc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128455237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1128455237
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_upload.3171553589
Short name T1016
Test name
Test status
Simulation time 11462209183 ps
CPU time 7.82 seconds
Started Mar 07 02:46:32 PM PST 24
Finished Mar 07 02:46:41 PM PST 24
Peak memory 218164 kb
Host smart-3659ee5b-2d04-43b5-979f-97b7a286810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171553589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3171553589
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1902116504
Short name T341
Test name
Test status
Simulation time 12864296 ps
CPU time 0.71 seconds
Started Mar 07 02:46:39 PM PST 24
Finished Mar 07 02:46:40 PM PST 24
Peak memory 204436 kb
Host smart-6d30a98e-a45f-4c8e-89ce-14cd322b4a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902116504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1902116504
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2875200817
Short name T840
Test name
Test status
Simulation time 62990984 ps
CPU time 0.69 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:44:07 PM PST 24
Peak memory 204480 kb
Host smart-53a16052-ebd3-4e91-8062-7edb9ad1a69b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875200817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2875200817
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4279646252
Short name T622
Test name
Test status
Simulation time 12743705362 ps
CPU time 12.73 seconds
Started Mar 07 02:46:32 PM PST 24
Finished Mar 07 02:46:46 PM PST 24
Peak memory 233264 kb
Host smart-bb1ed203-269e-443c-8744-66abdbba84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279646252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4279646252
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.469768386
Short name T1829
Test name
Test status
Simulation time 626308866 ps
CPU time 3.47 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 234612 kb
Host smart-12ceeb98-4dfe-4565-8a99-28f971724b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469768386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.469768386
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1478306651
Short name T1697
Test name
Test status
Simulation time 21986952 ps
CPU time 0.79 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 206616 kb
Host smart-03c99305-234a-4cd2-b61a-7e6819f1a524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478306651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1478306651
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2123689447
Short name T1076
Test name
Test status
Simulation time 21680869 ps
CPU time 0.79 seconds
Started Mar 07 02:46:31 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 205528 kb
Host smart-034eae44-c9ff-43fe-9b13-971d52209682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123689447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2123689447
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3447550333
Short name T649
Test name
Test status
Simulation time 136372831002 ps
CPU time 186.14 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:47:02 PM PST 24
Peak memory 251504 kb
Host smart-120d21fd-676b-41ce-bc9b-af0eec838c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447550333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3447550333
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.999185796
Short name T1168
Test name
Test status
Simulation time 103449170629 ps
CPU time 151.7 seconds
Started Mar 07 02:46:31 PM PST 24
Finished Mar 07 02:49:03 PM PST 24
Peak memory 256220 kb
Host smart-ce781154-80d3-4336-bf96-7871d147fbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999185796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.999185796
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1601515292
Short name T890
Test name
Test status
Simulation time 170238272898 ps
CPU time 86.22 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:47:54 PM PST 24
Peak memory 236856 kb
Host smart-96c995ec-160f-4027-9865-cbab2364518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601515292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1601515292
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1605243786
Short name T1800
Test name
Test status
Simulation time 39243234343 ps
CPU time 52.79 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:44:46 PM PST 24
Peak memory 252396 kb
Host smart-e6a6b70f-dccb-425d-a2a5-f652dadd0cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605243786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1605243786
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.526220836
Short name T1382
Test name
Test status
Simulation time 185403740182 ps
CPU time 298.23 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:48:53 PM PST 24
Peak memory 259380 kb
Host smart-84c519a1-ad7d-4709-a461-fe796e2cde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526220836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.526220836
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.643406901
Short name T1668
Test name
Test status
Simulation time 279076351069 ps
CPU time 500.99 seconds
Started Mar 07 02:46:41 PM PST 24
Finished Mar 07 02:55:02 PM PST 24
Peak memory 256436 kb
Host smart-e6a2b50b-dba7-46d8-ab4f-a9e69e7318de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643406901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.643406901
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1537800283
Short name T1765
Test name
Test status
Simulation time 10215006470 ps
CPU time 12.12 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:44:19 PM PST 24
Peak memory 235712 kb
Host smart-433ceebc-f7b1-43d8-9048-1ebc8b6a49da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537800283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1537800283
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3052351760
Short name T1777
Test name
Test status
Simulation time 315678294 ps
CPU time 6.97 seconds
Started Mar 07 02:46:27 PM PST 24
Finished Mar 07 02:46:34 PM PST 24
Peak memory 240188 kb
Host smart-d5fad85c-8f51-4e3d-8f41-0933f28c7b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052351760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3052351760
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.522318762
Short name T848
Test name
Test status
Simulation time 1152226689 ps
CPU time 4.23 seconds
Started Mar 07 02:46:27 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 223892 kb
Host smart-ef3b5711-ec7d-4c5e-8e15-7eb6997bf9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522318762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.522318762
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intercept.969202611
Short name T701
Test name
Test status
Simulation time 3382196964 ps
CPU time 12.13 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:08 PM PST 24
Peak memory 233788 kb
Host smart-fefaa1dd-8d7c-45ec-a4d4-140e40eb138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969202611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.969202611
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1982244290
Short name T561
Test name
Test status
Simulation time 509413491 ps
CPU time 4.64 seconds
Started Mar 07 12:43:59 PM PST 24
Finished Mar 07 12:44:04 PM PST 24
Peak memory 234652 kb
Host smart-e306453d-e3aa-49c0-8cfe-369ee0272cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982244290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1982244290
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2338696640
Short name T1316
Test name
Test status
Simulation time 1298996439 ps
CPU time 3.49 seconds
Started Mar 07 02:46:32 PM PST 24
Finished Mar 07 02:46:36 PM PST 24
Peak memory 232316 kb
Host smart-d7cb1efe-2804-44c9-b8be-5bef55594e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338696640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2338696640
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1608781963
Short name T478
Test name
Test status
Simulation time 5590541302 ps
CPU time 7.67 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:44:02 PM PST 24
Peak memory 218200 kb
Host smart-afbce9d7-55b5-450e-90fc-d942548dfaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608781963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1608781963
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2644819645
Short name T269
Test name
Test status
Simulation time 500394496 ps
CPU time 8.38 seconds
Started Mar 07 02:46:27 PM PST 24
Finished Mar 07 02:46:36 PM PST 24
Peak memory 239700 kb
Host smart-2ba62a5b-3074-49f7-a1aa-dd3fcd1a238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644819645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2644819645
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.221241316
Short name T1153
Test name
Test status
Simulation time 2307559184 ps
CPU time 12.15 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:08 PM PST 24
Peak memory 227860 kb
Host smart-8b65c815-918a-4831-b1a5-9d508baa92de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221241316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.221241316
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2318908858
Short name T881
Test name
Test status
Simulation time 9870039711 ps
CPU time 29.01 seconds
Started Mar 07 02:46:30 PM PST 24
Finished Mar 07 02:46:59 PM PST 24
Peak memory 223960 kb
Host smart-3baa7aca-9dc3-48fe-8105-922b620166fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318908858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2318908858
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4102632543
Short name T1093
Test name
Test status
Simulation time 5498981149 ps
CPU time 6.36 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:02 PM PST 24
Peak memory 222912 kb
Host smart-2dff5b99-2e54-499a-bc76-16d440b3945d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4102632543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4102632543
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.89354294
Short name T554
Test name
Test status
Simulation time 485449607 ps
CPU time 3.59 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:46:31 PM PST 24
Peak memory 221320 kb
Host smart-6a32b724-a510-4612-bfa6-207ea3b856ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=89354294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direc
t.89354294
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2882040911
Short name T1152
Test name
Test status
Simulation time 28806395056 ps
CPU time 67.93 seconds
Started Mar 07 02:46:42 PM PST 24
Finished Mar 07 02:47:50 PM PST 24
Peak memory 239236 kb
Host smart-38a3f8ba-d628-4c19-802d-eb1adfd8df90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882040911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2882040911
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3730641456
Short name T287
Test name
Test status
Simulation time 55324387421 ps
CPU time 348.72 seconds
Started Mar 07 12:43:55 PM PST 24
Finished Mar 07 12:49:44 PM PST 24
Peak memory 272844 kb
Host smart-5c63a36e-0f41-4922-af5f-a5febe82adaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730641456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3730641456
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2407446421
Short name T1535
Test name
Test status
Simulation time 12661402118 ps
CPU time 45.07 seconds
Started Mar 07 02:46:28 PM PST 24
Finished Mar 07 02:47:13 PM PST 24
Peak memory 215796 kb
Host smart-fc888d2c-2a0e-44d3-862b-c8abae7309e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407446421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2407446421
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4081821818
Short name T326
Test name
Test status
Simulation time 5032626842 ps
CPU time 14.78 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:44:11 PM PST 24
Peak memory 216324 kb
Host smart-8359761b-6c79-4a2b-80bf-9e9aaebfed9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081821818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4081821818
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2733632807
Short name T1833
Test name
Test status
Simulation time 1930087326 ps
CPU time 5.9 seconds
Started Mar 07 02:46:32 PM PST 24
Finished Mar 07 02:46:39 PM PST 24
Peak memory 207628 kb
Host smart-267d7f6f-f65c-470a-9d22-f20dc176c848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733632807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2733632807
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.693098615
Short name T1706
Test name
Test status
Simulation time 1258319611 ps
CPU time 3.11 seconds
Started Mar 07 12:43:55 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 216088 kb
Host smart-a1aa1680-4084-4bb8-bc64-267b644930be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693098615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.693098615
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2756852852
Short name T1740
Test name
Test status
Simulation time 913432774 ps
CPU time 2.35 seconds
Started Mar 07 02:46:29 PM PST 24
Finished Mar 07 02:46:31 PM PST 24
Peak memory 215868 kb
Host smart-de96421f-e26b-44d5-a29e-57c458f1126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756852852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2756852852
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.526348351
Short name T1209
Test name
Test status
Simulation time 86446207 ps
CPU time 1.08 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 207864 kb
Host smart-2dd18767-dfa7-42cf-b82b-ce939b9e170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526348351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.526348351
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4073088634
Short name T1860
Test name
Test status
Simulation time 93281973 ps
CPU time 1.04 seconds
Started Mar 07 12:43:54 PM PST 24
Finished Mar 07 12:43:56 PM PST 24
Peak memory 206536 kb
Host smart-fa7d7dec-b3b4-4bda-b6bc-25be9968e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073088634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4073088634
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.471051234
Short name T732
Test name
Test status
Simulation time 92794896 ps
CPU time 0.75 seconds
Started Mar 07 02:46:31 PM PST 24
Finished Mar 07 02:46:32 PM PST 24
Peak memory 204904 kb
Host smart-4f5922c2-dab0-465b-9434-884b4d31eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471051234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.471051234
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1462321779
Short name T1373
Test name
Test status
Simulation time 33234116298 ps
CPU time 28.24 seconds
Started Mar 07 02:46:32 PM PST 24
Finished Mar 07 02:47:02 PM PST 24
Peak memory 233216 kb
Host smart-9798f2a6-df95-4776-b146-a764ded317a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462321779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1462321779
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_upload.1831903236
Short name T545
Test name
Test status
Simulation time 3372174451 ps
CPU time 14.14 seconds
Started Mar 07 12:43:57 PM PST 24
Finished Mar 07 12:44:11 PM PST 24
Peak memory 249976 kb
Host smart-b010de6e-5c0f-4f3b-a36f-6356ee7615f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831903236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1831903236
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1247489901
Short name T1185
Test name
Test status
Simulation time 24363556 ps
CPU time 0.74 seconds
Started Mar 07 12:45:18 PM PST 24
Finished Mar 07 12:45:20 PM PST 24
Peak memory 203240 kb
Host smart-47a7ab09-4282-48aa-b65f-6367fb1a7430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247489901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1247489901
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1432453570
Short name T693
Test name
Test status
Simulation time 43201438 ps
CPU time 0.73 seconds
Started Mar 07 02:46:40 PM PST 24
Finished Mar 07 02:46:41 PM PST 24
Peak memory 204456 kb
Host smart-db2a744a-0ec0-497f-8ac6-5bc61ffbeb64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432453570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1432453570
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1129268189
Short name T1027
Test name
Test status
Simulation time 162165909 ps
CPU time 3.53 seconds
Started Mar 07 02:46:40 PM PST 24
Finished Mar 07 02:46:44 PM PST 24
Peak memory 223796 kb
Host smart-6144d0b7-6898-43da-95e1-24e90f091258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129268189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1129268189
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4129686801
Short name T720
Test name
Test status
Simulation time 149227385 ps
CPU time 2.48 seconds
Started Mar 07 12:44:03 PM PST 24
Finished Mar 07 12:44:05 PM PST 24
Peak memory 218508 kb
Host smart-0243f781-e125-4c90-b83b-b3e0c08dd039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129686801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4129686801
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3440731573
Short name T327
Test name
Test status
Simulation time 13298953 ps
CPU time 0.82 seconds
Started Mar 07 12:43:56 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 205292 kb
Host smart-6d65ee77-2102-40e4-bff2-9a1a92034ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440731573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3440731573
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3465669201
Short name T330
Test name
Test status
Simulation time 34992422 ps
CPU time 0.8 seconds
Started Mar 07 02:46:41 PM PST 24
Finished Mar 07 02:46:43 PM PST 24
Peak memory 205448 kb
Host smart-beb52f18-3817-4f9c-ad35-9a7400afd26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465669201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3465669201
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.144363436
Short name T932
Test name
Test status
Simulation time 76392671913 ps
CPU time 84.78 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:45:31 PM PST 24
Peak memory 250348 kb
Host smart-421f575f-c567-46c3-b1ad-829a8ceffb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144363436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.144363436
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4040941290
Short name T25
Test name
Test status
Simulation time 8424026090 ps
CPU time 29.42 seconds
Started Mar 07 02:46:42 PM PST 24
Finished Mar 07 02:47:12 PM PST 24
Peak memory 248572 kb
Host smart-fafc524d-380a-443c-954f-320b8912afdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040941290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4040941290
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3067747162
Short name T1107
Test name
Test status
Simulation time 5162336417 ps
CPU time 44.38 seconds
Started Mar 07 12:44:05 PM PST 24
Finished Mar 07 12:44:50 PM PST 24
Peak memory 240912 kb
Host smart-4c41bd65-c7f5-403f-b8ef-68c24d91123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067747162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3067747162
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.365127935
Short name T1604
Test name
Test status
Simulation time 15336205112 ps
CPU time 123.64 seconds
Started Mar 07 02:46:42 PM PST 24
Finished Mar 07 02:48:46 PM PST 24
Peak memory 239136 kb
Host smart-5144787b-2b33-4218-ab73-3f96644e43a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365127935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.365127935
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1767383028
Short name T21
Test name
Test status
Simulation time 110316544856 ps
CPU time 205.34 seconds
Started Mar 07 02:46:40 PM PST 24
Finished Mar 07 02:50:05 PM PST 24
Peak memory 251276 kb
Host smart-4f3ce612-9213-4e2c-b876-2a1168b7c421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767383028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1767383028
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3123885009
Short name T1135
Test name
Test status
Simulation time 79078802386 ps
CPU time 122.8 seconds
Started Mar 07 12:45:18 PM PST 24
Finished Mar 07 12:47:22 PM PST 24
Peak memory 255152 kb
Host smart-8228f0fd-30e3-41b3-a102-8790456801e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123885009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3123885009
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1632134063
Short name T1900
Test name
Test status
Simulation time 4413930248 ps
CPU time 19.21 seconds
Started Mar 07 12:44:04 PM PST 24
Finished Mar 07 12:44:24 PM PST 24
Peak memory 249020 kb
Host smart-f7ab6fbc-3718-4ee8-9acd-ae0eb41b0210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632134063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1632134063
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.17753918
Short name T1581
Test name
Test status
Simulation time 292743821 ps
CPU time 11.31 seconds
Started Mar 07 02:46:43 PM PST 24
Finished Mar 07 02:46:54 PM PST 24
Peak memory 238524 kb
Host smart-00755379-98bf-4926-8fa9-ad914acab073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17753918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.17753918
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1363228250
Short name T1898
Test name
Test status
Simulation time 3997835002 ps
CPU time 5.12 seconds
Started Mar 07 12:44:11 PM PST 24
Finished Mar 07 12:44:16 PM PST 24
Peak memory 224452 kb
Host smart-372245b3-6feb-4cde-9b46-6ba32879b998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363228250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1363228250
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1382378687
Short name T918
Test name
Test status
Simulation time 1447324308 ps
CPU time 6.3 seconds
Started Mar 07 02:46:40 PM PST 24
Finished Mar 07 02:46:46 PM PST 24
Peak memory 223784 kb
Host smart-c1011916-261c-4439-b1a4-1ee8963c335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382378687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1382378687
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1202384251
Short name T825
Test name
Test status
Simulation time 390005292 ps
CPU time 2.3 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:44:08 PM PST 24
Peak memory 218408 kb
Host smart-b86a32d3-bf92-424f-ac76-172b3f328bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202384251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1202384251
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2507118885
Short name T767
Test name
Test status
Simulation time 3409171122 ps
CPU time 22.2 seconds
Started Mar 07 02:46:42 PM PST 24
Finished Mar 07 02:47:05 PM PST 24
Peak memory 248084 kb
Host smart-b02b58ac-c3c0-4827-b845-ced5c107267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507118885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2507118885
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2740222605
Short name T401
Test name
Test status
Simulation time 16430540339 ps
CPU time 12.6 seconds
Started Mar 07 12:44:03 PM PST 24
Finished Mar 07 12:44:16 PM PST 24
Peak memory 224616 kb
Host smart-98b556f4-0195-471f-ab35-75ecf6702892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740222605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2740222605
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.693380564
Short name T32
Test name
Test status
Simulation time 446143178 ps
CPU time 6.69 seconds
Started Mar 07 02:46:43 PM PST 24
Finished Mar 07 02:46:49 PM PST 24
Peak memory 218240 kb
Host smart-29181f23-7097-4912-ab82-fb3a06693828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693380564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.693380564
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2146698098
Short name T716
Test name
Test status
Simulation time 1438136280 ps
CPU time 3.01 seconds
Started Mar 07 02:46:40 PM PST 24
Finished Mar 07 02:46:43 PM PST 24
Peak memory 215952 kb
Host smart-93430033-7e8b-45e3-ab09-13116708413e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146698098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2146698098
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2445041731
Short name T1324
Test name
Test status
Simulation time 6316042176 ps
CPU time 17.41 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:44:24 PM PST 24
Peak memory 234696 kb
Host smart-5f689413-a343-401a-bd94-6cce2ebda0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445041731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2445041731
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2879965242
Short name T1133
Test name
Test status
Simulation time 2879293470 ps
CPU time 4.96 seconds
Started Mar 07 12:44:04 PM PST 24
Finished Mar 07 12:44:09 PM PST 24
Peak memory 220212 kb
Host smart-19037c50-b6c2-4453-9fc4-d1a874675594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2879965242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2879965242
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3722654578
Short name T846
Test name
Test status
Simulation time 318019876 ps
CPU time 3.95 seconds
Started Mar 07 02:46:37 PM PST 24
Finished Mar 07 02:46:42 PM PST 24
Peak memory 221496 kb
Host smart-add1c833-300e-4b6d-8ec9-35dbc963f6f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3722654578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3722654578
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2216910764
Short name T668
Test name
Test status
Simulation time 58411982 ps
CPU time 0.83 seconds
Started Mar 07 02:46:41 PM PST 24
Finished Mar 07 02:46:42 PM PST 24
Peak memory 204876 kb
Host smart-748ba63f-c86d-45fe-bd2e-16d55b6304c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216910764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2216910764
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3326179259
Short name T143
Test name
Test status
Simulation time 4508618574 ps
CPU time 87.39 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:45:34 PM PST 24
Peak memory 254168 kb
Host smart-4587562c-65c8-421a-8156-5e867f424258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326179259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3326179259
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1037641073
Short name T424
Test name
Test status
Simulation time 16504136717 ps
CPU time 77.39 seconds
Started Mar 07 12:44:03 PM PST 24
Finished Mar 07 12:45:21 PM PST 24
Peak memory 216316 kb
Host smart-3eb796e9-9e29-4d19-8400-7c4a1c949a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037641073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1037641073
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2809382591
Short name T1769
Test name
Test status
Simulation time 6435576410 ps
CPU time 10.54 seconds
Started Mar 07 02:46:44 PM PST 24
Finished Mar 07 02:46:54 PM PST 24
Peak memory 215876 kb
Host smart-f819bb9f-773b-4ec9-a938-5cf7d8efd234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809382591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2809382591
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2497599008
Short name T1034
Test name
Test status
Simulation time 4347602633 ps
CPU time 6.82 seconds
Started Mar 07 12:43:55 PM PST 24
Finished Mar 07 12:44:02 PM PST 24
Peak memory 216124 kb
Host smart-d8cf2e8c-004e-4f11-b46f-b5e56e575d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497599008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2497599008
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4049013176
Short name T570
Test name
Test status
Simulation time 20171005003 ps
CPU time 15.84 seconds
Started Mar 07 02:46:41 PM PST 24
Finished Mar 07 02:46:57 PM PST 24
Peak memory 215688 kb
Host smart-49cc9156-f06d-4b7e-b332-e6f4ceb9c68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049013176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4049013176
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.152228659
Short name T1441
Test name
Test status
Simulation time 72671630 ps
CPU time 1.93 seconds
Started Mar 07 12:44:11 PM PST 24
Finished Mar 07 12:44:13 PM PST 24
Peak memory 207768 kb
Host smart-1df3a603-35d1-4713-824a-9526991c46c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152228659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.152228659
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3345810685
Short name T498
Test name
Test status
Simulation time 48806785 ps
CPU time 0.81 seconds
Started Mar 07 02:46:42 PM PST 24
Finished Mar 07 02:46:43 PM PST 24
Peak memory 204924 kb
Host smart-8866f83e-f70f-4e78-8e06-3ca24e776846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345810685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3345810685
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.780839123
Short name T827
Test name
Test status
Simulation time 185063678 ps
CPU time 0.83 seconds
Started Mar 07 02:46:40 PM PST 24
Finished Mar 07 02:46:41 PM PST 24
Peak memory 204904 kb
Host smart-85662fb2-3978-4f36-8254-9c411fa7d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780839123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.780839123
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.948477638
Short name T400
Test name
Test status
Simulation time 135377882 ps
CPU time 0.86 seconds
Started Mar 07 12:43:57 PM PST 24
Finished Mar 07 12:43:58 PM PST 24
Peak memory 205376 kb
Host smart-c8e91a16-38ed-4933-a489-480359bbc1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948477638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.948477638
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.416824627
Short name T1734
Test name
Test status
Simulation time 15976927844 ps
CPU time 12.99 seconds
Started Mar 07 02:46:37 PM PST 24
Finished Mar 07 02:46:51 PM PST 24
Peak memory 232096 kb
Host smart-c49e5eb1-b304-487a-914f-932d165b470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416824627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.416824627
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_upload.976101635
Short name T795
Test name
Test status
Simulation time 1312480853 ps
CPU time 4.37 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:44:11 PM PST 24
Peak memory 221948 kb
Host smart-d14df12e-6ec1-4e26-aeb4-01d59954da2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976101635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.976101635
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3065830819
Short name T1103
Test name
Test status
Simulation time 13569143 ps
CPU time 0.72 seconds
Started Mar 07 02:46:47 PM PST 24
Finished Mar 07 02:46:48 PM PST 24
Peak memory 204372 kb
Host smart-f8b9434c-4e23-4577-b7ea-17a26221c07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065830819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3065830819
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4191125486
Short name T441
Test name
Test status
Simulation time 14460555 ps
CPU time 0.78 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:44:07 PM PST 24
Peak memory 205028 kb
Host smart-1bedd419-57b9-4b3c-97e5-06d6c6f434c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191125486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4191125486
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2451691971
Short name T929
Test name
Test status
Simulation time 2772393657 ps
CPU time 5.87 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:44:13 PM PST 24
Peak memory 219676 kb
Host smart-d3c92d0d-3ec7-4897-a633-20db5ae24962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451691971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2451691971
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4263499094
Short name T229
Test name
Test status
Simulation time 158448283 ps
CPU time 3.04 seconds
Started Mar 07 02:46:40 PM PST 24
Finished Mar 07 02:46:44 PM PST 24
Peak memory 233280 kb
Host smart-9b1b7725-3da3-4a0b-a960-883237ddc1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263499094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4263499094
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2636823295
Short name T1601
Test name
Test status
Simulation time 48673158 ps
CPU time 0.74 seconds
Started Mar 07 02:46:41 PM PST 24
Finished Mar 07 02:46:42 PM PST 24
Peak memory 204828 kb
Host smart-20839a38-95d4-4c8c-a300-7bdb5c4be529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636823295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2636823295
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3134384591
Short name T748
Test name
Test status
Simulation time 17027831 ps
CPU time 0.78 seconds
Started Mar 07 12:44:03 PM PST 24
Finished Mar 07 12:44:04 PM PST 24
Peak memory 205252 kb
Host smart-72835a9b-acab-4bc3-befa-a0268d21b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134384591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3134384591
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3448340859
Short name T696
Test name
Test status
Simulation time 11155094627 ps
CPU time 47.87 seconds
Started Mar 07 12:44:04 PM PST 24
Finished Mar 07 12:44:52 PM PST 24
Peak memory 252036 kb
Host smart-b34f3780-ec19-4aff-aeb5-9e688f24a6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448340859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3448340859
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3846711485
Short name T857
Test name
Test status
Simulation time 5189068928 ps
CPU time 50.81 seconds
Started Mar 07 02:46:49 PM PST 24
Finished Mar 07 02:47:40 PM PST 24
Peak memory 248364 kb
Host smart-7844a0b7-00a9-4dc3-af03-c233412d0ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846711485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3846711485
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2168872208
Short name T1315
Test name
Test status
Simulation time 73009805158 ps
CPU time 100.69 seconds
Started Mar 07 02:46:51 PM PST 24
Finished Mar 07 02:48:32 PM PST 24
Peak memory 233236 kb
Host smart-31ac1377-8484-441c-815a-c8b315171fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168872208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2168872208
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2468764454
Short name T1204
Test name
Test status
Simulation time 11504792908 ps
CPU time 73.38 seconds
Started Mar 07 12:44:04 PM PST 24
Finished Mar 07 12:45:18 PM PST 24
Peak memory 249244 kb
Host smart-05caa148-7996-41bd-90da-d8316915d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468764454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2468764454
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1823906219
Short name T1730
Test name
Test status
Simulation time 30591090354 ps
CPU time 183.26 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:47:10 PM PST 24
Peak memory 239896 kb
Host smart-860eddc5-f512-48f1-a675-f85c7bb52fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823906219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1823906219
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.600021182
Short name T427
Test name
Test status
Simulation time 9023444306 ps
CPU time 43.57 seconds
Started Mar 07 02:47:00 PM PST 24
Finished Mar 07 02:47:44 PM PST 24
Peak memory 240104 kb
Host smart-2fd0c54c-a1fc-4053-9cee-7e044c01154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600021182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.600021182
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1667528211
Short name T1392
Test name
Test status
Simulation time 2548692604 ps
CPU time 19.87 seconds
Started Mar 07 02:46:48 PM PST 24
Finished Mar 07 02:47:08 PM PST 24
Peak memory 243188 kb
Host smart-a9623aea-d760-49b1-8998-4c828371962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667528211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1667528211
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1918947175
Short name T459
Test name
Test status
Simulation time 645292306 ps
CPU time 13.2 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:44:20 PM PST 24
Peak memory 245272 kb
Host smart-77e83344-9409-41d1-8852-adb75c6d5c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918947175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1918947175
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3338296988
Short name T599
Test name
Test status
Simulation time 800394985 ps
CPU time 4.94 seconds
Started Mar 07 02:46:42 PM PST 24
Finished Mar 07 02:46:47 PM PST 24
Peak memory 234224 kb
Host smart-ff85efe8-f538-4128-8923-847c46d1ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338296988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3338296988
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3774377666
Short name T215
Test name
Test status
Simulation time 421591219 ps
CPU time 5.62 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:44:13 PM PST 24
Peak memory 233492 kb
Host smart-db8e10cf-7d42-4a4c-9cc2-15d16842540f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774377666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3774377666
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1534776593
Short name T1343
Test name
Test status
Simulation time 4017490028 ps
CPU time 5.65 seconds
Started Mar 07 02:46:39 PM PST 24
Finished Mar 07 02:46:45 PM PST 24
Peak memory 234144 kb
Host smart-16dcfa7d-add3-47a6-8736-6902e607d8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534776593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1534776593
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.377534189
Short name T782
Test name
Test status
Simulation time 115461827 ps
CPU time 2.51 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:44:10 PM PST 24
Peak memory 232660 kb
Host smart-3b7ae494-f0c1-4d22-8fde-f5921e254fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377534189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.377534189
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2999098226
Short name T581
Test name
Test status
Simulation time 928674882 ps
CPU time 5.28 seconds
Started Mar 07 12:44:08 PM PST 24
Finished Mar 07 12:44:13 PM PST 24
Peak memory 233660 kb
Host smart-218f1c45-024e-424a-9259-c51cb879a359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999098226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2999098226
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3462794059
Short name T300
Test name
Test status
Simulation time 5005631720 ps
CPU time 8.14 seconds
Started Mar 07 02:46:37 PM PST 24
Finished Mar 07 02:46:46 PM PST 24
Peak memory 227748 kb
Host smart-c844a67f-c06d-4e0e-86e3-511df7453a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462794059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3462794059
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.11335947
Short name T845
Test name
Test status
Simulation time 386670729 ps
CPU time 6.39 seconds
Started Mar 07 12:44:07 PM PST 24
Finished Mar 07 12:44:14 PM PST 24
Peak memory 223600 kb
Host smart-474f492f-2eb4-4e3b-9002-f1ec90eb8698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11335947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.11335947
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.50066380
Short name T240
Test name
Test status
Simulation time 11928936821 ps
CPU time 14.92 seconds
Started Mar 07 02:46:43 PM PST 24
Finished Mar 07 02:46:58 PM PST 24
Peak memory 236332 kb
Host smart-2069f9f3-c53d-4d9e-9732-6d8b3db65275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50066380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.50066380
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2083475646
Short name T86
Test name
Test status
Simulation time 989264361 ps
CPU time 3.47 seconds
Started Mar 07 12:44:04 PM PST 24
Finished Mar 07 12:44:08 PM PST 24
Peak memory 220024 kb
Host smart-22c3038d-4b01-4339-8a4f-6a0af3f7e401
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2083475646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2083475646
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4015262309
Short name T772
Test name
Test status
Simulation time 465926714 ps
CPU time 3.4 seconds
Started Mar 07 02:46:52 PM PST 24
Finished Mar 07 02:46:56 PM PST 24
Peak memory 218348 kb
Host smart-9dcff8ad-a1b1-4fb7-a168-94524d5c3589
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4015262309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4015262309
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2004404137
Short name T1673
Test name
Test status
Simulation time 17015104278 ps
CPU time 106.28 seconds
Started Mar 07 12:44:10 PM PST 24
Finished Mar 07 12:45:57 PM PST 24
Peak memory 251156 kb
Host smart-2b8aa887-8658-4672-a71f-9fc09fddb593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004404137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2004404137
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3411947479
Short name T56
Test name
Test status
Simulation time 38918320745 ps
CPU time 232.67 seconds
Started Mar 07 02:46:48 PM PST 24
Finished Mar 07 02:50:41 PM PST 24
Peak memory 289496 kb
Host smart-027a0030-242d-4e61-b8b5-063a023cd5d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411947479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3411947479
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2686338422
Short name T323
Test name
Test status
Simulation time 7916394684 ps
CPU time 38.93 seconds
Started Mar 07 12:44:08 PM PST 24
Finished Mar 07 12:44:47 PM PST 24
Peak memory 216300 kb
Host smart-2950415f-f745-4f90-a3fb-2f75a082ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686338422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2686338422
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4260111974
Short name T1364
Test name
Test status
Simulation time 16512966930 ps
CPU time 51.18 seconds
Started Mar 07 02:46:37 PM PST 24
Finished Mar 07 02:47:29 PM PST 24
Peak memory 215816 kb
Host smart-6532e29d-35b3-4e89-bb15-6bbae0c00126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260111974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4260111974
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2307985858
Short name T707
Test name
Test status
Simulation time 3616137401 ps
CPU time 11.53 seconds
Started Mar 07 02:46:38 PM PST 24
Finished Mar 07 02:46:50 PM PST 24
Peak memory 215788 kb
Host smart-f62ea2d2-d020-4a46-8025-a648bcee1889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307985858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2307985858
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3156508716
Short name T502
Test name
Test status
Simulation time 2123140699 ps
CPU time 8.95 seconds
Started Mar 07 12:44:05 PM PST 24
Finished Mar 07 12:44:15 PM PST 24
Peak memory 216060 kb
Host smart-1e16e326-9810-4720-ac6b-a5e676f7e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156508716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3156508716
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3572180643
Short name T1180
Test name
Test status
Simulation time 1820243907 ps
CPU time 5.8 seconds
Started Mar 07 12:44:05 PM PST 24
Finished Mar 07 12:44:11 PM PST 24
Peak memory 216496 kb
Host smart-a8eb1f70-7a29-4577-8a44-39cdaa23002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572180643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3572180643
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.539452475
Short name T1757
Test name
Test status
Simulation time 648621849 ps
CPU time 12.58 seconds
Started Mar 07 02:46:37 PM PST 24
Finished Mar 07 02:46:50 PM PST 24
Peak memory 215764 kb
Host smart-53eddb16-434c-4747-afa7-17ab7e6e458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539452475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.539452475
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.330659018
Short name T1395
Test name
Test status
Simulation time 90684793 ps
CPU time 0.97 seconds
Started Mar 07 02:46:39 PM PST 24
Finished Mar 07 02:46:40 PM PST 24
Peak memory 204860 kb
Host smart-72220e54-327d-4c78-80aa-1f948d0d2302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330659018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.330659018
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3806209791
Short name T386
Test name
Test status
Simulation time 76614327 ps
CPU time 0.78 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:44:07 PM PST 24
Peak memory 205376 kb
Host smart-be3baa54-ffc8-46e4-ba04-1ca2bb3aabbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806209791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3806209791
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4090492640
Short name T590
Test name
Test status
Simulation time 1905748059 ps
CPU time 14.33 seconds
Started Mar 07 02:46:40 PM PST 24
Finished Mar 07 02:46:55 PM PST 24
Peak memory 227740 kb
Host smart-0249a981-8650-4f45-a065-d7c8d7f53082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090492640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4090492640
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_upload.4159128527
Short name T507
Test name
Test status
Simulation time 707258310 ps
CPU time 4.25 seconds
Started Mar 07 12:44:05 PM PST 24
Finished Mar 07 12:44:09 PM PST 24
Peak memory 217460 kb
Host smart-6e174cb9-3688-4a83-badd-10b14f1c5c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159128527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4159128527
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2870375533
Short name T1539
Test name
Test status
Simulation time 15177041 ps
CPU time 0.79 seconds
Started Mar 07 02:47:00 PM PST 24
Finished Mar 07 02:47:01 PM PST 24
Peak memory 204212 kb
Host smart-d1da9a4f-477c-44f9-a4fc-e7b2039ad4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870375533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2870375533
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.662666760
Short name T1455
Test name
Test status
Simulation time 180141906 ps
CPU time 0.72 seconds
Started Mar 07 12:44:14 PM PST 24
Finished Mar 07 12:44:15 PM PST 24
Peak memory 205488 kb
Host smart-5d73f98f-15bc-4863-8116-21c9ff79cff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662666760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.662666760
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2887891142
Short name T968
Test name
Test status
Simulation time 571568184 ps
CPU time 5.87 seconds
Started Mar 07 12:44:17 PM PST 24
Finished Mar 07 12:44:23 PM PST 24
Peak memory 233656 kb
Host smart-db6f15f6-1b41-42b2-a53d-cb28437b86cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887891142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2887891142
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.293144029
Short name T232
Test name
Test status
Simulation time 745042365 ps
CPU time 4.43 seconds
Started Mar 07 02:46:46 PM PST 24
Finished Mar 07 02:46:50 PM PST 24
Peak memory 232948 kb
Host smart-1a46c582-ff87-49ad-8b75-032fe3ca7716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293144029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.293144029
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3393115732
Short name T730
Test name
Test status
Simulation time 48058441 ps
CPU time 0.75 seconds
Started Mar 07 02:46:46 PM PST 24
Finished Mar 07 02:46:47 PM PST 24
Peak memory 205864 kb
Host smart-6062f870-1101-4332-bc27-10fba4529a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393115732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3393115732
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4151079554
Short name T1039
Test name
Test status
Simulation time 41770489 ps
CPU time 0.74 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:44:07 PM PST 24
Peak memory 205196 kb
Host smart-16c5c4ec-d20a-4360-99be-3efadbf29e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151079554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4151079554
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3773448671
Short name T1690
Test name
Test status
Simulation time 3283774767 ps
CPU time 20.16 seconds
Started Mar 07 12:44:17 PM PST 24
Finished Mar 07 12:44:37 PM PST 24
Peak memory 240976 kb
Host smart-3a160fae-5daa-4791-95d0-48af943db208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773448671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3773448671
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.83586564
Short name T1300
Test name
Test status
Simulation time 67918223235 ps
CPU time 126.34 seconds
Started Mar 07 02:46:52 PM PST 24
Finished Mar 07 02:48:59 PM PST 24
Peak memory 262008 kb
Host smart-d117232b-3000-4b20-a989-de6501801b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83586564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.83586564
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1536195763
Short name T1487
Test name
Test status
Simulation time 1026833372555 ps
CPU time 519.94 seconds
Started Mar 07 02:46:46 PM PST 24
Finished Mar 07 02:55:27 PM PST 24
Peak memory 251548 kb
Host smart-26c45ba3-0446-4474-ac75-515eb25359eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536195763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1536195763
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.489648935
Short name T1555
Test name
Test status
Simulation time 9310700911 ps
CPU time 29.77 seconds
Started Mar 07 12:44:16 PM PST 24
Finished Mar 07 12:44:46 PM PST 24
Peak memory 232768 kb
Host smart-6b6720ac-b2d7-4367-9dcd-d876dc9c2ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489648935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.489648935
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2802525494
Short name T142
Test name
Test status
Simulation time 52581745151 ps
CPU time 140.61 seconds
Started Mar 07 02:47:00 PM PST 24
Finished Mar 07 02:49:21 PM PST 24
Peak memory 254308 kb
Host smart-cc158c15-5c0a-49e4-850a-4e84d6467a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802525494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2802525494
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4070536044
Short name T1239
Test name
Test status
Simulation time 90675736176 ps
CPU time 590.39 seconds
Started Mar 07 12:44:15 PM PST 24
Finished Mar 07 12:54:06 PM PST 24
Peak memory 249172 kb
Host smart-51e8e24a-6357-4c9a-8b5b-1d475efd1493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070536044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4070536044
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2274222269
Short name T1453
Test name
Test status
Simulation time 5067655647 ps
CPU time 32.18 seconds
Started Mar 07 02:46:46 PM PST 24
Finished Mar 07 02:47:18 PM PST 24
Peak memory 239568 kb
Host smart-20317834-4aa9-439c-b6d9-671a1d1fc9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274222269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2274222269
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2951676194
Short name T449
Test name
Test status
Simulation time 1478068250 ps
CPU time 11.9 seconds
Started Mar 07 12:44:17 PM PST 24
Finished Mar 07 12:44:29 PM PST 24
Peak memory 232676 kb
Host smart-ff8ee6ba-912c-4596-b37b-87e3f666cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951676194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2951676194
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2172161147
Short name T1277
Test name
Test status
Simulation time 492601814 ps
CPU time 4.68 seconds
Started Mar 07 12:45:25 PM PST 24
Finished Mar 07 12:45:30 PM PST 24
Peak memory 224276 kb
Host smart-9d9ceb27-422f-4c35-91bb-3cd53bcbdc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172161147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2172161147
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2936873392
Short name T256
Test name
Test status
Simulation time 1872360174 ps
CPU time 4.51 seconds
Started Mar 07 02:46:46 PM PST 24
Finished Mar 07 02:46:51 PM PST 24
Peak memory 218656 kb
Host smart-d831988a-8fd6-4bea-977b-c5c92aca5619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936873392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2936873392
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1713465393
Short name T683
Test name
Test status
Simulation time 1688579501 ps
CPU time 6.15 seconds
Started Mar 07 02:46:44 PM PST 24
Finished Mar 07 02:46:50 PM PST 24
Peak memory 238708 kb
Host smart-3a779102-6c4b-473e-8f10-fe6ae47697ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713465393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1713465393
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.225563166
Short name T516
Test name
Test status
Simulation time 10094186243 ps
CPU time 31.5 seconds
Started Mar 07 12:44:14 PM PST 24
Finished Mar 07 12:44:46 PM PST 24
Peak memory 234816 kb
Host smart-7bd68f70-1395-4248-9208-654dd4613411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225563166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.225563166
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2506175842
Short name T1755
Test name
Test status
Simulation time 460253216 ps
CPU time 5.06 seconds
Started Mar 07 02:46:45 PM PST 24
Finished Mar 07 02:46:50 PM PST 24
Peak memory 232488 kb
Host smart-0bca4aa6-332a-42c5-884d-b14242de7aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506175842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2506175842
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2904911361
Short name T869
Test name
Test status
Simulation time 6833373890 ps
CPU time 9.78 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:44:15 PM PST 24
Peak memory 229920 kb
Host smart-e92d1a35-8933-48d6-9fd9-210a4e3519f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904911361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2904911361
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1960714437
Short name T1683
Test name
Test status
Simulation time 7473111647 ps
CPU time 18.23 seconds
Started Mar 07 12:44:06 PM PST 24
Finished Mar 07 12:44:24 PM PST 24
Peak memory 217656 kb
Host smart-a17f5a08-aa22-430c-b242-7bed09b2c15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960714437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1960714437
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3450450106
Short name T1881
Test name
Test status
Simulation time 444644971 ps
CPU time 5.07 seconds
Started Mar 07 02:46:46 PM PST 24
Finished Mar 07 02:46:52 PM PST 24
Peak memory 216084 kb
Host smart-3226649e-8e8e-4102-a667-9c3ace490a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450450106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3450450106
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1926906662
Short name T643
Test name
Test status
Simulation time 745595311 ps
CPU time 5.09 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:44:23 PM PST 24
Peak memory 222776 kb
Host smart-bd3d21b1-88a5-4c72-9fe2-6c13b600f258
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1926906662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1926906662
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2837974399
Short name T1478
Test name
Test status
Simulation time 282009947 ps
CPU time 3.66 seconds
Started Mar 07 02:46:49 PM PST 24
Finished Mar 07 02:46:53 PM PST 24
Peak memory 221500 kb
Host smart-3d70f319-7e28-48d1-bae9-4b9b10bb69e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2837974399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2837974399
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3811954461
Short name T264
Test name
Test status
Simulation time 45370207789 ps
CPU time 358.92 seconds
Started Mar 07 02:46:47 PM PST 24
Finished Mar 07 02:52:46 PM PST 24
Peak memory 262020 kb
Host smart-3d602c05-381d-4ed1-b51a-53d743bc494b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811954461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3811954461
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2950376412
Short name T472
Test name
Test status
Simulation time 4053660679 ps
CPU time 26.12 seconds
Started Mar 07 02:46:46 PM PST 24
Finished Mar 07 02:47:12 PM PST 24
Peak memory 215940 kb
Host smart-83000370-3150-4eff-bf9a-24cf541adcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950376412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2950376412
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3631536177
Short name T1902
Test name
Test status
Simulation time 10437145544 ps
CPU time 16.37 seconds
Started Mar 07 12:44:04 PM PST 24
Finished Mar 07 12:44:21 PM PST 24
Peak memory 216280 kb
Host smart-5ecd33c1-e22c-4daf-91ff-105a5e594a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631536177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3631536177
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3708663959
Short name T1049
Test name
Test status
Simulation time 9946115387 ps
CPU time 18.59 seconds
Started Mar 07 02:47:00 PM PST 24
Finished Mar 07 02:47:19 PM PST 24
Peak memory 216276 kb
Host smart-270049c9-f09e-4294-beac-de3e397e9e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708663959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3708663959
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4267121741
Short name T1195
Test name
Test status
Simulation time 7930102561 ps
CPU time 13.09 seconds
Started Mar 07 12:44:08 PM PST 24
Finished Mar 07 12:44:21 PM PST 24
Peak memory 216264 kb
Host smart-2ae53c82-91a9-4bb0-81d9-e9bfe0f83d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267121741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4267121741
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3681857853
Short name T1889
Test name
Test status
Simulation time 45672197 ps
CPU time 0.81 seconds
Started Mar 07 02:47:00 PM PST 24
Finished Mar 07 02:47:01 PM PST 24
Peak memory 204680 kb
Host smart-14ae6141-a910-4d54-94e0-a74eb0d76c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681857853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3681857853
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3777066537
Short name T1022
Test name
Test status
Simulation time 88459946 ps
CPU time 1.46 seconds
Started Mar 07 12:44:11 PM PST 24
Finished Mar 07 12:44:12 PM PST 24
Peak memory 216176 kb
Host smart-c153445c-4bb8-40be-b557-75307130aa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777066537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3777066537
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.171571474
Short name T383
Test name
Test status
Simulation time 203971028 ps
CPU time 0.93 seconds
Started Mar 07 12:45:18 PM PST 24
Finished Mar 07 12:45:20 PM PST 24
Peak memory 203512 kb
Host smart-b1fc2ab1-de7f-4bf4-bb8e-8175aab3a80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171571474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.171571474
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.361719955
Short name T1174
Test name
Test status
Simulation time 58326280 ps
CPU time 0.95 seconds
Started Mar 07 02:46:51 PM PST 24
Finished Mar 07 02:46:52 PM PST 24
Peak memory 204888 kb
Host smart-7246fff4-6771-4b38-8fe3-e8b826b0a021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361719955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.361719955
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3608924003
Short name T726
Test name
Test status
Simulation time 5757398108 ps
CPU time 25.13 seconds
Started Mar 07 02:46:51 PM PST 24
Finished Mar 07 02:47:17 PM PST 24
Peak memory 249572 kb
Host smart-bb8734da-e4a0-4eeb-be51-3bb28f70f00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608924003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3608924003
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_upload.67340578
Short name T392
Test name
Test status
Simulation time 685680243 ps
CPU time 5.57 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:44:23 PM PST 24
Peak memory 228476 kb
Host smart-f7d6d58a-13f0-45e0-b6be-70b7ebbbb8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67340578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.67340578
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.216195285
Short name T1548
Test name
Test status
Simulation time 16792505 ps
CPU time 0.72 seconds
Started Mar 07 02:46:54 PM PST 24
Finished Mar 07 02:46:55 PM PST 24
Peak memory 204304 kb
Host smart-c5f53683-b9ed-442f-bdd0-c4fe02ad1b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216195285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.216195285
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3911817592
Short name T1409
Test name
Test status
Simulation time 191534957 ps
CPU time 0.72 seconds
Started Mar 07 12:44:16 PM PST 24
Finished Mar 07 12:44:17 PM PST 24
Peak memory 205140 kb
Host smart-12c3cf64-f09a-4e09-a6b7-0cb72f6f45a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911817592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3911817592
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3063812233
Short name T1770
Test name
Test status
Simulation time 337086355 ps
CPU time 3.44 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:44:21 PM PST 24
Peak memory 235900 kb
Host smart-942a596a-89c2-4802-b05c-12ec02a84df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063812233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3063812233
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3665280059
Short name T594
Test name
Test status
Simulation time 375470739 ps
CPU time 3.14 seconds
Started Mar 07 02:46:53 PM PST 24
Finished Mar 07 02:46:57 PM PST 24
Peak memory 233028 kb
Host smart-cf321d52-1609-48f1-a52d-51baf17b9dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665280059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3665280059
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.311629746
Short name T1230
Test name
Test status
Simulation time 22611550 ps
CPU time 0.8 seconds
Started Mar 07 12:44:16 PM PST 24
Finished Mar 07 12:44:17 PM PST 24
Peak memory 206208 kb
Host smart-af7dfaef-a1a5-46b2-84ab-9e2763ebd5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311629746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.311629746
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.94592932
Short name T84
Test name
Test status
Simulation time 16977489 ps
CPU time 0.83 seconds
Started Mar 07 02:47:00 PM PST 24
Finished Mar 07 02:47:01 PM PST 24
Peak memory 204204 kb
Host smart-4e3dadad-ed23-46f5-81fa-94fe7baefc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94592932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.94592932
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1767543033
Short name T204
Test name
Test status
Simulation time 5499848884 ps
CPU time 75.12 seconds
Started Mar 07 02:46:56 PM PST 24
Finished Mar 07 02:48:12 PM PST 24
Peak memory 266116 kb
Host smart-620f4b36-c13f-422a-bfcf-b70ea8bec5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767543033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1767543033
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4190908498
Short name T1481
Test name
Test status
Simulation time 45456351956 ps
CPU time 169.12 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:47:07 PM PST 24
Peak memory 263864 kb
Host smart-6e3f91c7-47df-4171-a5ab-8ce38575a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190908498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4190908498
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.11680566
Short name T597
Test name
Test status
Simulation time 8162999455 ps
CPU time 101.64 seconds
Started Mar 07 02:46:54 PM PST 24
Finished Mar 07 02:48:36 PM PST 24
Peak memory 249680 kb
Host smart-f0294511-4d86-4efe-be70-40f2eb649769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11680566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.11680566
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.706428652
Short name T302
Test name
Test status
Simulation time 21350907737 ps
CPU time 174.33 seconds
Started Mar 07 12:44:14 PM PST 24
Finished Mar 07 12:47:09 PM PST 24
Peak memory 256704 kb
Host smart-183ae647-d6c3-4ff7-8f97-dc3b698376fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706428652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.706428652
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1035600981
Short name T212
Test name
Test status
Simulation time 1326207322 ps
CPU time 15.23 seconds
Started Mar 07 02:46:55 PM PST 24
Finished Mar 07 02:47:11 PM PST 24
Peak memory 240352 kb
Host smart-914ec7d6-cb80-4767-afc4-a0b172c016c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035600981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1035600981
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.549575073
Short name T847
Test name
Test status
Simulation time 37613707874 ps
CPU time 85.49 seconds
Started Mar 07 12:44:21 PM PST 24
Finished Mar 07 12:45:46 PM PST 24
Peak memory 250004 kb
Host smart-27bc3968-264b-4646-9364-2946fbaada8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549575073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.549575073
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1280164371
Short name T1810
Test name
Test status
Simulation time 4561869584 ps
CPU time 23.63 seconds
Started Mar 07 02:46:55 PM PST 24
Finished Mar 07 02:47:19 PM PST 24
Peak memory 233032 kb
Host smart-ded118ef-5abd-4173-8a04-e218606a50ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280164371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1280164371
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1746113080
Short name T1600
Test name
Test status
Simulation time 116533719385 ps
CPU time 28.81 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:44:47 PM PST 24
Peak memory 224460 kb
Host smart-7806ff8e-6bdf-489e-bdee-3523ba3707b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746113080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1746113080
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1949499121
Short name T1050
Test name
Test status
Simulation time 420971524 ps
CPU time 2.78 seconds
Started Mar 07 12:44:14 PM PST 24
Finished Mar 07 12:44:17 PM PST 24
Peak memory 224376 kb
Host smart-0a878f17-0aa8-42f6-8966-a011a71a4552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949499121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1949499121
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2920296600
Short name T430
Test name
Test status
Simulation time 3838277548 ps
CPU time 8.91 seconds
Started Mar 07 02:46:54 PM PST 24
Finished Mar 07 02:47:03 PM PST 24
Peak memory 217732 kb
Host smart-e02aa816-f88f-4da8-a17f-9de1175ae3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920296600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2920296600
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1007238149
Short name T101
Test name
Test status
Simulation time 13498283887 ps
CPU time 16.7 seconds
Started Mar 07 02:46:54 PM PST 24
Finished Mar 07 02:47:12 PM PST 24
Peak memory 234056 kb
Host smart-aaae0113-176b-43f8-81af-a6f9ee59a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007238149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1007238149
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1452482111
Short name T1460
Test name
Test status
Simulation time 249819922 ps
CPU time 5.16 seconds
Started Mar 07 12:44:19 PM PST 24
Finished Mar 07 12:44:25 PM PST 24
Peak memory 235716 kb
Host smart-d578ecd3-e4d3-4bc1-83db-e6ebc76c1155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452482111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1452482111
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1313944670
Short name T954
Test name
Test status
Simulation time 4979981591 ps
CPU time 9.82 seconds
Started Mar 07 12:44:17 PM PST 24
Finished Mar 07 12:44:27 PM PST 24
Peak memory 232820 kb
Host smart-91e52857-da66-4f2d-838b-e40590b436d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313944670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1313944670
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4197310489
Short name T1390
Test name
Test status
Simulation time 18108973766 ps
CPU time 18.17 seconds
Started Mar 07 02:46:54 PM PST 24
Finished Mar 07 02:47:13 PM PST 24
Peak memory 232132 kb
Host smart-1adb9d0a-7320-4b6c-9feb-49157434aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197310489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4197310489
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4104884896
Short name T852
Test name
Test status
Simulation time 2170341836 ps
CPU time 8.95 seconds
Started Mar 07 02:46:46 PM PST 24
Finished Mar 07 02:46:55 PM PST 24
Peak memory 223956 kb
Host smart-a1072f9c-8f56-4aa8-a9c9-8a1c3e754caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104884896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4104884896
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.506825459
Short name T851
Test name
Test status
Simulation time 19992815409 ps
CPU time 17.38 seconds
Started Mar 07 12:44:19 PM PST 24
Finished Mar 07 12:44:37 PM PST 24
Peak memory 237908 kb
Host smart-caf4a034-ec3a-43ab-80fe-7036858d77fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506825459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.506825459
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1352386199
Short name T1143
Test name
Test status
Simulation time 1460908345 ps
CPU time 4.27 seconds
Started Mar 07 12:44:17 PM PST 24
Finished Mar 07 12:44:21 PM PST 24
Peak memory 220080 kb
Host smart-54e2f279-58c5-4607-ab0d-b834aa4b766c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1352386199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1352386199
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2058030689
Short name T1308
Test name
Test status
Simulation time 778354658 ps
CPU time 3.35 seconds
Started Mar 07 02:46:53 PM PST 24
Finished Mar 07 02:46:57 PM PST 24
Peak memory 219224 kb
Host smart-4fa358e2-3cdc-40d5-82df-985bbc560c28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2058030689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2058030689
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4150083771
Short name T305
Test name
Test status
Simulation time 209821391908 ps
CPU time 483.85 seconds
Started Mar 07 02:46:53 PM PST 24
Finished Mar 07 02:54:58 PM PST 24
Peak memory 264912 kb
Host smart-5b0d6f1a-dc28-4ed2-bc6a-45c5c64c8880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150083771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4150083771
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.605509997
Short name T1522
Test name
Test status
Simulation time 45858193 ps
CPU time 1.05 seconds
Started Mar 07 12:44:15 PM PST 24
Finished Mar 07 12:44:16 PM PST 24
Peak memory 206592 kb
Host smart-39351e18-c57f-4664-b66a-af8ba0f8b79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605509997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.605509997
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2185888739
Short name T1610
Test name
Test status
Simulation time 370131846 ps
CPU time 5.17 seconds
Started Mar 07 02:46:47 PM PST 24
Finished Mar 07 02:46:52 PM PST 24
Peak memory 215688 kb
Host smart-e986ae62-6238-443b-b3ab-c91a1b10d21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185888739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2185888739
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.836315191
Short name T1879
Test name
Test status
Simulation time 10918881207 ps
CPU time 34.58 seconds
Started Mar 07 12:44:17 PM PST 24
Finished Mar 07 12:44:52 PM PST 24
Peak memory 216216 kb
Host smart-9c3a07e4-d8e7-4d60-937f-5bc1a3fd1b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836315191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.836315191
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.294134502
Short name T1716
Test name
Test status
Simulation time 355982928 ps
CPU time 1.73 seconds
Started Mar 07 02:47:00 PM PST 24
Finished Mar 07 02:47:02 PM PST 24
Peak memory 206040 kb
Host smart-55c3f563-108d-449a-9ee3-cc53a09a24a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294134502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.294134502
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3976213611
Short name T553
Test name
Test status
Simulation time 11095731982 ps
CPU time 3.85 seconds
Started Mar 07 12:44:14 PM PST 24
Finished Mar 07 12:44:18 PM PST 24
Peak memory 216116 kb
Host smart-a40147fc-dd59-403c-9548-25c4b4fcc942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976213611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3976213611
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1723514608
Short name T1667
Test name
Test status
Simulation time 146616745 ps
CPU time 2.25 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:44:20 PM PST 24
Peak memory 216188 kb
Host smart-056858e0-fa52-4608-aa1a-1436f9a0852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723514608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1723514608
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.4106423467
Short name T1172
Test name
Test status
Simulation time 1744102164 ps
CPU time 4.78 seconds
Started Mar 07 02:47:00 PM PST 24
Finished Mar 07 02:47:05 PM PST 24
Peak memory 215628 kb
Host smart-cd56f233-12c9-4cd5-9460-479fcdf9076d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106423467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.4106423467
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1837601553
Short name T334
Test name
Test status
Simulation time 422114220 ps
CPU time 1 seconds
Started Mar 07 02:46:45 PM PST 24
Finished Mar 07 02:46:46 PM PST 24
Peak memory 205976 kb
Host smart-aba5a447-655d-460a-b6bb-c9f89e4bcb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837601553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1837601553
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3151179617
Short name T456
Test name
Test status
Simulation time 86566261 ps
CPU time 0.91 seconds
Started Mar 07 12:44:15 PM PST 24
Finished Mar 07 12:44:16 PM PST 24
Peak memory 206492 kb
Host smart-41769079-c661-4608-996f-26ef9a03fc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151179617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3151179617
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3889683065
Short name T785
Test name
Test status
Simulation time 1971779750 ps
CPU time 10.84 seconds
Started Mar 07 02:46:54 PM PST 24
Finished Mar 07 02:47:05 PM PST 24
Peak memory 233676 kb
Host smart-dc6f3b75-4aed-43dd-bc3a-0469db2289a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889683065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3889683065
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_upload.4213084067
Short name T41
Test name
Test status
Simulation time 2025657022 ps
CPU time 14.76 seconds
Started Mar 07 12:44:17 PM PST 24
Finished Mar 07 12:44:31 PM PST 24
Peak memory 249076 kb
Host smart-8c92cf9f-eec4-4b78-9ae8-5209fc8cd47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213084067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4213084067
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2655897773
Short name T902
Test name
Test status
Simulation time 34969175 ps
CPU time 0.73 seconds
Started Mar 07 02:47:06 PM PST 24
Finished Mar 07 02:47:07 PM PST 24
Peak memory 204396 kb
Host smart-8d2434ca-fb05-49af-afd4-6b64825426c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655897773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2655897773
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3389592425
Short name T818
Test name
Test status
Simulation time 13127455 ps
CPU time 0.71 seconds
Started Mar 07 12:44:19 PM PST 24
Finished Mar 07 12:44:20 PM PST 24
Peak memory 205160 kb
Host smart-69f1dc48-4e8e-4960-950c-f37e66331378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389592425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3389592425
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2294337015
Short name T997
Test name
Test status
Simulation time 1371675617 ps
CPU time 5.21 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:44:24 PM PST 24
Peak memory 233584 kb
Host smart-30e38b23-b473-478a-bfcc-2a5495f0bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294337015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2294337015
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4235772307
Short name T1417
Test name
Test status
Simulation time 762088149 ps
CPU time 5.63 seconds
Started Mar 07 02:46:55 PM PST 24
Finished Mar 07 02:47:01 PM PST 24
Peak memory 218452 kb
Host smart-2d3e0eb9-7ad3-4b89-a515-3a87e47fc28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235772307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4235772307
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2737104690
Short name T1512
Test name
Test status
Simulation time 13322769 ps
CPU time 0.76 seconds
Started Mar 07 02:46:54 PM PST 24
Finished Mar 07 02:46:55 PM PST 24
Peak memory 204492 kb
Host smart-f82424cb-e34a-4c22-879d-ac5d76a7cbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737104690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2737104690
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4079150978
Short name T1753
Test name
Test status
Simulation time 46248418 ps
CPU time 0.74 seconds
Started Mar 07 12:44:17 PM PST 24
Finished Mar 07 12:44:18 PM PST 24
Peak memory 206268 kb
Host smart-49e8db5f-f554-47c7-b068-d83321a896a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079150978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4079150978
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1651056556
Short name T1181
Test name
Test status
Simulation time 19792154179 ps
CPU time 115.62 seconds
Started Mar 07 02:46:55 PM PST 24
Finished Mar 07 02:48:51 PM PST 24
Peak memory 248416 kb
Host smart-5f6d6c15-d831-490e-ae30-19742a0efad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651056556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1651056556
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.272131815
Short name T166
Test name
Test status
Simulation time 45302065636 ps
CPU time 200.68 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:47:39 PM PST 24
Peak memory 240088 kb
Host smart-970f3c9e-3544-405e-8926-735e1c58b64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272131815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.272131815
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2837158878
Short name T43
Test name
Test status
Simulation time 27186557895 ps
CPU time 229.55 seconds
Started Mar 07 12:44:13 PM PST 24
Finished Mar 07 12:48:03 PM PST 24
Peak memory 253200 kb
Host smart-82863dbf-2150-4221-9d20-e6183af6538f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837158878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2837158878
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.32689239
Short name T1432
Test name
Test status
Simulation time 14402636577 ps
CPU time 189.27 seconds
Started Mar 07 02:46:58 PM PST 24
Finished Mar 07 02:50:08 PM PST 24
Peak memory 272648 kb
Host smart-31d292cb-3efa-4065-aa3d-0832eb2acde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32689239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.32689239
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2664473404
Short name T1329
Test name
Test status
Simulation time 33087427858 ps
CPU time 95.36 seconds
Started Mar 07 02:47:06 PM PST 24
Finished Mar 07 02:48:42 PM PST 24
Peak memory 236952 kb
Host smart-004ac964-b6dd-4116-b41b-1d0421b3d9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664473404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2664473404
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2796452818
Short name T1385
Test name
Test status
Simulation time 179170986743 ps
CPU time 276.21 seconds
Started Mar 07 12:44:14 PM PST 24
Finished Mar 07 12:48:50 PM PST 24
Peak memory 257360 kb
Host smart-bf93c333-39f4-41d5-9f20-04cdb913cfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796452818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2796452818
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2224822441
Short name T634
Test name
Test status
Simulation time 1798597413 ps
CPU time 21.56 seconds
Started Mar 07 12:44:14 PM PST 24
Finished Mar 07 12:44:35 PM PST 24
Peak memory 237848 kb
Host smart-fd903542-bff8-4eb8-9cc4-76110abe6106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224822441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2224822441
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.794736159
Short name T448
Test name
Test status
Simulation time 2382927395 ps
CPU time 15.39 seconds
Started Mar 07 02:46:57 PM PST 24
Finished Mar 07 02:47:12 PM PST 24
Peak memory 240292 kb
Host smart-c8a000a0-d1b3-4f51-ab42-7ee1eaff6be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794736159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.794736159
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2865222648
Short name T194
Test name
Test status
Simulation time 1170877535 ps
CPU time 4.4 seconds
Started Mar 07 02:46:56 PM PST 24
Finished Mar 07 02:47:01 PM PST 24
Peak memory 236956 kb
Host smart-dbb8ec8e-1569-4e63-8cf7-5207725b62f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865222648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2865222648
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3875875780
Short name T1355
Test name
Test status
Simulation time 2552566902 ps
CPU time 4.22 seconds
Started Mar 07 12:44:20 PM PST 24
Finished Mar 07 12:44:25 PM PST 24
Peak memory 224604 kb
Host smart-288ce85a-5d35-4c73-b0f7-658355b1775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875875780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3875875780
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.325724634
Short name T565
Test name
Test status
Simulation time 11142993786 ps
CPU time 12.15 seconds
Started Mar 07 12:44:16 PM PST 24
Finished Mar 07 12:44:29 PM PST 24
Peak memory 218488 kb
Host smart-f7412439-5518-4d82-92f5-7f359a26ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325724634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.325724634
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4149672937
Short name T781
Test name
Test status
Simulation time 3935093737 ps
CPU time 13.18 seconds
Started Mar 07 02:46:56 PM PST 24
Finished Mar 07 02:47:09 PM PST 24
Peak memory 250248 kb
Host smart-2398c5c6-9215-498e-9af1-4cbd6d288f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149672937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4149672937
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2311922649
Short name T786
Test name
Test status
Simulation time 234419939 ps
CPU time 2.58 seconds
Started Mar 07 02:46:57 PM PST 24
Finished Mar 07 02:47:00 PM PST 24
Peak memory 217956 kb
Host smart-59ab18ad-661d-4a10-a27f-fb80a2be6265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311922649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2311922649
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3655117475
Short name T1037
Test name
Test status
Simulation time 4432011145 ps
CPU time 12.99 seconds
Started Mar 07 12:44:15 PM PST 24
Finished Mar 07 12:44:28 PM PST 24
Peak memory 233520 kb
Host smart-4ea51aca-c72b-41be-afab-e3a8449fc7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655117475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3655117475
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.13294271
Short name T1312
Test name
Test status
Simulation time 2748707202 ps
CPU time 12.08 seconds
Started Mar 07 02:46:55 PM PST 24
Finished Mar 07 02:47:07 PM PST 24
Peak memory 234036 kb
Host smart-3e8b5345-cc84-4f45-919e-8e53d46dc9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13294271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.13294271
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2501399357
Short name T1176
Test name
Test status
Simulation time 6408921986 ps
CPU time 11.1 seconds
Started Mar 07 12:44:16 PM PST 24
Finished Mar 07 12:44:28 PM PST 24
Peak memory 243216 kb
Host smart-5d593d95-11e6-49d1-a4a7-661e3e336da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501399357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2501399357
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3274256646
Short name T1186
Test name
Test status
Simulation time 627313554 ps
CPU time 3.74 seconds
Started Mar 07 02:46:55 PM PST 24
Finished Mar 07 02:46:59 PM PST 24
Peak memory 218788 kb
Host smart-5529c7a3-5baf-4a01-96a2-74c079478646
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3274256646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3274256646
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.771200518
Short name T1906
Test name
Test status
Simulation time 5569235879 ps
CPU time 6.55 seconds
Started Mar 07 12:44:19 PM PST 24
Finished Mar 07 12:44:26 PM PST 24
Peak memory 218540 kb
Host smart-0b7b09be-275d-4d49-aeef-c363828aabb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=771200518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.771200518
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.292055615
Short name T1616
Test name
Test status
Simulation time 129957277322 ps
CPU time 253.73 seconds
Started Mar 07 02:47:06 PM PST 24
Finished Mar 07 02:51:20 PM PST 24
Peak memory 273256 kb
Host smart-b0de9344-bfec-4033-b1ec-d016f9e191c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292055615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.292055615
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3791440623
Short name T1259
Test name
Test status
Simulation time 221253247928 ps
CPU time 327.7 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:49:45 PM PST 24
Peak memory 249140 kb
Host smart-8837245e-1a14-4467-a844-8481c3af113c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791440623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3791440623
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1501117571
Short name T495
Test name
Test status
Simulation time 422484876 ps
CPU time 3.4 seconds
Started Mar 07 02:46:56 PM PST 24
Finished Mar 07 02:47:00 PM PST 24
Peak memory 215704 kb
Host smart-1fc31b5e-fbc6-43a5-92c0-0067dde8f537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501117571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1501117571
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2725578252
Short name T793
Test name
Test status
Simulation time 1243732168 ps
CPU time 13.45 seconds
Started Mar 07 12:44:22 PM PST 24
Finished Mar 07 12:44:36 PM PST 24
Peak memory 216416 kb
Host smart-3ead5f41-7af4-4373-839d-2f7d2c0bc50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725578252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2725578252
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2449383224
Short name T371
Test name
Test status
Simulation time 1009731945 ps
CPU time 6.02 seconds
Started Mar 07 12:44:19 PM PST 24
Finished Mar 07 12:44:25 PM PST 24
Peak memory 216192 kb
Host smart-45a7f441-8896-4d8a-a6ef-6acafa0cb8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449383224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2449383224
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3721741236
Short name T704
Test name
Test status
Simulation time 7645624134 ps
CPU time 12.19 seconds
Started Mar 07 02:46:57 PM PST 24
Finished Mar 07 02:47:09 PM PST 24
Peak memory 215900 kb
Host smart-c655919c-dce8-4cae-9624-398ebd7e5e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721741236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3721741236
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.456823705
Short name T1747
Test name
Test status
Simulation time 25201915 ps
CPU time 1.68 seconds
Started Mar 07 02:46:54 PM PST 24
Finished Mar 07 02:46:56 PM PST 24
Peak memory 215800 kb
Host smart-47988cd2-c35e-44a5-bab7-d093da31a93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456823705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.456823705
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.914948251
Short name T390
Test name
Test status
Simulation time 1442375365 ps
CPU time 1.65 seconds
Started Mar 07 12:44:19 PM PST 24
Finished Mar 07 12:44:21 PM PST 24
Peak memory 208388 kb
Host smart-c6a4587b-6036-4f5a-8e8c-16167aae5e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914948251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.914948251
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3686837580
Short name T1556
Test name
Test status
Simulation time 57344021 ps
CPU time 0.87 seconds
Started Mar 07 02:46:55 PM PST 24
Finished Mar 07 02:46:57 PM PST 24
Peak memory 204832 kb
Host smart-de25fdd1-40d7-48df-9820-cbfd7791fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686837580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3686837580
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.660383237
Short name T569
Test name
Test status
Simulation time 176000756 ps
CPU time 1.26 seconds
Started Mar 07 12:44:18 PM PST 24
Finished Mar 07 12:44:19 PM PST 24
Peak memory 206568 kb
Host smart-bc45a9a1-ea26-449e-9fff-0898da8ad21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660383237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.660383237
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2096659531
Short name T943
Test name
Test status
Simulation time 1814778734 ps
CPU time 8.77 seconds
Started Mar 07 12:44:16 PM PST 24
Finished Mar 07 12:44:25 PM PST 24
Peak memory 217264 kb
Host smart-3274fb6c-9f8f-40d2-9f41-708624ff5df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096659531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2096659531
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_upload.3384666305
Short name T1128
Test name
Test status
Simulation time 513295177 ps
CPU time 6.77 seconds
Started Mar 07 02:46:55 PM PST 24
Finished Mar 07 02:47:02 PM PST 24
Peak memory 218744 kb
Host smart-17312a25-142f-410b-ad42-87e0687fd074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384666305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3384666305
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.497041523
Short name T895
Test name
Test status
Simulation time 23794000 ps
CPU time 0.68 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:43:14 PM PST 24
Peak memory 203816 kb
Host smart-7e1f8c0d-e30e-4b95-820a-7e7d8a3e3e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497041523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.497041523
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.499045862
Short name T1144
Test name
Test status
Simulation time 12469683 ps
CPU time 0.73 seconds
Started Mar 07 12:41:14 PM PST 24
Finished Mar 07 12:41:15 PM PST 24
Peak memory 205164 kb
Host smart-6ed19f9d-17b6-4ddd-b5e6-5b7b82cd22c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499045862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.499045862
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1961193064
Short name T559
Test name
Test status
Simulation time 1596842675 ps
CPU time 4.38 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:29 PM PST 24
Peak memory 219328 kb
Host smart-33c77b59-1b8c-4c8e-b9b5-27daab437fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961193064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1961193064
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2355234225
Short name T1058
Test name
Test status
Simulation time 4389131843 ps
CPU time 6.24 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:43:21 PM PST 24
Peak memory 233300 kb
Host smart-93a3f465-061f-43fb-9d5d-78e339f8a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355234225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2355234225
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3395730502
Short name T1651
Test name
Test status
Simulation time 42703955 ps
CPU time 0.79 seconds
Started Mar 07 02:43:09 PM PST 24
Finished Mar 07 02:43:10 PM PST 24
Peak memory 205536 kb
Host smart-b26fa302-1fef-45d5-a3ed-5d56b14d7b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395730502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3395730502
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.755371980
Short name T1419
Test name
Test status
Simulation time 16941000 ps
CPU time 0.79 seconds
Started Mar 07 12:41:08 PM PST 24
Finished Mar 07 12:41:09 PM PST 24
Peak memory 206228 kb
Host smart-5324e645-40c5-4416-9853-73926ebd8320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755371980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.755371980
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1371624856
Short name T100
Test name
Test status
Simulation time 34624619181 ps
CPU time 159.62 seconds
Started Mar 07 12:41:16 PM PST 24
Finished Mar 07 12:43:56 PM PST 24
Peak memory 256852 kb
Host smart-a2d56e8b-bb2d-42bc-bbd2-5e520e6dff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371624856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1371624856
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1494874003
Short name T274
Test name
Test status
Simulation time 29488195620 ps
CPU time 69.55 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:44:25 PM PST 24
Peak memory 255360 kb
Host smart-d93d1e72-2b03-4ccc-a037-c1169ad2a9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494874003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1494874003
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4266217457
Short name T814
Test name
Test status
Simulation time 226981490802 ps
CPU time 404.9 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:49:58 PM PST 24
Peak memory 261800 kb
Host smart-4bac0381-ad72-44df-b518-057308ef430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266217457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4266217457
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.821298029
Short name T1899
Test name
Test status
Simulation time 231368459495 ps
CPU time 462.9 seconds
Started Mar 07 12:41:16 PM PST 24
Finished Mar 07 12:48:59 PM PST 24
Peak memory 269836 kb
Host smart-d8d6f821-8c63-4ade-82fe-dffa37003342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821298029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.821298029
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1617789441
Short name T1482
Test name
Test status
Simulation time 81860143900 ps
CPU time 166.19 seconds
Started Mar 07 12:41:20 PM PST 24
Finished Mar 07 12:44:06 PM PST 24
Peak memory 251832 kb
Host smart-60fcaa38-2bfe-4347-87b5-a93f272a4c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617789441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1617789441
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4261939837
Short name T1816
Test name
Test status
Simulation time 302691515780 ps
CPU time 381.34 seconds
Started Mar 07 02:43:18 PM PST 24
Finished Mar 07 02:49:40 PM PST 24
Peak memory 262464 kb
Host smart-5449449a-0be3-446e-8558-8d03ea959e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261939837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4261939837
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3265009322
Short name T1736
Test name
Test status
Simulation time 2930834663 ps
CPU time 11.29 seconds
Started Mar 07 12:41:18 PM PST 24
Finished Mar 07 12:41:29 PM PST 24
Peak memory 233740 kb
Host smart-6f822890-f32a-4c48-8719-35bbbf80513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265009322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3265009322
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2751934228
Short name T1006
Test name
Test status
Simulation time 2460856732 ps
CPU time 5.58 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:43:19 PM PST 24
Peak memory 233320 kb
Host smart-813cd10d-4bbb-43c5-940d-b3db5353b93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751934228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2751934228
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4155961659
Short name T241
Test name
Test status
Simulation time 225135665 ps
CPU time 3.74 seconds
Started Mar 07 12:41:12 PM PST 24
Finished Mar 07 12:41:16 PM PST 24
Peak memory 224324 kb
Host smart-24766636-c8d5-400a-ba4c-cfbbf73279ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155961659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4155961659
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3194531049
Short name T1644
Test name
Test status
Simulation time 8380520706 ps
CPU time 12.91 seconds
Started Mar 07 12:41:09 PM PST 24
Finished Mar 07 12:41:23 PM PST 24
Peak memory 231332 kb
Host smart-265be0ce-0e41-40f1-8fee-50c147588ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194531049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3194531049
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4098431432
Short name T254
Test name
Test status
Simulation time 284059488 ps
CPU time 6.7 seconds
Started Mar 07 02:43:16 PM PST 24
Finished Mar 07 02:43:23 PM PST 24
Peak memory 223840 kb
Host smart-a7e8bf48-2a6f-4a6b-b645-a44583c0cbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098431432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4098431432
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1732426387
Short name T1335
Test name
Test status
Simulation time 16505391 ps
CPU time 1.01 seconds
Started Mar 07 02:43:09 PM PST 24
Finished Mar 07 02:43:11 PM PST 24
Peak memory 217288 kb
Host smart-98398645-45f7-403d-b864-55ad6b1a4c67
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732426387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1732426387
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3273060372
Short name T1606
Test name
Test status
Simulation time 1528471205 ps
CPU time 5.48 seconds
Started Mar 07 12:41:09 PM PST 24
Finished Mar 07 12:41:15 PM PST 24
Peak memory 218404 kb
Host smart-9c5cbad8-e956-48d4-8124-f62c3cbbf9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273060372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3273060372
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3367331155
Short name T252
Test name
Test status
Simulation time 491555531 ps
CPU time 4.22 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:43:19 PM PST 24
Peak memory 216100 kb
Host smart-5feebd0a-57f9-4620-9016-9ff20e99c779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367331155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3367331155
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2765631148
Short name T940
Test name
Test status
Simulation time 1350045700 ps
CPU time 5.39 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:43:20 PM PST 24
Peak memory 216672 kb
Host smart-c5227488-5372-48fc-979f-fd5a26fa54f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765631148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2765631148
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3324596768
Short name T1550
Test name
Test status
Simulation time 498578474 ps
CPU time 4.93 seconds
Started Mar 07 12:41:08 PM PST 24
Finished Mar 07 12:41:13 PM PST 24
Peak memory 222052 kb
Host smart-a4cf75f2-478c-4a15-897e-6376f2377bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324596768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3324596768
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.2912362407
Short name T1557
Test name
Test status
Simulation time 25000002 ps
CPU time 0.76 seconds
Started Mar 07 12:41:11 PM PST 24
Finished Mar 07 12:41:12 PM PST 24
Peak memory 216196 kb
Host smart-5e015660-b892-47e1-87ba-54c3458cc3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912362407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.2912362407
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3750724531
Short name T65
Test name
Test status
Simulation time 18729350 ps
CPU time 0.76 seconds
Started Mar 07 02:43:17 PM PST 24
Finished Mar 07 02:43:18 PM PST 24
Peak memory 215508 kb
Host smart-f63816e5-fea0-4f99-aa4a-18fd72997b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750724531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3750724531
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3744119253
Short name T1471
Test name
Test status
Simulation time 427323340 ps
CPU time 3.89 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:29 PM PST 24
Peak memory 222700 kb
Host smart-2398ed1c-9883-48bc-a4ad-91a80e8ca438
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3744119253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3744119253
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.464603431
Short name T1843
Test name
Test status
Simulation time 654187207 ps
CPU time 4.49 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:43:19 PM PST 24
Peak memory 215928 kb
Host smart-bdfab732-b6b5-40af-b2a2-aaf36e65c46d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=464603431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.464603431
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2459737936
Short name T1080
Test name
Test status
Simulation time 198510923 ps
CPU time 0.99 seconds
Started Mar 07 12:41:15 PM PST 24
Finished Mar 07 12:41:16 PM PST 24
Peak memory 206676 kb
Host smart-e4b7cb10-fe0e-456c-81d3-7bd034c68c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459737936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2459737936
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1128329297
Short name T705
Test name
Test status
Simulation time 12102035990 ps
CPU time 74.31 seconds
Started Mar 07 02:43:09 PM PST 24
Finished Mar 07 02:44:24 PM PST 24
Peak memory 219860 kb
Host smart-317c90f4-92ac-4c57-90d0-7dc3f3889258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128329297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1128329297
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2980652614
Short name T378
Test name
Test status
Simulation time 2921557620 ps
CPU time 8.98 seconds
Started Mar 07 12:41:11 PM PST 24
Finished Mar 07 12:41:21 PM PST 24
Peak memory 216236 kb
Host smart-363f8cd7-2960-41d8-bb28-6450e61738ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980652614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2980652614
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1147741072
Short name T1051
Test name
Test status
Simulation time 13810552321 ps
CPU time 7.76 seconds
Started Mar 07 12:41:10 PM PST 24
Finished Mar 07 12:41:19 PM PST 24
Peak memory 216188 kb
Host smart-0b45ab65-d14c-472d-b293-681fa2f7ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147741072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1147741072
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1866999427
Short name T551
Test name
Test status
Simulation time 2378083290 ps
CPU time 4.99 seconds
Started Mar 07 02:43:16 PM PST 24
Finished Mar 07 02:43:21 PM PST 24
Peak memory 215776 kb
Host smart-ca416a5f-b61b-4822-a861-dac7dfa6440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866999427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1866999427
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.658592118
Short name T404
Test name
Test status
Simulation time 142446641 ps
CPU time 1.17 seconds
Started Mar 07 12:41:09 PM PST 24
Finished Mar 07 12:41:10 PM PST 24
Peak memory 216284 kb
Host smart-8e784c01-9359-4ce6-a0f6-74aeaabf3021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658592118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.658592118
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.956428999
Short name T1201
Test name
Test status
Simulation time 234443211 ps
CPU time 1.49 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:43:15 PM PST 24
Peak memory 215808 kb
Host smart-3cd08b4e-ca11-4e19-af3e-86af2e3770a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956428999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.956428999
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3668186556
Short name T1357
Test name
Test status
Simulation time 17751927 ps
CPU time 0.76 seconds
Started Mar 07 12:41:08 PM PST 24
Finished Mar 07 12:41:09 PM PST 24
Peak memory 205528 kb
Host smart-c4276993-1367-4858-889f-0a00fceb400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668186556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3668186556
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3834530133
Short name T931
Test name
Test status
Simulation time 197619121 ps
CPU time 0.82 seconds
Started Mar 07 02:43:11 PM PST 24
Finished Mar 07 02:43:12 PM PST 24
Peak memory 204896 kb
Host smart-31147c2c-de30-4043-ba9b-8719a1b7d629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834530133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3834530133
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1516065865
Short name T1286
Test name
Test status
Simulation time 5155831874 ps
CPU time 8.43 seconds
Started Mar 07 12:41:14 PM PST 24
Finished Mar 07 12:41:22 PM PST 24
Peak memory 218772 kb
Host smart-fc5dd0e7-ed2d-48c1-85b9-0635577a3b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516065865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1516065865
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_upload.2647593469
Short name T1044
Test name
Test status
Simulation time 17162207815 ps
CPU time 52.92 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:44:08 PM PST 24
Peak memory 246824 kb
Host smart-24b7023a-d3ae-49e0-b6d4-299199f79a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647593469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2647593469
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1921448378
Short name T1853
Test name
Test status
Simulation time 42764779 ps
CPU time 0.7 seconds
Started Mar 07 12:41:14 PM PST 24
Finished Mar 07 12:41:15 PM PST 24
Peak memory 205164 kb
Host smart-802f6fa1-7a20-49c1-bfe6-33487c3b0db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921448378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
921448378
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2256994627
Short name T1309
Test name
Test status
Simulation time 12915090 ps
CPU time 0.68 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:43:14 PM PST 24
Peak memory 204584 kb
Host smart-5d348966-5aa9-4c2b-9a9d-91b118fdab56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256994627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
256994627
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1395943373
Short name T1636
Test name
Test status
Simulation time 10575400428 ps
CPU time 10.54 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:35 PM PST 24
Peak memory 224484 kb
Host smart-cf1cc05f-96f9-4dc3-a4b2-e104c0f839ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395943373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1395943373
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.204976101
Short name T497
Test name
Test status
Simulation time 2193921630 ps
CPU time 4.97 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:43:20 PM PST 24
Peak memory 233728 kb
Host smart-71143361-84ab-46c6-948d-4ce084bc877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204976101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.204976101
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1484231213
Short name T1608
Test name
Test status
Simulation time 21542139 ps
CPU time 0.79 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:43:15 PM PST 24
Peak memory 205732 kb
Host smart-5665b9fa-f694-441b-a506-0855991e514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484231213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1484231213
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.996997014
Short name T746
Test name
Test status
Simulation time 47830157 ps
CPU time 0.71 seconds
Started Mar 07 12:41:14 PM PST 24
Finished Mar 07 12:41:15 PM PST 24
Peak memory 205620 kb
Host smart-ae9aba78-b4a8-4792-ba96-6a4ed6cb8247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996997014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.996997014
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2934041977
Short name T1412
Test name
Test status
Simulation time 121316152844 ps
CPU time 133.21 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:45:28 PM PST 24
Peak memory 234504 kb
Host smart-f895dcc3-a06f-4385-9a13-2655c4861826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934041977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2934041977
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3660635547
Short name T214
Test name
Test status
Simulation time 77378112630 ps
CPU time 196.91 seconds
Started Mar 07 12:41:17 PM PST 24
Finished Mar 07 12:44:35 PM PST 24
Peak memory 249028 kb
Host smart-a60b2ea9-1ea5-4d0c-905b-bebead98c824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660635547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3660635547
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3897289374
Short name T1192
Test name
Test status
Simulation time 7687671809 ps
CPU time 78.66 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:44:33 PM PST 24
Peak memory 253768 kb
Host smart-061e182f-b89b-426f-ba7c-7baf127934ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897289374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3897289374
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4230077568
Short name T489
Test name
Test status
Simulation time 57148569907 ps
CPU time 305.37 seconds
Started Mar 07 12:41:16 PM PST 24
Finished Mar 07 12:46:23 PM PST 24
Peak memory 259872 kb
Host smart-36353c9f-0808-4a36-be7c-09382dd35811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230077568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4230077568
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.980644513
Short name T1635
Test name
Test status
Simulation time 4547039266 ps
CPU time 69.91 seconds
Started Mar 07 12:41:16 PM PST 24
Finished Mar 07 12:42:26 PM PST 24
Peak memory 264856 kb
Host smart-5dbfc937-2bf7-45a5-b33a-de2c7e417133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980644513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
980644513
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3064679538
Short name T628
Test name
Test status
Simulation time 15080627591 ps
CPU time 34.84 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:43:48 PM PST 24
Peak memory 233276 kb
Host smart-9f85e2bd-7b28-4826-b323-001c00591cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064679538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3064679538
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.740902291
Short name T311
Test name
Test status
Simulation time 240282798 ps
CPU time 5.98 seconds
Started Mar 07 12:41:17 PM PST 24
Finished Mar 07 12:41:23 PM PST 24
Peak memory 233068 kb
Host smart-fbd636d5-fd0c-45c1-a8d9-11a50a419e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740902291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.740902291
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2601300327
Short name T816
Test name
Test status
Simulation time 21840247447 ps
CPU time 18.34 seconds
Started Mar 07 02:43:16 PM PST 24
Finished Mar 07 02:43:35 PM PST 24
Peak memory 233088 kb
Host smart-cfe38401-a72d-411c-9dad-5d8a681241e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601300327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2601300327
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3680665876
Short name T1029
Test name
Test status
Simulation time 615382501 ps
CPU time 4.89 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:30 PM PST 24
Peak memory 234100 kb
Host smart-49e0d066-3742-4c70-8f82-ec01b7d6a39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680665876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3680665876
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2064987547
Short name T1411
Test name
Test status
Simulation time 56462978633 ps
CPU time 43.19 seconds
Started Mar 07 02:43:20 PM PST 24
Finished Mar 07 02:44:04 PM PST 24
Peak memory 232112 kb
Host smart-d367c1e3-0ff1-48cd-9df1-0bb0ad307f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064987547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2064987547
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3913097521
Short name T617
Test name
Test status
Simulation time 4860460103 ps
CPU time 18.03 seconds
Started Mar 07 12:41:24 PM PST 24
Finished Mar 07 12:41:42 PM PST 24
Peak memory 239024 kb
Host smart-13c2ab14-9b70-4931-8970-e4a16c53c173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913097521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3913097521
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.612615324
Short name T23
Test name
Test status
Simulation time 24694056 ps
CPU time 1.13 seconds
Started Mar 07 02:43:17 PM PST 24
Finished Mar 07 02:43:19 PM PST 24
Peak memory 217064 kb
Host smart-e9a55086-a289-405d-a058-cab6399a59f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612615324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.612615324
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2480065605
Short name T913
Test name
Test status
Simulation time 1497350448 ps
CPU time 3.65 seconds
Started Mar 07 02:43:20 PM PST 24
Finished Mar 07 02:43:24 PM PST 24
Peak memory 223812 kb
Host smart-2c428721-fed6-4ab4-8a69-1748f87d791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480065605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2480065605
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.266240126
Short name T218
Test name
Test status
Simulation time 50208589035 ps
CPU time 36.38 seconds
Started Mar 07 12:41:21 PM PST 24
Finished Mar 07 12:41:58 PM PST 24
Peak memory 233592 kb
Host smart-2be3d6e3-77c7-47a4-bb5b-19020ec88e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266240126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
266240126
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2807653097
Short name T230
Test name
Test status
Simulation time 1123449715 ps
CPU time 4.1 seconds
Started Mar 07 12:41:17 PM PST 24
Finished Mar 07 12:41:22 PM PST 24
Peak memory 233680 kb
Host smart-403f5d85-a690-406a-9fcc-b87d9206433e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807653097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2807653097
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.885159267
Short name T1710
Test name
Test status
Simulation time 24588520511 ps
CPU time 21.41 seconds
Started Mar 07 02:43:15 PM PST 24
Finished Mar 07 02:43:36 PM PST 24
Peak memory 239888 kb
Host smart-f47847a2-fccd-4721-a7c4-80eb4ab01980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885159267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.885159267
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2907965579
Short name T1723
Test name
Test status
Simulation time 22333464 ps
CPU time 0.73 seconds
Started Mar 07 02:43:20 PM PST 24
Finished Mar 07 02:43:21 PM PST 24
Peak memory 215600 kb
Host smart-3fa8ba8c-6162-4240-93b7-95c4a45525f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907965579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2907965579
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3046501562
Short name T1003
Test name
Test status
Simulation time 126334275 ps
CPU time 0.72 seconds
Started Mar 07 12:41:17 PM PST 24
Finished Mar 07 12:41:18 PM PST 24
Peak memory 216144 kb
Host smart-aaf58d3e-3ee1-40ef-88ba-2b574cea4210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046501562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3046501562
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3120359390
Short name T1319
Test name
Test status
Simulation time 1756505547 ps
CPU time 5.5 seconds
Started Mar 07 12:41:16 PM PST 24
Finished Mar 07 12:41:22 PM PST 24
Peak memory 222536 kb
Host smart-044948e9-9285-4a7f-a3be-817a10e2892e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3120359390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3120359390
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4109777051
Short name T1425
Test name
Test status
Simulation time 635720820 ps
CPU time 4.83 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:43:18 PM PST 24
Peak memory 221500 kb
Host smart-7af28349-457a-49ca-9e32-ba120771d1a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4109777051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4109777051
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1169342244
Short name T297
Test name
Test status
Simulation time 486345389285 ps
CPU time 827.99 seconds
Started Mar 07 12:41:20 PM PST 24
Finished Mar 07 12:55:08 PM PST 24
Peak memory 297616 kb
Host smart-24da4c37-87e3-4bf1-a456-e088568198ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169342244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1169342244
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3964413873
Short name T941
Test name
Test status
Simulation time 32746650547 ps
CPU time 165.16 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:45:59 PM PST 24
Peak memory 256664 kb
Host smart-9b071baa-7719-4ad5-85e2-d8f32b2b4fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964413873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3964413873
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2438995296
Short name T374
Test name
Test status
Simulation time 7466342248 ps
CPU time 13.75 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:40 PM PST 24
Peak memory 216364 kb
Host smart-dfff007b-89ae-4ee3-9378-24e928ebded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438995296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2438995296
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3464015657
Short name T930
Test name
Test status
Simulation time 5975256001 ps
CPU time 16.33 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 215836 kb
Host smart-4c5fd3b0-4f9f-466f-bcca-f99971b3f0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464015657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3464015657
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1981666462
Short name T1570
Test name
Test status
Simulation time 5407041745 ps
CPU time 19.86 seconds
Started Mar 07 02:43:16 PM PST 24
Finished Mar 07 02:43:37 PM PST 24
Peak memory 215864 kb
Host smart-3c7361d9-762e-4b4c-bd4c-a7e5fdb360d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981666462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1981666462
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3008041041
Short name T389
Test name
Test status
Simulation time 4944159088 ps
CPU time 10.53 seconds
Started Mar 07 12:41:15 PM PST 24
Finished Mar 07 12:41:26 PM PST 24
Peak memory 216216 kb
Host smart-ff924128-f77e-4a26-8e88-8d480ee06783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008041041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3008041041
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1440684702
Short name T1365
Test name
Test status
Simulation time 43303317 ps
CPU time 1.2 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:43:14 PM PST 24
Peak memory 207208 kb
Host smart-30e8fd8f-8dbf-4035-9da9-86ff7cf2a60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440684702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1440684702
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.785331523
Short name T1289
Test name
Test status
Simulation time 20084010 ps
CPU time 0.68 seconds
Started Mar 07 12:41:14 PM PST 24
Finished Mar 07 12:41:16 PM PST 24
Peak memory 205496 kb
Host smart-12cfc351-1200-479a-8b55-b2259b89cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785331523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.785331523
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1872216849
Short name T1790
Test name
Test status
Simulation time 117205630 ps
CPU time 1.02 seconds
Started Mar 07 12:41:18 PM PST 24
Finished Mar 07 12:41:19 PM PST 24
Peak memory 206436 kb
Host smart-a210ed79-93f8-4bdf-a849-f5f7ce5611c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872216849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1872216849
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2621600213
Short name T995
Test name
Test status
Simulation time 68469686 ps
CPU time 0.93 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:43:15 PM PST 24
Peak memory 204848 kb
Host smart-f682c29d-21e0-4154-93c1-8ddff6f2102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621600213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2621600213
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.115159718
Short name T915
Test name
Test status
Simulation time 561299419 ps
CPU time 3.66 seconds
Started Mar 07 12:41:20 PM PST 24
Finished Mar 07 12:41:24 PM PST 24
Peak memory 217232 kb
Host smart-3f2b325d-aea2-4815-91cf-722a7193fb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115159718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.115159718
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_upload.2923436170
Short name T190
Test name
Test status
Simulation time 5462714243 ps
CPU time 9.44 seconds
Started Mar 07 02:43:19 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 227568 kb
Host smart-72376c1f-3a52-484d-9bc8-b43108526856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923436170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2923436170
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1396402588
Short name T1163
Test name
Test status
Simulation time 131170205 ps
CPU time 0.69 seconds
Started Mar 07 12:41:24 PM PST 24
Finished Mar 07 12:41:25 PM PST 24
Peak memory 205460 kb
Host smart-80a278fc-bd0c-44bf-a3a1-647040e19d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396402588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
396402588
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3922276118
Short name T360
Test name
Test status
Simulation time 15046877 ps
CPU time 0.75 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:43:24 PM PST 24
Peak memory 204452 kb
Host smart-8167abc3-c2f7-4769-b488-97ac68feea02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922276118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
922276118
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4095905453
Short name T429
Test name
Test status
Simulation time 525334939 ps
CPU time 3.19 seconds
Started Mar 07 02:43:22 PM PST 24
Finished Mar 07 02:43:26 PM PST 24
Peak memory 233764 kb
Host smart-191894ab-ad0b-43e4-832d-46c480d877c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095905453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4095905453
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.61377373
Short name T658
Test name
Test status
Simulation time 40808285 ps
CPU time 2.19 seconds
Started Mar 07 12:41:24 PM PST 24
Finished Mar 07 12:41:26 PM PST 24
Peak memory 216828 kb
Host smart-1163fd25-2b68-4198-9234-8ad9d73866e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61377373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.61377373
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1116417665
Short name T329
Test name
Test status
Simulation time 15588330 ps
CPU time 0.76 seconds
Started Mar 07 12:41:18 PM PST 24
Finished Mar 07 12:41:19 PM PST 24
Peak memory 206248 kb
Host smart-4d70b6e8-85bc-456c-8665-20cb792f723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116417665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1116417665
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2570956583
Short name T1095
Test name
Test status
Simulation time 14700296 ps
CPU time 0.76 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:43:15 PM PST 24
Peak memory 204516 kb
Host smart-40fba7f9-cc68-4fc5-9783-08d41e98be4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570956583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2570956583
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1870501526
Short name T1834
Test name
Test status
Simulation time 24035651154 ps
CPU time 77.3 seconds
Started Mar 07 12:41:26 PM PST 24
Finished Mar 07 12:42:43 PM PST 24
Peak memory 251796 kb
Host smart-2142a8c2-b1f1-491f-8ba6-76ee27abb30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870501526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1870501526
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4160055772
Short name T291
Test name
Test status
Simulation time 32424990992 ps
CPU time 167.96 seconds
Started Mar 07 02:43:22 PM PST 24
Finished Mar 07 02:46:10 PM PST 24
Peak memory 263452 kb
Host smart-8971bfa2-6363-43bb-964c-ba5b6591aa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160055772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4160055772
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1846586661
Short name T1585
Test name
Test status
Simulation time 8759031541 ps
CPU time 54.09 seconds
Started Mar 07 12:41:26 PM PST 24
Finished Mar 07 12:42:20 PM PST 24
Peak memory 257392 kb
Host smart-a7fdf4a6-a8e2-4712-8d2b-517132032ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846586661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1846586661
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.739396664
Short name T666
Test name
Test status
Simulation time 1927197634 ps
CPU time 14.28 seconds
Started Mar 07 02:43:22 PM PST 24
Finished Mar 07 02:43:37 PM PST 24
Peak memory 233244 kb
Host smart-ff4ac71e-915a-46c3-bf2a-d97a50ea0a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739396664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.739396664
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1654182557
Short name T1182
Test name
Test status
Simulation time 56305782698 ps
CPU time 72 seconds
Started Mar 07 12:41:26 PM PST 24
Finished Mar 07 12:42:38 PM PST 24
Peak memory 249276 kb
Host smart-8504daf2-6136-4ae2-9bb6-0a54d54eb75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654182557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1654182557
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4061957721
Short name T1669
Test name
Test status
Simulation time 13991411766 ps
CPU time 122.16 seconds
Started Mar 07 02:43:24 PM PST 24
Finished Mar 07 02:45:26 PM PST 24
Peak memory 249636 kb
Host smart-8615ec69-ac90-4d69-9a3e-b3529427c4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061957721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4061957721
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2678111895
Short name T312
Test name
Test status
Simulation time 9783536403 ps
CPU time 21.08 seconds
Started Mar 07 02:43:21 PM PST 24
Finished Mar 07 02:43:43 PM PST 24
Peak memory 245128 kb
Host smart-fd4688f4-6b1d-4fa3-a31a-3c16220929e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678111895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2678111895
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.881974283
Short name T1812
Test name
Test status
Simulation time 28373667988 ps
CPU time 37.63 seconds
Started Mar 07 12:41:26 PM PST 24
Finished Mar 07 12:42:04 PM PST 24
Peak memory 239364 kb
Host smart-ac2bfb1f-f1b1-4c99-b730-c7051adf91a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881974283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.881974283
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.163188062
Short name T1141
Test name
Test status
Simulation time 433620627 ps
CPU time 2.86 seconds
Started Mar 07 12:41:23 PM PST 24
Finished Mar 07 12:41:26 PM PST 24
Peak memory 224380 kb
Host smart-ed168699-6244-4b12-9e03-4652fa0373f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163188062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.163188062
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2004693865
Short name T1709
Test name
Test status
Simulation time 1197458753 ps
CPU time 2.98 seconds
Started Mar 07 02:43:13 PM PST 24
Finished Mar 07 02:43:16 PM PST 24
Peak memory 233112 kb
Host smart-62130c11-101c-4b3f-ad7c-249f4c388e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004693865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2004693865
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3800130695
Short name T1775
Test name
Test status
Simulation time 7557839427 ps
CPU time 11.89 seconds
Started Mar 07 12:41:22 PM PST 24
Finished Mar 07 12:41:34 PM PST 24
Peak memory 232812 kb
Host smart-d614a75b-3810-4f49-b86d-c416efcd5852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800130695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3800130695
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.445138939
Short name T263
Test name
Test status
Simulation time 72619428325 ps
CPU time 90.56 seconds
Started Mar 07 02:43:21 PM PST 24
Finished Mar 07 02:44:52 PM PST 24
Peak memory 256584 kb
Host smart-b8d2b0bb-e64f-4b9c-91bf-d944e57545b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445138939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.445138939
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3024455403
Short name T1175
Test name
Test status
Simulation time 90758650 ps
CPU time 1.08 seconds
Started Mar 07 02:43:20 PM PST 24
Finished Mar 07 02:43:22 PM PST 24
Peak memory 216032 kb
Host smart-210d2547-2dd6-4681-9d27-bc6bece5ac3c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024455403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3024455403
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1546490303
Short name T1627
Test name
Test status
Simulation time 7709863306 ps
CPU time 14.34 seconds
Started Mar 07 12:41:23 PM PST 24
Finished Mar 07 12:41:37 PM PST 24
Peak memory 224488 kb
Host smart-5ca638ab-83dd-43b4-a953-d80f3fe1b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546490303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1546490303
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2961853563
Short name T1912
Test name
Test status
Simulation time 419957424 ps
CPU time 3.69 seconds
Started Mar 07 02:43:17 PM PST 24
Finished Mar 07 02:43:22 PM PST 24
Peak memory 217452 kb
Host smart-cb1c223c-33d1-4eac-ac8a-2c415a5d7e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961853563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2961853563
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3323243535
Short name T1847
Test name
Test status
Simulation time 52188372524 ps
CPU time 36.17 seconds
Started Mar 07 12:41:24 PM PST 24
Finished Mar 07 12:42:00 PM PST 24
Peak memory 240488 kb
Host smart-8ad6d012-f190-4acd-9c3f-d9832fb3e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323243535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3323243535
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.829620934
Short name T1303
Test name
Test status
Simulation time 8780149665 ps
CPU time 13.33 seconds
Started Mar 07 02:43:21 PM PST 24
Finished Mar 07 02:43:34 PM PST 24
Peak memory 232488 kb
Host smart-fc714b23-85b7-4abf-94c2-375e008e3d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829620934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.829620934
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2780594870
Short name T388
Test name
Test status
Simulation time 19890210 ps
CPU time 0.77 seconds
Started Mar 07 12:41:17 PM PST 24
Finished Mar 07 12:41:18 PM PST 24
Peak memory 216148 kb
Host smart-88b27cef-3558-4034-b886-02344597ab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780594870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2780594870
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.621285246
Short name T482
Test name
Test status
Simulation time 39058329 ps
CPU time 0.72 seconds
Started Mar 07 02:43:11 PM PST 24
Finished Mar 07 02:43:12 PM PST 24
Peak memory 215488 kb
Host smart-bb8fc0ee-d29c-4e62-922b-52e5f8d9e84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621285246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.621285246
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2115917471
Short name T1804
Test name
Test status
Simulation time 134198863 ps
CPU time 3.08 seconds
Started Mar 07 02:43:25 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 217764 kb
Host smart-a20c5825-07da-422d-9954-acfb9f574dba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2115917471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2115917471
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.344684633
Short name T706
Test name
Test status
Simulation time 714384361 ps
CPU time 4.37 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:29 PM PST 24
Peak memory 219432 kb
Host smart-38c75a18-addf-415a-a940-fda4d45bdfbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=344684633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.344684633
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4205023201
Short name T1580
Test name
Test status
Simulation time 132360623 ps
CPU time 0.91 seconds
Started Mar 07 02:43:22 PM PST 24
Finished Mar 07 02:43:23 PM PST 24
Peak memory 205936 kb
Host smart-30368e14-8871-4b95-8bf8-30cfbbcc8793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205023201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4205023201
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4248130342
Short name T703
Test name
Test status
Simulation time 151910576980 ps
CPU time 273.19 seconds
Started Mar 07 12:41:24 PM PST 24
Finished Mar 07 12:45:57 PM PST 24
Peak memory 249344 kb
Host smart-4e476bfa-6d9a-46f6-b0d5-f88187aa1ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248130342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4248130342
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1181473067
Short name T1119
Test name
Test status
Simulation time 10746275190 ps
CPU time 14.38 seconds
Started Mar 07 02:43:21 PM PST 24
Finished Mar 07 02:43:35 PM PST 24
Peak memory 215768 kb
Host smart-42a4e678-d358-4562-af60-cd76263343fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181473067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1181473067
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2149641406
Short name T457
Test name
Test status
Simulation time 2866977367 ps
CPU time 26.54 seconds
Started Mar 07 12:41:24 PM PST 24
Finished Mar 07 12:41:51 PM PST 24
Peak memory 216384 kb
Host smart-ffeedf78-c29a-4657-a585-8961ab099673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149641406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2149641406
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2785774537
Short name T700
Test name
Test status
Simulation time 6052238916 ps
CPU time 12.53 seconds
Started Mar 07 02:43:16 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 215800 kb
Host smart-c7927b5c-fe16-498e-939e-9b0c441b36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785774537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2785774537
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3882342434
Short name T878
Test name
Test status
Simulation time 11565233570 ps
CPU time 8.95 seconds
Started Mar 07 12:41:18 PM PST 24
Finished Mar 07 12:41:27 PM PST 24
Peak memory 216232 kb
Host smart-2c31bb8c-379c-4abd-99a9-bca2ba2ef2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882342434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3882342434
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2060136791
Short name T412
Test name
Test status
Simulation time 116870324 ps
CPU time 2.82 seconds
Started Mar 07 12:41:15 PM PST 24
Finished Mar 07 12:41:18 PM PST 24
Peak memory 216200 kb
Host smart-5243c3ed-2146-4bc4-99f3-f235765178a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060136791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2060136791
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3762910646
Short name T368
Test name
Test status
Simulation time 282465367 ps
CPU time 6.64 seconds
Started Mar 07 02:43:14 PM PST 24
Finished Mar 07 02:43:21 PM PST 24
Peak memory 215788 kb
Host smart-1f575d22-9b70-4c44-ad9a-749c4c9e162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762910646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3762910646
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1054741851
Short name T1599
Test name
Test status
Simulation time 30496746 ps
CPU time 0.92 seconds
Started Mar 07 02:43:17 PM PST 24
Finished Mar 07 02:43:19 PM PST 24
Peak memory 204880 kb
Host smart-91f10622-ec71-4690-9719-3beeddc215f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054741851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1054741851
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3825320631
Short name T951
Test name
Test status
Simulation time 224843154 ps
CPU time 0.92 seconds
Started Mar 07 12:41:17 PM PST 24
Finished Mar 07 12:41:18 PM PST 24
Peak memory 206404 kb
Host smart-71211f07-a0ed-4351-b2e7-7318dd9a43dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825320631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3825320631
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1690221400
Short name T1465
Test name
Test status
Simulation time 6749082829 ps
CPU time 16.96 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:42 PM PST 24
Peak memory 249064 kb
Host smart-7ba1051b-c3e7-4901-afb5-25f7ad3cff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690221400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1690221400
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_upload.2640291238
Short name T1321
Test name
Test status
Simulation time 3227727224 ps
CPU time 8.02 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:43:31 PM PST 24
Peak memory 237968 kb
Host smart-147a1346-1130-47fa-a3e6-7dfb41590c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640291238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2640291238
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.483758973
Short name T1446
Test name
Test status
Simulation time 13200905 ps
CPU time 0.75 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:41:40 PM PST 24
Peak memory 205124 kb
Host smart-8ee83664-7afa-4733-beed-b090a8094e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483758973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.483758973
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.614549188
Short name T885
Test name
Test status
Simulation time 23444561 ps
CPU time 0.7 seconds
Started Mar 07 02:43:31 PM PST 24
Finished Mar 07 02:43:33 PM PST 24
Peak memory 204772 kb
Host smart-1b40a2c4-0aae-457c-abdd-aca9ae5a204a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614549188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.614549188
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.119901621
Short name T1242
Test name
Test status
Simulation time 455227931 ps
CPU time 3.13 seconds
Started Mar 07 02:43:26 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 236016 kb
Host smart-feec7258-c6fd-4c2b-91d5-13e52552d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119901621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.119901621
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1700082507
Short name T801
Test name
Test status
Simulation time 11526096261 ps
CPU time 7.1 seconds
Started Mar 07 12:41:24 PM PST 24
Finished Mar 07 12:41:31 PM PST 24
Peak memory 224564 kb
Host smart-068f43c4-1755-48f0-aca6-a729f193758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700082507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1700082507
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3812154891
Short name T1082
Test name
Test status
Simulation time 17211761 ps
CPU time 0.74 seconds
Started Mar 07 12:41:22 PM PST 24
Finished Mar 07 12:41:23 PM PST 24
Peak memory 206200 kb
Host smart-e99997f4-36d4-4bd1-ad32-c5115e255041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812154891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3812154891
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.424022779
Short name T364
Test name
Test status
Simulation time 18626948 ps
CPU time 0.8 seconds
Started Mar 07 02:43:25 PM PST 24
Finished Mar 07 02:43:26 PM PST 24
Peak memory 204492 kb
Host smart-53e6503c-08b2-406c-9503-1a6fe7814034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424022779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.424022779
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1800692924
Short name T1820
Test name
Test status
Simulation time 1744766282 ps
CPU time 17.44 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:41:57 PM PST 24
Peak memory 234684 kb
Host smart-e0049747-b927-4602-aa11-eaf926f834df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800692924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1800692924
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2434096098
Short name T273
Test name
Test status
Simulation time 22060366261 ps
CPU time 82.87 seconds
Started Mar 07 02:43:21 PM PST 24
Finished Mar 07 02:44:44 PM PST 24
Peak memory 264524 kb
Host smart-8a82f5b3-b33c-430d-ae16-8d2f9ef5fd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434096098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2434096098
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2026512696
Short name T1341
Test name
Test status
Simulation time 16323730088 ps
CPU time 109.81 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:45:13 PM PST 24
Peak memory 265092 kb
Host smart-7e8d91fd-f649-43ae-953b-5115a66a036d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026512696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2026512696
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2922439600
Short name T1459
Test name
Test status
Simulation time 1502914921 ps
CPU time 26.9 seconds
Started Mar 07 12:41:42 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 248188 kb
Host smart-8682ebd7-8637-47a2-ab18-bbe1385d0233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922439600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2922439600
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.106001308
Short name T1218
Test name
Test status
Simulation time 202384385016 ps
CPU time 476.25 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:49:36 PM PST 24
Peak memory 255672 kb
Host smart-af477603-8e78-47f6-b92a-fb83276a4030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106001308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
106001308
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2981522737
Short name T1007
Test name
Test status
Simulation time 58295020450 ps
CPU time 364.06 seconds
Started Mar 07 02:43:32 PM PST 24
Finished Mar 07 02:49:36 PM PST 24
Peak memory 256668 kb
Host smart-c899491f-73f8-4c1d-8692-e00f09225549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981522737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2981522737
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2115642460
Short name T1295
Test name
Test status
Simulation time 38591934775 ps
CPU time 47.53 seconds
Started Mar 07 02:43:31 PM PST 24
Finished Mar 07 02:44:18 PM PST 24
Peak memory 248408 kb
Host smart-3b0812b1-d6e7-41da-9bbb-9f621927917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115642460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2115642460
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2511961707
Short name T815
Test name
Test status
Simulation time 17536692315 ps
CPU time 24.23 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:42:06 PM PST 24
Peak memory 230820 kb
Host smart-7529b85f-5985-42e4-a7ee-c55246e43e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511961707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2511961707
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2340277943
Short name T1809
Test name
Test status
Simulation time 3119880633 ps
CPU time 11.19 seconds
Started Mar 07 02:43:21 PM PST 24
Finished Mar 07 02:43:33 PM PST 24
Peak memory 218632 kb
Host smart-e1ab02a2-817f-4b55-8dcf-9b3c6767fa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340277943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2340277943
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3715045825
Short name T613
Test name
Test status
Simulation time 2992796714 ps
CPU time 4.94 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:30 PM PST 24
Peak memory 224532 kb
Host smart-7e896252-0a8d-4501-9d4b-7b6b9c075c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715045825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3715045825
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1204707569
Short name T1067
Test name
Test status
Simulation time 61844071508 ps
CPU time 37.04 seconds
Started Mar 07 02:43:27 PM PST 24
Finished Mar 07 02:44:04 PM PST 24
Peak memory 233424 kb
Host smart-62b9a3b9-87cd-49db-87b0-8e9b3fd80903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204707569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1204707569
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.4268529977
Short name T582
Test name
Test status
Simulation time 86318819506 ps
CPU time 65.64 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:42:30 PM PST 24
Peak memory 234068 kb
Host smart-f4b170d9-5633-4856-b5d4-a4624b867315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268529977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4268529977
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3467224935
Short name T1577
Test name
Test status
Simulation time 16498237 ps
CPU time 1.02 seconds
Started Mar 07 02:43:24 PM PST 24
Finished Mar 07 02:43:25 PM PST 24
Peak memory 215996 kb
Host smart-164be8af-ad7a-4713-a836-3a2b65e5536f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467224935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3467224935
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.184457196
Short name T1645
Test name
Test status
Simulation time 3591541276 ps
CPU time 11.38 seconds
Started Mar 07 12:41:27 PM PST 24
Finished Mar 07 12:41:38 PM PST 24
Peak memory 224500 kb
Host smart-5bf118b7-21aa-447b-9873-e5fed8708520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184457196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
184457196
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3954130876
Short name T907
Test name
Test status
Simulation time 5362718195 ps
CPU time 19.29 seconds
Started Mar 07 02:43:28 PM PST 24
Finished Mar 07 02:43:47 PM PST 24
Peak memory 240052 kb
Host smart-a409c7a6-3c8e-4896-bd0b-166514178e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954130876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3954130876
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1486316592
Short name T216
Test name
Test status
Simulation time 323150687 ps
CPU time 3.04 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:43:26 PM PST 24
Peak memory 232092 kb
Host smart-97d47a1b-b056-4ae5-b705-8aa3e0c0fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486316592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1486316592
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4217921944
Short name T1375
Test name
Test status
Simulation time 1011057069 ps
CPU time 4.06 seconds
Started Mar 07 12:41:23 PM PST 24
Finished Mar 07 12:41:27 PM PST 24
Peak memory 224420 kb
Host smart-64b72922-3a5b-4bc3-95b9-e2b27ce0384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217921944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4217921944
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.1681542034
Short name T520
Test name
Test status
Simulation time 33286683 ps
CPU time 0.78 seconds
Started Mar 07 12:41:27 PM PST 24
Finished Mar 07 12:41:28 PM PST 24
Peak memory 216168 kb
Host smart-c0e01764-a7a1-49ca-ab6b-bdf48337399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681542034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.1681542034
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2116922194
Short name T541
Test name
Test status
Simulation time 41739440 ps
CPU time 0.73 seconds
Started Mar 07 02:43:24 PM PST 24
Finished Mar 07 02:43:25 PM PST 24
Peak memory 215624 kb
Host smart-b2109e94-9eed-466c-8c8e-ac84b885d298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116922194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2116922194
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1129409908
Short name T958
Test name
Test status
Simulation time 2246701416 ps
CPU time 4.85 seconds
Started Mar 07 02:43:24 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 222232 kb
Host smart-3b37b847-fa34-40d4-a4b9-339909b0299d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1129409908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1129409908
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2477866059
Short name T1376
Test name
Test status
Simulation time 1475720172 ps
CPU time 6.29 seconds
Started Mar 07 12:41:42 PM PST 24
Finished Mar 07 12:41:48 PM PST 24
Peak memory 218864 kb
Host smart-d99202f0-52ba-4d5d-83dc-091a1316e18a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2477866059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2477866059
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2118950298
Short name T1589
Test name
Test status
Simulation time 861871334 ps
CPU time 1.15 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:41:41 PM PST 24
Peak memory 207640 kb
Host smart-2c170976-4f38-4cd7-a770-e254f459a176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118950298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2118950298
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.270654666
Short name T1752
Test name
Test status
Simulation time 38190064 ps
CPU time 0.97 seconds
Started Mar 07 02:43:25 PM PST 24
Finished Mar 07 02:43:26 PM PST 24
Peak memory 205740 kb
Host smart-b2b2255e-975a-43a2-9e02-73a8b89cda75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270654666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.270654666
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1587964374
Short name T477
Test name
Test status
Simulation time 8306021501 ps
CPU time 20.61 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:43:44 PM PST 24
Peak memory 215872 kb
Host smart-65806356-4915-43fc-95c6-77a88c90c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587964374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1587964374
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2744423565
Short name T1036
Test name
Test status
Simulation time 1233646161 ps
CPU time 12 seconds
Started Mar 07 12:41:23 PM PST 24
Finished Mar 07 12:41:35 PM PST 24
Peak memory 216200 kb
Host smart-b9f6a1f2-7bd3-4e90-962a-db7ad92aeb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744423565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2744423565
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1359723042
Short name T1188
Test name
Test status
Simulation time 852462538 ps
CPU time 3.02 seconds
Started Mar 07 12:41:23 PM PST 24
Finished Mar 07 12:41:26 PM PST 24
Peak memory 216072 kb
Host smart-9ce3a2bc-c77f-4c31-ad3b-adf7c20b1bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359723042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1359723042
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1825349596
Short name T1886
Test name
Test status
Simulation time 4975938590 ps
CPU time 9.09 seconds
Started Mar 07 02:43:24 PM PST 24
Finished Mar 07 02:43:33 PM PST 24
Peak memory 215848 kb
Host smart-6cd7b638-8f9e-4e1b-bb2d-f8ea449c73f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825349596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1825349596
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2830618774
Short name T39
Test name
Test status
Simulation time 48524641 ps
CPU time 1.38 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:43:24 PM PST 24
Peak memory 215768 kb
Host smart-a1e1bef1-ac49-40f7-aee3-7eaaccdfca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830618774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2830618774
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3350928220
Short name T350
Test name
Test status
Simulation time 2175851058 ps
CPU time 5.03 seconds
Started Mar 07 12:41:23 PM PST 24
Finished Mar 07 12:41:28 PM PST 24
Peak memory 216208 kb
Host smart-6094dce1-19be-474e-bdbe-66664a591d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350928220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3350928220
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1229100336
Short name T1151
Test name
Test status
Simulation time 46290107 ps
CPU time 0.83 seconds
Started Mar 07 12:41:25 PM PST 24
Finished Mar 07 12:41:26 PM PST 24
Peak memory 205464 kb
Host smart-a549d408-6448-48e7-bf45-d738aabb94af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229100336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1229100336
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3118967518
Short name T1223
Test name
Test status
Simulation time 90403671 ps
CPU time 0.83 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:43:24 PM PST 24
Peak memory 204892 kb
Host smart-cf0b7ddf-0c06-452a-827d-5a3575156893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118967518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3118967518
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1066402053
Short name T1116
Test name
Test status
Simulation time 7282330120 ps
CPU time 23.51 seconds
Started Mar 07 02:43:32 PM PST 24
Finished Mar 07 02:43:56 PM PST 24
Peak memory 223964 kb
Host smart-dd6649e8-09ea-4a5b-8bb6-6bc17236cc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066402053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1066402053
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_upload.1708650534
Short name T749
Test name
Test status
Simulation time 1317171634 ps
CPU time 4.77 seconds
Started Mar 07 12:41:24 PM PST 24
Finished Mar 07 12:41:29 PM PST 24
Peak memory 218704 kb
Host smart-e5693aa7-3029-4319-8e53-dd84734880f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708650534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1708650534
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1199931977
Short name T1260
Test name
Test status
Simulation time 11541582 ps
CPU time 0.74 seconds
Started Mar 07 02:43:26 PM PST 24
Finished Mar 07 02:43:27 PM PST 24
Peak memory 204400 kb
Host smart-4b3e94df-5c50-4d8b-bb3a-4eecf02d850e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199931977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
199931977
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.366261572
Short name T1724
Test name
Test status
Simulation time 23563835 ps
CPU time 0.73 seconds
Started Mar 07 12:41:40 PM PST 24
Finished Mar 07 12:41:41 PM PST 24
Peak memory 205504 kb
Host smart-e412f06d-8d1b-4514-bbb0-1f04ce633277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366261572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.366261572
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2253110640
Short name T1383
Test name
Test status
Simulation time 1907073732 ps
CPU time 7.94 seconds
Started Mar 07 02:43:36 PM PST 24
Finished Mar 07 02:43:44 PM PST 24
Peak memory 223616 kb
Host smart-eabaa10b-73c3-4d09-9266-e42b67dbe0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253110640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2253110640
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3104034386
Short name T1178
Test name
Test status
Simulation time 481545850 ps
CPU time 3.41 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:41:45 PM PST 24
Peak memory 218572 kb
Host smart-586f0f3c-a1db-43ef-94ee-6e415d70a290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104034386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3104034386
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3150633762
Short name T586
Test name
Test status
Simulation time 27053303 ps
CPU time 0.78 seconds
Started Mar 07 02:43:27 PM PST 24
Finished Mar 07 02:43:28 PM PST 24
Peak memory 205472 kb
Host smart-a826cee5-977c-4da2-af18-9e878236783b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150633762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3150633762
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3597396953
Short name T509
Test name
Test status
Simulation time 65964885 ps
CPU time 0.8 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:41:42 PM PST 24
Peak memory 205316 kb
Host smart-1f56fd5e-9af9-4d79-9764-4f770f5b9e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597396953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3597396953
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1891670905
Short name T506
Test name
Test status
Simulation time 9412054374 ps
CPU time 22.69 seconds
Started Mar 07 02:43:36 PM PST 24
Finished Mar 07 02:43:59 PM PST 24
Peak memory 235740 kb
Host smart-1431dcde-54e6-4836-849a-a9d7bf0be0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891670905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1891670905
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.74965699
Short name T1464
Test name
Test status
Simulation time 97069745235 ps
CPU time 152.05 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:44:14 PM PST 24
Peak memory 255540 kb
Host smart-80692c9f-80f8-47d3-b8ac-2f807415382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74965699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.74965699
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2347274424
Short name T1534
Test name
Test status
Simulation time 31684213692 ps
CPU time 171.39 seconds
Started Mar 07 02:43:36 PM PST 24
Finished Mar 07 02:46:28 PM PST 24
Peak memory 253816 kb
Host smart-20efd6bb-047a-4937-8ead-96c8b4db5c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347274424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2347274424
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2440386427
Short name T320
Test name
Test status
Simulation time 169822590486 ps
CPU time 292.07 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:46:33 PM PST 24
Peak memory 250168 kb
Host smart-df09da93-5464-4a42-add6-8f81e31a9d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440386427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2440386427
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1861847210
Short name T529
Test name
Test status
Simulation time 53795667280 ps
CPU time 134.43 seconds
Started Mar 07 02:43:25 PM PST 24
Finished Mar 07 02:45:40 PM PST 24
Peak memory 252360 kb
Host smart-8275c146-35d5-4107-886e-bc8421f0a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861847210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1861847210
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3723919007
Short name T926
Test name
Test status
Simulation time 3983416370 ps
CPU time 41.32 seconds
Started Mar 07 12:41:40 PM PST 24
Finished Mar 07 12:42:21 PM PST 24
Peak memory 249280 kb
Host smart-1a84ef7a-2a66-48c7-b764-64c299b400eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723919007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3723919007
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1218924947
Short name T592
Test name
Test status
Simulation time 6170453849 ps
CPU time 19.8 seconds
Started Mar 07 02:43:36 PM PST 24
Finished Mar 07 02:43:56 PM PST 24
Peak memory 240864 kb
Host smart-98622269-145a-48fd-a5dc-7f3770f912c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218924947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1218924947
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1232611560
Short name T399
Test name
Test status
Simulation time 460650037 ps
CPU time 5.83 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:41:47 PM PST 24
Peak memory 232720 kb
Host smart-5fc369cf-2e83-490c-a659-44b17cd053bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232611560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1232611560
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1417661048
Short name T1440
Test name
Test status
Simulation time 168485643 ps
CPU time 4.26 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:41:44 PM PST 24
Peak memory 233576 kb
Host smart-81f3dc4a-7e5c-4df9-84d0-c37ef346e1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417661048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1417661048
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3243463444
Short name T796
Test name
Test status
Simulation time 1953871637 ps
CPU time 9.28 seconds
Started Mar 07 02:43:23 PM PST 24
Finished Mar 07 02:43:32 PM PST 24
Peak memory 233608 kb
Host smart-50e33637-e7bf-419d-abea-175c5e5afdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243463444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3243463444
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3918378252
Short name T1301
Test name
Test status
Simulation time 21763243788 ps
CPU time 12.44 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:41:54 PM PST 24
Peak memory 237516 kb
Host smart-8e333e2b-13f5-4352-a809-034756deeaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918378252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3918378252
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.814415917
Short name T1504
Test name
Test status
Simulation time 634088940 ps
CPU time 2.82 seconds
Started Mar 07 02:43:36 PM PST 24
Finished Mar 07 02:43:39 PM PST 24
Peak memory 232860 kb
Host smart-3417dc5e-0d55-42ff-9291-3160a9352d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814415917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.814415917
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.797817544
Short name T1909
Test name
Test status
Simulation time 103638133 ps
CPU time 1.04 seconds
Started Mar 07 02:43:24 PM PST 24
Finished Mar 07 02:43:25 PM PST 24
Peak memory 217296 kb
Host smart-323c4962-1aaa-4f72-b8c7-9e1bac81fbc2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797817544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.797817544
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3266117643
Short name T266
Test name
Test status
Simulation time 7797646776 ps
CPU time 26.86 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:42:07 PM PST 24
Peak memory 228308 kb
Host smart-55cf9055-1829-4a50-8168-e16730e0a435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266117643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3266117643
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3683581399
Short name T247
Test name
Test status
Simulation time 683402571 ps
CPU time 3.9 seconds
Started Mar 07 02:43:25 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 216008 kb
Host smart-65d6c302-f3e5-42ff-a1fc-b546e68a076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683581399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3683581399
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2701789537
Short name T1725
Test name
Test status
Simulation time 13093646296 ps
CPU time 12.32 seconds
Started Mar 07 02:43:26 PM PST 24
Finished Mar 07 02:43:38 PM PST 24
Peak memory 228020 kb
Host smart-a93cfd0e-7e8b-47eb-99eb-0673215ced27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701789537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2701789537
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2771818336
Short name T361
Test name
Test status
Simulation time 4050177452 ps
CPU time 16.24 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:41:56 PM PST 24
Peak memory 240372 kb
Host smart-1b4a5dad-82fc-418d-9af7-eb5cd42cb434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771818336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2771818336
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2544278957
Short name T447
Test name
Test status
Simulation time 29821955 ps
CPU time 0.74 seconds
Started Mar 07 02:43:20 PM PST 24
Finished Mar 07 02:43:20 PM PST 24
Peak memory 215644 kb
Host smart-7b785249-c7ae-4b21-bf64-12fe88d996f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544278957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2544278957
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3673097483
Short name T805
Test name
Test status
Simulation time 152081062 ps
CPU time 0.76 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:41:42 PM PST 24
Peak memory 216104 kb
Host smart-893b6398-74bf-4edf-b3a5-ecbb07a76148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673097483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3673097483
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3226620227
Short name T76
Test name
Test status
Simulation time 1536472840 ps
CPU time 6.41 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:41:46 PM PST 24
Peak memory 222088 kb
Host smart-93eb80b3-e1ed-445f-bf94-688c76cc06fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3226620227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3226620227
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.749799264
Short name T901
Test name
Test status
Simulation time 328750501 ps
CPU time 3.57 seconds
Started Mar 07 02:43:25 PM PST 24
Finished Mar 07 02:43:29 PM PST 24
Peak memory 222112 kb
Host smart-f1f96d42-ee03-4aa4-af65-8fc34ed7b453
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=749799264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.749799264
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2151390498
Short name T898
Test name
Test status
Simulation time 66604240116 ps
CPU time 251.15 seconds
Started Mar 07 12:41:40 PM PST 24
Finished Mar 07 12:45:52 PM PST 24
Peak memory 255620 kb
Host smart-c8c31ace-3506-4975-83ac-43056348448e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151390498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2151390498
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.300675176
Short name T45
Test name
Test status
Simulation time 59482169462 ps
CPU time 352.18 seconds
Started Mar 07 02:43:29 PM PST 24
Finished Mar 07 02:49:21 PM PST 24
Peak memory 265840 kb
Host smart-0421d463-a506-4e0c-a5f4-5742a37a8ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300675176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.300675176
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2579213173
Short name T922
Test name
Test status
Simulation time 6185420186 ps
CPU time 12.96 seconds
Started Mar 07 02:43:31 PM PST 24
Finished Mar 07 02:43:45 PM PST 24
Peak memory 215792 kb
Host smart-5f3379d4-5b7b-41fa-82a5-afa586cababd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579213173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2579213173
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2753698371
Short name T324
Test name
Test status
Simulation time 5992982929 ps
CPU time 25.62 seconds
Started Mar 07 12:41:40 PM PST 24
Finished Mar 07 12:42:06 PM PST 24
Peak memory 216396 kb
Host smart-8bfe9d71-0d04-4e1b-b296-29762bf970b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753698371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2753698371
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1103715805
Short name T1711
Test name
Test status
Simulation time 13131726475 ps
CPU time 11.56 seconds
Started Mar 07 02:43:24 PM PST 24
Finished Mar 07 02:43:36 PM PST 24
Peak memory 215704 kb
Host smart-1dddf0b6-38cc-44c1-8f0b-4fb17f76210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103715805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1103715805
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4160200248
Short name T77
Test name
Test status
Simulation time 827580656 ps
CPU time 2.91 seconds
Started Mar 07 12:41:39 PM PST 24
Finished Mar 07 12:41:42 PM PST 24
Peak memory 207720 kb
Host smart-2fe9ff47-ef7d-461e-b5cc-428d77b158db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160200248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4160200248
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.304186649
Short name T1208
Test name
Test status
Simulation time 138856899 ps
CPU time 1.08 seconds
Started Mar 07 02:43:36 PM PST 24
Finished Mar 07 02:43:38 PM PST 24
Peak memory 206692 kb
Host smart-c59c8087-31f7-4050-98f6-cdc9010985ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304186649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.304186649
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3309512755
Short name T853
Test name
Test status
Simulation time 1019800200 ps
CPU time 1.98 seconds
Started Mar 07 12:41:40 PM PST 24
Finished Mar 07 12:41:43 PM PST 24
Peak memory 216248 kb
Host smart-15540c1a-07bd-4b02-b30f-028316fea513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309512755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3309512755
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1923158581
Short name T1270
Test name
Test status
Simulation time 428658806 ps
CPU time 0.91 seconds
Started Mar 07 02:43:32 PM PST 24
Finished Mar 07 02:43:34 PM PST 24
Peak memory 204884 kb
Host smart-a47ed120-f0a2-4f29-8d12-de5e1f6d421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923158581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1923158581
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2278802195
Short name T511
Test name
Test status
Simulation time 36924037 ps
CPU time 0.79 seconds
Started Mar 07 12:41:43 PM PST 24
Finished Mar 07 12:41:44 PM PST 24
Peak memory 205476 kb
Host smart-f6344269-316d-445f-8908-70b2a1fd0899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278802195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2278802195
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3152309294
Short name T1579
Test name
Test status
Simulation time 1091585081 ps
CPU time 4.16 seconds
Started Mar 07 02:43:29 PM PST 24
Finished Mar 07 02:43:33 PM PST 24
Peak memory 233756 kb
Host smart-c410d7a5-475c-44c1-a557-b6e8c4245b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152309294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3152309294
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_upload.3990912693
Short name T601
Test name
Test status
Simulation time 1110963796 ps
CPU time 11.29 seconds
Started Mar 07 12:41:41 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 230812 kb
Host smart-1dd710d9-6c98-44da-b628-b2836a848895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990912693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3990912693
Directory /workspace/9.spi_device_upload/latest
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