Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14303500	1			T1	1006		T2	1		T3	1
all_values[1]	14303500	1			T1	1006		T2	1		T3	1
all_values[2]	14303500	1			T1	1006		T2	1		T3	1
all_values[3]	14303500	1			T1	1006		T2	1		T3	1
all_values[4]	14303500	1			T1	1006		T2	1		T3	1
all_values[5]	14303500	1			T1	1006		T2	1		T3	1
all_values[6]	14303500	1			T1	1006		T2	1		T3	1
all_values[7]	14303500	1			T1	1006		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110327023

1

T1

8048

T2

8

T3

8

auto[1]

4100977

1

T46

73

T62

28678

T63

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114276273

1

T1

8048

T2

8

T3

8

auto[1]

151727

1

T4

40

T5

1438

T11

450

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	13608841	1			T1	1006		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	85903	1			T4	20		T5	741		T11	322
all_values[0]	auto[1]	auto[0]	605084	1			T46	2		T62	4486		T63	5
all_values[0]	auto[1]	auto[1]	3672	1			T46	2		T62	290		T63	4
all_values[1]	auto[0]	auto[0]	13788028	1			T1	1006		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	40034	1			T4	20		T5	485		T11	67
all_values[1]	auto[1]	auto[0]	473703	1			T46	4		T62	8		T63	8
all_values[1]	auto[1]	auto[1]	1735	1			T46	5		T62	1		T63	4
all_values[2]	auto[0]	auto[0]	13835389	1			T1	1006		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	15218	1			T5	212		T11	61		T21	59
all_values[2]	auto[1]	auto[0]	451973	1			T46	7		T62	4698		T63	2
all_values[2]	auto[1]	auto[1]	920	1			T46	2		T62	84		T63	1
all_values[3]	auto[0]	auto[0]	13726905	1			T1	1006		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	401	1			T46	2		T62	2		T63	3
all_values[3]	auto[1]	auto[0]	575831	1			T46	5		T62	2		T63	4
all_values[3]	auto[1]	auto[1]	363	1			T46	3		T62	1		T63	1
all_values[4]	auto[0]	auto[0]	13656427	1			T1	1006		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	400	1			T62	2		T63	1		T148	1
all_values[4]	auto[1]	auto[0]	646280	1			T46	10		T62	4776		T63	4
all_values[4]	auto[1]	auto[1]	393	1			T46	2		T62	2		T63	2
all_values[5]	auto[0]	auto[0]	13824993	1			T1	1006		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	812	1			T45	5		T46	1		T172	6
all_values[5]	auto[1]	auto[0]	477349	1			T46	8		T62	4770		T63	8
all_values[5]	auto[1]	auto[1]	346	1			T46	3		T62	7		T63	1
all_values[6]	auto[0]	auto[0]	14024748	1			T1	1006		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	398	1			T46	3		T63	1		T168	5
all_values[6]	auto[1]	auto[0]	277975	1			T46	8		T62	4772		T63	5
all_values[6]	auto[1]	auto[1]	379	1			T46	4		T62	3		T63	6
all_values[7]	auto[0]	auto[0]	13718124	1			T1	1006		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	402	1			T46	3		T62	1		T63	2
all_values[7]	auto[1]	auto[0]	584623	1			T46	5		T62	4772		T63	6
all_values[7]	auto[1]	auto[1]	351	1			T46	3		T62	6		T63	3