Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	83995	1			T3	8		T4	22		T5	183
auto[SpiFlashAddrCfg]	17960	1			T3	14		T4	7		T5	77
auto[SpiFlashAddr3b]	21948	1			T1	6		T3	6		T4	3
auto[SpiFlashAddr4b]	18241	1			T1	3		T3	4		T4	3

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82311

1

T1

9

T3

32

T4

26

auto[1]

59833

1

T4

9

T5

173

T11

235

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75798

1

T1

2

T3

26

T4

7

auto[1]

66346

1

T1

7

T3

6

T4

28

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	95077	1			T1	2		T3	12		T4	26
values[1]	2583	1			T4	1		T5	8		T11	8
values[2]	3575	1			T5	8		T11	16		T21	8
values[3]	3507	1			T3	4		T5	11		T8	4
values[4]	3345	1			T3	2		T5	13		T11	17
values[5]	3498	1			T4	1		T5	4		T10	4
values[6]	3495	1			T4	1		T5	15		T9	2
values[7]	3505	1			T3	6		T4	1		T5	19
values[8]	23559	1			T1	7		T3	8		T4	5

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72835

1

T3

32

T4

35

T8

26

auto[1]

69309

1

T1

9

T5

401

T11

701

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

137058

1

T1

9

T3

30

T4

32

write

5086

1

T3

2

T4

3

T5

25

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

47390

1

T1

4

T3

6

T4

9

valids[0x1]

94754

1

T1

5

T3

26

T4

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	3765	1			T4	2		T5	13		T8	8
internal_process_ops[0x5a]	3799	1			T3	2		T4	1		T5	14
internal_process_ops[0x05]	50863	1			T4	16		T5	74		T10	2
internal_process_ops[0x35]	3720	1			T5	12		T8	2		T11	13
internal_process_ops[0x15]	3817	1			T4	2		T5	13		T8	2
internal_process_ops[0x03]	2574	1			T1	2		T4	1		T5	4
internal_process_ops[0x0b]	2596	1			T1	3		T3	4		T5	5
internal_process_ops[0x3b]	2671	1			T1	4		T3	4		T4	1
internal_process_ops[0x6b]	2622	1			T5	5		T8	4		T9	2
internal_process_ops[0xbb]	2655	1			T5	4		T9	4		T11	2
internal_process_ops[0xeb]	2622	1			T3	2		T5	6		T9	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139652

1

T1

9

T3

32

T4

32

auto[1]

2492

1

T4

3

T5

14

T11

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137195

1

T1

9

T3

32

T4

33

auto[1]

4949

1

T4

2

T5

32

T11

22

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

25845

1

T3

6

T4

20

T8

16

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

14470

1

T4

2

T17

28

T29

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

5009

1

T3

14

T4

5

T8

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

4305

1

T4

1

T17

19

T29

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

6302

1

T3

6

T4

1

T8

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

5115

1

T4

2

T17

33

T29

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

5083

1

T3

4

T9

2

T10

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

4333

1

T4

1

T17

22

T29

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

192

1

T3

2

T33

2

T169

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

114

1

T36

1

T37

2

T138

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

136

1

T17

1

T30

3

T36

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

178

1

T17

1

T29

4

T30

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

159

1

T33

2

T30

1

T36

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

121

1

T30

1

T35

1

T41

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

120

1

T30

1

T36

2

T37

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

174

1

T4

1

T17

1

T35

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

181

1

T22

2

T43

2

T30

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

117

1

T37

1

T39

1

T154

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

133

1

T30

1

T35

2

T36

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

129

1

T17

3

T30

1

T35

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

163

1

T17

1

T30

2

T35

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

133

1

T30

2

T35

1

T170

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

162

1

T30

2

T35

1

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

161

1

T4

2

T17

1

T37

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

25067

1

T5

129

T11

373

T21

103

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

17280

1

T5

46

T11

123

T21

192

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

3888

1

T5

33

T11

28

T21

28

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

3541

1

T5

37

T11

31

T21

30

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

4717

1

T1

6

T5

42

T11

31

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

4600

1

T5

39

T11

34

T21

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

3898

1

T1

3

T5

15

T11

31

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

3605

1

T5

35

T11

42

T21

26

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

185

1

T11

1

T19

1

T46

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

193

1

T5

1

T21

2

T18

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

163

1

T5

4

T21

4

T15

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

172

1

T5

3

T21

6

T18

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

150

1

T21

2

T18

3

T19

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

152

1

T5

2

T11

1

T21

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

186

1

T5

1

T21

3

T15

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

155

1

T5

4

T21

1

T46

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

150

1

T21

1

T18

3

T62

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

159

1

T5

2

T21

2

T18

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

163

1

T19

3

T46

1

T85

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

182

1

T5

1

T11

4

T15

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

167

1

T5

3

T46

1

T85

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

166

1

T5

1

T11

1

T46

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

184

1

T5

3

T19

1

T46

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

186

1

T11

1

T21

4

T19

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	9720	1			T4	2		T12	4		T49	2
auto[0]	values[0]	valids[0x1]	36988	1			T3	12		T4	24		T8	22
auto[0]	values[1]	valids[0x1]	1272	1			T4	1		T49	2		T17	6
auto[0]	values[2]	valids[0x0]	1269	1			T17	2		T32	6		T30	10
auto[0]	values[2]	valids[0x1]	717	1			T17	6		T30	1		T35	1
auto[0]	values[3]	valids[0x0]	1302	1			T3	4		T8	4		T9	4
auto[0]	values[3]	valids[0x1]	742	1			T17	3		T29	2		T90	4
auto[0]	values[4]	valids[0x0]	1167	1			T3	2		T22	4		T17	2
auto[0]	values[4]	valids[0x1]	715	1			T17	2		T30	4		T35	6
auto[0]	values[5]	valids[0x0]	1258	1			T4	1		T10	4		T34	6
auto[0]	values[5]	valids[0x1]	702	1			T17	4		T30	8		T35	1
auto[0]	values[6]	valids[0x0]	1297	1			T9	2		T17	1		T171	8
auto[0]	values[6]	valids[0x1]	689	1			T4	1		T49	2		T17	3
auto[0]	values[7]	valids[0x0]	1289	1			T4	1		T9	2		T22	2
auto[0]	values[7]	valids[0x1]	663	1			T3	6		T49	4		T17	2
auto[0]	values[8]	valids[0x0]	8230	1			T4	5		T9	4		T22	2
auto[0]	values[8]	valids[0x1]	4815	1			T3	8		T89	2		T74	2
auto[1]	values[0]	valids[0x0]	10009	1			T5	73		T11	71		T21	78
auto[1]	values[0]	valids[0x1]	38360	1			T1	2		T5	171		T11	461
auto[1]	values[1]	valids[0x1]	1311	1			T5	8		T11	8		T21	1
auto[1]	values[2]	valids[0x0]	979	1			T5	6		T11	11		T21	6
auto[1]	values[2]	valids[0x1]	610	1			T5	2		T11	5		T21	2
auto[1]	values[3]	valids[0x0]	885	1			T5	4		T11	3		T21	5
auto[1]	values[3]	valids[0x1]	578	1			T5	7		T11	2		T21	4
auto[1]	values[4]	valids[0x0]	866	1			T5	10		T11	11		T21	9
auto[1]	values[4]	valids[0x1]	597	1			T5	3		T11	6		T21	4
auto[1]	values[5]	valids[0x0]	943	1			T5	2		T11	12		T21	12
auto[1]	values[5]	valids[0x1]	595	1			T5	2		T11	7		T21	3
auto[1]	values[6]	valids[0x0]	892	1			T5	11		T11	5		T21	8
auto[1]	values[6]	valids[0x1]	617	1			T5	4		T11	5		T21	4
auto[1]	values[7]	valids[0x0]	934	1			T5	12		T11	10		T21	2
auto[1]	values[7]	valids[0x1]	619	1			T5	7		T11	2		T21	7
auto[1]	values[8]	valids[0x0]	6350	1			T1	4		T5	55		T11	41
auto[1]	values[8]	valids[0x1]	4164	1			T1	3		T5	24		T11	41