Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38639

1

T1

17

T3

1

T4

11

auto[1]

51542

1

T4

16

T5

92

T11

397

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32481

1

T1

17

T3

1

T4

9

auto[1]

57700

1

T4

18

T5

99

T11

422

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	14349	1			T1	3		T3	1		T4	1
auto[524288:1048575]	11574	1			T4	5		T5	21		T8	2
auto[1048576:1572863]	10928	1			T1	3		T4	21		T5	39
auto[1572864:2097151]	11471	1			T5	56		T8	2		T10	4
auto[2097152:2621439]	9909	1			T5	3		T8	3		T11	95
auto[2621440:3145727]	10443	1			T1	2		T5	30		T8	3
auto[3145728:3670015]	11109	1			T1	4		T5	13		T8	6
auto[3670016:4194303]	10398	1			T1	5		T5	1		T8	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88300

1

T1

17

T3

1

T4

25

auto[1]

1881

1

T4

2

T5

1

T11

15

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72345

1

T1

17

T3

1

T4

27

auto[1]

17836

1

T5

43

T11

84

T21

58

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	3782	1			T1	3		T3	1		T5	17
auto[0]	auto[0]	auto[0:524287]	auto[1]	1472	1			T4	1		T5	9		T11	6
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	2751	1			T4	4		T5	7		T8	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	1139	1			T4	1		T5	1		T11	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	2730	1			T1	3		T4	3		T5	12
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	1064	1			T4	2		T5	4		T11	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	2717	1			T5	23		T8	2		T10	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	1052	1			T5	9		T11	6		T21	7
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	2491	1			T8	3		T11	6		T12	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	979	1			T11	1		T21	1		T18	12
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	2717	1			T1	2		T5	5		T8	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	1018	1			T5	4		T11	4		T21	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	2606	1			T1	4		T5	4		T8	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	1030	1			T5	2		T11	6		T21	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	2628	1			T1	5		T5	1		T8	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	995	1			T11	3		T21	2		T17	6
auto[0]	auto[1]	auto[0:524287]	auto[0]	701	1			T5	1		T11	1		T21	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	322	1			T5	1		T11	1		T21	2
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	589	1			T5	1		T17	2		T18	13
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	294	1			T17	3		T18	2		T19	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	636	1			T5	5		T11	4		T21	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	292	1			T5	1		T11	2		T21	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	597	1			T5	2		T11	3		T21	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	280	1			T5	1		T11	2		T21	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	696	1			T11	8		T21	3		T18	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	315	1			T5	3		T11	1		T21	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	649	1			T5	5		T11	2		T21	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	266	1			T5	4		T11	1		T15	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	642	1			T11	1		T21	5		T18	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	299	1			T11	1		T21	2		T17	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	600	1			T21	3		T17	5		T18	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	290	1			T21	4		T17	1		T85	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	641	1			T5	7		T11	2		T22	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	6253	1			T5	16		T11	20		T22	84
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	492	1			T5	2		T11	2		T21	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4976	1			T5	6		T11	39		T21	13
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	501	1			T4	2		T5	3		T11	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	4467	1			T4	14		T5	5		T11	71
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	484	1			T5	7		T11	2		T21	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4702	1			T5	12		T11	52		T21	68
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	430	1			T11	2		T19	1		T20	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3751	1			T11	64		T19	1		T20	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	478	1			T5	3		T11	1		T17	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4395	1			T5	5		T11	9		T17	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	482	1			T5	2		T11	3		T21	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4493	1			T5	5		T11	53		T21	19
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	461	1			T11	1		T21	1		T15	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4168	1			T11	16		T21	6		T15	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	129	1			T21	2		T19	1		T46	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	1049	1			T21	11		T19	15		T46	38
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	119	1			T5	1		T18	5		T46	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1214	1			T5	3		T18	10		T46	14
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	119	1			T5	4		T11	2		T19	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1119	1			T5	5		T11	19		T19	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	109	1			T5	1		T11	1		T85	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1530	1			T5	1		T11	7		T85	21
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	120	1			T11	2		T19	1		T85	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1127	1			T11	11		T19	1		T85	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	125	1			T5	2		T11	1		T18	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	795	1			T5	2		T11	14		T18	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	140	1			T21	1		T18	2		T19	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1417	1			T21	5		T18	10		T19	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	119	1			T21	1		T18	3		T137	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1137	1			T21	5		T18	9		T137	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	30374	1			T1	17		T3	1		T4	10
auto[0]	auto[0]	auto[1]	797	1			T4	1		T11	4		T21	3
auto[0]	auto[1]	auto[0]	7268	1			T5	24		T11	25		T21	31
auto[0]	auto[1]	auto[1]	200	1			T11	2		T21	2		T46	2
auto[1]	auto[0]	auto[0]	40448	1			T4	15		T5	72		T11	333
auto[1]	auto[0]	auto[1]	726	1			T4	1		T5	1		T11	7
auto[1]	auto[1]	auto[0]	10210	1			T5	19		T11	55		T21	23
auto[1]	auto[1]	auto[1]	158	1			T11	2		T21	2		T46	1