Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43419

1

T3

32

T4

26

T8

26

auto[1]

29416

1

T4

9

T17

109

T29

30

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	10540	1			T49	14		T17	54		T33	8
values[1]	8700	1			T9	16		T88	14		T29	30
values[2]	8365	1			T17	47		T30	46		T35	20
values[3]	9728	1			T10	6		T89	4		T17	40
values[4]	9469	1			T12	4		T74	10		T206	102
values[5]	8152	1			T22	104		T227	24		T17	60
values[6]	8483	1			T4	35		T8	26		T31	10
values[7]	9398	1			T3	32		T34	28		T30	76

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	8123	1			T17	55		T169	10		T30	105
values[1]	8836	1			T4	35		T89	4		T74	10
values[2]	9531	1			T12	4		T49	14		T17	27
values[3]	9199	1			T29	30		T228	6		T30	92
values[4]	9115	1			T9	16		T34	28		T17	102
values[5]	9717	1			T22	104		T88	14		T17	40
values[6]	9055	1			T31	10		T30	94		T35	91
values[7]	9259	1			T3	32		T8	26		T10	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	757	1			T17	25		T169	10		T30	17
auto[0]	values[0]	values[1]	991	1			T30	12		T229	6		T170	12
auto[0]	values[0]	values[2]	1255	1			T49	14		T36	17		T25	10
auto[0]	values[0]	values[3]	742	1			T30	7		T36	15		T138	7
auto[0]	values[0]	values[4]	714	1			T33	8		T35	13		T224	24
auto[0]	values[0]	values[5]	1060	1			T36	26		T196	34		T39	16
auto[0]	values[0]	values[6]	649	1			T36	9		T138	7		T23	27
auto[0]	values[0]	values[7]	542	1			T17	13		T36	11		T230	8
auto[0]	values[1]	values[0]	532	1			T36	9		T170	12		T154	13
auto[0]	values[1]	values[1]	751	1			T30	8		T191	32		T41	29
auto[0]	values[1]	values[2]	702	1			T231	12		T170	10		T25	12
auto[0]	values[1]	values[3]	610	1			T36	14		T37	24		T232	36
auto[0]	values[1]	values[4]	526	1			T9	16		T30	9		T208	10
auto[0]	values[1]	values[5]	668	1			T88	14		T36	11		T41	15
auto[0]	values[1]	values[6]	690	1			T35	10		T37	25		T170	13
auto[0]	values[1]	values[7]	577	1			T37	11		T138	17		T50	6
auto[0]	values[2]	values[0]	604	1			T30	22		T35	14		T36	13
auto[0]	values[2]	values[1]	534	1			T36	10		T209	6		T25	20
auto[0]	values[2]	values[2]	778	1			T17	7		T30	16		T37	12
auto[0]	values[2]	values[3]	668	1			T37	12		T39	9		T23	10
auto[0]	values[2]	values[4]	515	1			T25	8		T233	9		T223	46
auto[0]	values[2]	values[5]	646	1			T17	9		T234	12		T235	16
auto[0]	values[2]	values[6]	426	1			T36	27		T37	15		T41	12
auto[0]	values[2]	values[7]	635	1			T190	13		T236	22		T157	13
auto[0]	values[3]	values[0]	738	1			T219	20		T41	8		T209	10
auto[0]	values[3]	values[1]	708	1			T89	4		T30	9		T37	8
auto[0]	values[3]	values[2]	694	1			T35	14		T209	11		T237	6
auto[0]	values[3]	values[3]	942	1			T36	8		T238	10		T138	17
auto[0]	values[3]	values[4]	866	1			T17	8		T171	10		T36	14
auto[0]	values[3]	values[5]	487	1			T17	12		T239	8		T204	6
auto[0]	values[3]	values[6]	669	1			T30	13		T39	14		T214	24
auto[0]	values[3]	values[7]	754	1			T10	6		T44	18		T198	10
auto[0]	values[4]	values[0]	576	1			T30	12		T36	11		T240	2
auto[0]	values[4]	values[1]	673	1			T74	10		T241	10		T25	11
auto[0]	values[4]	values[2]	648	1			T12	4		T37	40		T209	34
auto[0]	values[4]	values[3]	754	1			T30	18		T36	14		T202	8
auto[0]	values[4]	values[4]	651	1			T30	17		T242	30		T50	13
auto[0]	values[4]	values[5]	781	1			T35	41		T50	11		T243	6
auto[0]	values[4]	values[6]	793	1			T36	20		T244	28		T23	14
auto[0]	values[4]	values[7]	939	1			T206	102		T37	10		T41	15
auto[0]	values[5]	values[0]	590	1			T41	10		T245	4		T246	26
auto[0]	values[5]	values[1]	526	1			T35	15		T36	28		T195	30
auto[0]	values[5]	values[2]	586	1			T36	10		T37	20		T209	18
auto[0]	values[5]	values[3]	739	1			T36	12		T37	22		T39	10
auto[0]	values[5]	values[4]	647	1			T17	35		T90	10		T23	7
auto[0]	values[5]	values[5]	682	1			T22	104		T35	9		T23	20
auto[0]	values[5]	values[6]	691	1			T35	6		T39	54		T154	12
auto[0]	values[5]	values[7]	566	1			T227	24		T36	14		T247	10
auto[0]	values[6]	values[0]	554	1			T17	12		T248	4		T36	12
auto[0]	values[6]	values[1]	545	1			T4	26		T32	67		T43	10
auto[0]	values[6]	values[2]	714	1			T37	25		T249	16		T154	26
auto[0]	values[6]	values[3]	378	1			T228	6		T30	12		T203	12
auto[0]	values[6]	values[4]	565	1			T17	14		T41	13		T154	26
auto[0]	values[6]	values[5]	776	1			T35	15		T209	8		T25	12
auto[0]	values[6]	values[6]	673	1			T31	10		T30	22		T36	17
auto[0]	values[6]	values[7]	593	1			T8	26		T30	13		T36	17
auto[0]	values[7]	values[0]	618	1			T30	10		T154	10		T250	24
auto[0]	values[7]	values[1]	633	1			T37	9		T251	12		T204	12
auto[0]	values[7]	values[2]	761	1			T35	13		T252	10		T253	67
auto[0]	values[7]	values[3]	639	1			T30	13		T41	45		T192	22
auto[0]	values[7]	values[4]	769	1			T34	28		T39	11		T23	6
auto[0]	values[7]	values[5]	408	1			T35	7		T254	2		T23	19
auto[0]	values[7]	values[6]	715	1			T35	8		T37	20		T170	9
auto[0]	values[7]	values[7]	806	1			T3	32		T30	15		T35	11
auto[1]	values[0]	values[0]	469	1			T17	9		T30	6		T35	9
auto[1]	values[0]	values[1]	534	1			T30	8		T170	8		T154	10
auto[1]	values[0]	values[2]	395	1			T36	9		T25	10		T255	15
auto[1]	values[0]	values[3]	670	1			T30	18		T36	5		T138	15
auto[1]	values[0]	values[4]	483	1			T35	8		T138	7		T222	18
auto[1]	values[0]	values[5]	397	1			T36	14		T39	14		T256	16
auto[1]	values[0]	values[6]	414	1			T36	11		T138	22		T23	10
auto[1]	values[0]	values[7]	468	1			T17	7		T36	16		T41	5
auto[1]	values[1]	values[0]	468	1			T36	11		T170	8		T154	7
auto[1]	values[1]	values[1]	577	1			T30	12		T41	18		T154	14
auto[1]	values[1]	values[2]	212	1			T118	4		T170	10		T25	8
auto[1]	values[1]	values[3]	341	1			T29	30		T36	6		T37	13
auto[1]	values[1]	values[4]	422	1			T30	11		T25	4		T221	9
auto[1]	values[1]	values[5]	570	1			T36	33		T41	9		T187	9
auto[1]	values[1]	values[6]	774	1			T35	41		T37	65		T170	7
auto[1]	values[1]	values[7]	280	1			T37	9		T138	3		T50	14
auto[1]	values[2]	values[0]	346	1			T30	4		T35	6		T36	7
auto[1]	values[2]	values[1]	365	1			T36	14		T209	14		T25	10
auto[1]	values[2]	values[2]	674	1			T17	20		T30	4		T37	14
auto[1]	values[2]	values[3]	455	1			T37	25		T39	11		T23	13
auto[1]	values[2]	values[4]	545	1			T25	23		T233	11		T223	8
auto[1]	values[2]	values[5]	441	1			T17	11		T234	8		T209	8
auto[1]	values[2]	values[6]	351	1			T36	13		T37	61		T41	8
auto[1]	values[2]	values[7]	382	1			T190	48		T157	9		T223	12
auto[1]	values[3]	values[0]	503	1			T41	20		T209	38		T187	9
auto[1]	values[3]	values[1]	366	1			T30	11		T37	17		T138	8
auto[1]	values[3]	values[2]	255	1			T35	7		T209	9		T216	22
auto[1]	values[3]	values[3]	540	1			T36	12		T138	4		T23	18
auto[1]	values[3]	values[4]	466	1			T17	12		T36	13		T38	34
auto[1]	values[3]	values[5]	548	1			T17	8		T204	14		T257	4
auto[1]	values[3]	values[6]	523	1			T30	10		T39	6		T25	5
auto[1]	values[3]	values[7]	669	1			T35	11		T36	8		T39	19
auto[1]	values[4]	values[0]	353	1			T30	8		T36	9		T41	21
auto[1]	values[4]	values[1]	288	1			T25	9		T258	12		T255	11
auto[1]	values[4]	values[2]	422	1			T37	7		T209	22		T25	7
auto[1]	values[4]	values[3]	667	1			T30	8		T36	6		T202	12
auto[1]	values[4]	values[4]	465	1			T30	4		T50	8		T255	88
auto[1]	values[4]	values[5]	601	1			T35	8		T50	14		T187	6
auto[1]	values[4]	values[6]	264	1			T36	4		T23	6		T25	4
auto[1]	values[4]	values[7]	594	1			T37	10		T41	5		T154	18
auto[1]	values[5]	values[0]	241	1			T41	10		T257	5		T259	8
auto[1]	values[5]	values[1]	425	1			T35	6		T36	7		T41	17
auto[1]	values[5]	values[2]	499	1			T36	17		T37	20		T260	14
auto[1]	values[5]	values[3]	325	1			T36	9		T37	20		T39	10
auto[1]	values[5]	values[4]	421	1			T17	25		T23	19		T170	7
auto[1]	values[5]	values[5]	475	1			T35	15		T23	3		T209	22
auto[1]	values[5]	values[6]	497	1			T35	14		T39	25		T154	41
auto[1]	values[5]	values[7]	242	1			T36	6		T23	6		T261	7
auto[1]	values[6]	values[0]	218	1			T17	9		T36	9		T23	9
auto[1]	values[6]	values[1]	427	1			T4	9		T35	5		T39	44
auto[1]	values[6]	values[2]	459	1			T37	15		T154	14		T233	6
auto[1]	values[6]	values[3]	297	1			T30	9		T39	6		T192	12
auto[1]	values[6]	values[4]	487	1			T17	8		T41	7		T154	16
auto[1]	values[6]	values[5]	887	1			T35	7		T209	21		T25	8
auto[1]	values[6]	values[6]	471	1			T30	49		T36	13		T41	13
auto[1]	values[6]	values[7]	439	1			T30	7		T36	12		T37	12
auto[1]	values[7]	values[0]	556	1			T30	26		T154	10		T223	9
auto[1]	values[7]	values[1]	493	1			T37	11		T204	8		T187	28
auto[1]	values[7]	values[2]	477	1			T35	18		T252	10		T253	15
auto[1]	values[7]	values[3]	432	1			T30	7		T194	12		T41	20
auto[1]	values[7]	values[4]	573	1			T39	9		T23	28		T170	83
auto[1]	values[7]	values[5]	290	1			T35	13		T23	21		T262	6
auto[1]	values[7]	values[6]	455	1			T35	12		T37	8		T170	37
auto[1]	values[7]	values[7]	773	1			T30	5		T35	9		T255	5