Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	974	1			T8	4		T9	2		T10	4
auto[ReadAddrCrossIntoMailbox]	636	1			T17	2		T30	4		T35	2
auto[ReadAddrCrossOutOfMailbox]	710	1			T17	5		T171	2		T30	2
auto[ReadAddrCrossAllMailbox]	484	1			T17	1		T30	2		T35	3
auto[ReadAddrOutsideMailbox]	8453	1			T3	8		T4	2		T9	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5591

1

T3

4

T8

2

T9

6

auto[1]

5666

1

T3

4

T4

2

T8

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1815	1			T4	1		T89	2		T74	2
read_ops[0x0b]	1852	1			T3	4		T49	2		T17	4
read_ops[0x3b]	1928	1			T3	4		T4	1		T9	4
read_ops[0x6b]	1893	1			T8	4		T9	2		T10	4
read_ops[0xbb]	1873	1			T9	4		T22	2		T17	7
read_ops[0xeb]	1896	1			T9	2		T22	2		T34	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	65	1			T36	2		T219	2		T37	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	81	1			T30	1		T219	2		T208	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	58	1			T35	1		T36	2		T39	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T30	2		T36	2		T23	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	39	1			T17	1		T249	1		T23	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	56	1			T36	1		T249	1		T233	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	37	1			T35	1		T36	1		T263	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	45	1			T209	1		T223	2		T187	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	712	1			T89	1		T74	1		T17	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	683	1			T4	1		T89	1		T74	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	90	1			T219	4		T37	2		T41	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	78	1			T36	1		T219	4		T37	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	63	1			T36	1		T210	1		T23	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	53	1			T39	1		T210	1		T170	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	52	1			T154	2		T50	1		T192	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	47	1			T30	1		T37	4		T23	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	34	1			T39	1		T210	1		T23	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	38	1			T30	1		T36	1		T210	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	699	1			T3	2		T49	1		T17	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	698	1			T3	2		T49	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	77	1			T36	1		T241	2		T39	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	102	1			T30	2		T36	2		T241	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	54	1			T36	1		T37	2		T251	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	47	1			T209	2		T202	1		T251	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	72	1			T37	3		T39	1		T23	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	59	1			T17	1		T138	1		T39	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	39	1			T17	1		T37	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	48	1			T36	1		T37	1		T138	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	730	1			T3	2		T9	2		T88	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	700	1			T3	2		T4	1		T9	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	92	1			T8	2		T10	2		T30	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	78	1			T8	2		T10	2		T36	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	46	1			T17	2		T35	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	41	1			T209	2		T223	1		T261	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	65	1			T23	2		T209	1		T246	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	72	1			T36	1		T37	3		T41	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	38	1			T36	1		T138	1		T209	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	40	1			T41	1		T170	2		T154	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	681	1			T9	1		T74	1		T31	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	740	1			T9	1		T74	1		T31	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	63	1			T17	1		T171	2		T36	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	84	1			T171	2		T35	1		T36	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	59	1			T36	1		T37	1		T138	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	56	1			T249	1		T208	1		T170	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	66	1			T17	2		T171	1		T241	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	70	1			T171	1		T30	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	45	1			T249	2		T50	1		T209	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	42	1			T35	1		T249	2		T23	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	682	1			T9	2		T22	1		T17	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	706	1			T9	2		T22	1		T17	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	83	1			T9	1		T17	1		T30	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	81	1			T9	1		T36	2		T219	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	56	1			T30	2		T36	2		T210	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	64	1			T36	1		T37	2		T210	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	55	1			T17	1		T36	1		T210	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	57	1			T37	1		T41	1		T210	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	35	1			T30	1		T36	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	43	1			T35	1		T230	2		T249	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	704	1			T22	1		T34	3		T74	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	718	1			T22	1		T34	3		T74	2