Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14303500	1			T1	1006		T2	1		T3	1
all_pins[1]	14303500	1			T1	1006		T2	1		T3	1
all_pins[2]	14303500	1			T1	1006		T2	1		T3	1
all_pins[3]	14303500	1			T1	1006		T2	1		T3	1
all_pins[4]	14303500	1			T1	1006		T2	1		T3	1
all_pins[5]	14303500	1			T1	1006		T2	1		T3	1
all_pins[6]	14303500	1			T1	1006		T2	1		T3	1
all_pins[7]	14303500	1			T1	1006		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	114129034	1			T1	8048		T2	8		T3	8
values[0x1]	298966	1			T46	24		T62	6145		T63	22
transitions[0x0=>0x1]	288807	1			T46	17		T62	5158		T63	14
transitions[0x1=>0x0]	288825	1			T46	17		T62	5158		T63	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14299690	1			T1	1006		T2	1		T3	1
all_pins[0]	values[0x1]	3810	1			T46	2		T62	299		T63	4
all_pins[0]	transitions[0x0=>0x1]	2755	1			T46	2		T62	298		T63	2
all_pins[0]	transitions[0x1=>0x0]	743	1			T46	5		T63	2		T168	7
all_pins[1]	values[0x0]	14301702	1			T1	1006		T2	1		T3	1
all_pins[1]	values[0x1]	1798	1			T46	5		T62	1		T63	4
all_pins[1]	transitions[0x0=>0x1]	1500	1			T46	4		T62	1		T63	4
all_pins[1]	transitions[0x1=>0x0]	643	1			T46	1		T62	86		T63	1
all_pins[2]	values[0x0]	14302559	1			T1	1006		T2	1		T3	1
all_pins[2]	values[0x1]	941	1			T46	2		T62	86		T63	1
all_pins[2]	transitions[0x0=>0x1]	846	1			T46	1		T62	86		T63	1
all_pins[2]	transitions[0x1=>0x0]	268	1			T46	2		T62	1		T63	1
all_pins[3]	values[0x0]	14303137	1			T1	1006		T2	1		T3	1
all_pins[3]	values[0x1]	363	1			T46	3		T62	1		T63	1
all_pins[3]	transitions[0x0=>0x1]	268	1			T46	3		T62	1		T63	1
all_pins[3]	transitions[0x1=>0x0]	298	1			T46	2		T62	2		T63	2
all_pins[4]	values[0x0]	14303107	1			T1	1006		T2	1		T3	1
all_pins[4]	values[0x1]	393	1			T46	2		T62	2		T63	2
all_pins[4]	transitions[0x0=>0x1]	305	1			T46	2		T62	1		T63	2
all_pins[4]	transitions[0x1=>0x0]	13764	1			T46	3		T62	991		T63	1
all_pins[5]	values[0x0]	14289648	1			T1	1006		T2	1		T3	1
all_pins[5]	values[0x1]	13852	1			T46	3		T62	992		T63	1
all_pins[5]	transitions[0x0=>0x1]	5527	1			T46	2		T62	11		T168	2
all_pins[5]	transitions[0x1=>0x0]	269133	1			T46	3		T62	3777		T63	5
all_pins[6]	values[0x0]	14026042	1			T1	1006		T2	1		T3	1
all_pins[6]	values[0x1]	277458	1			T46	4		T62	4758		T63	6
all_pins[6]	transitions[0x0=>0x1]	277366	1			T46	1		T62	4756		T63	4
all_pins[6]	transitions[0x1=>0x0]	259	1			T62	4		T63	1		T168	4
all_pins[7]	values[0x0]	14303149	1			T1	1006		T2	1		T3	1
all_pins[7]	values[0x1]	351	1			T46	3		T62	6		T63	3
all_pins[7]	transitions[0x0=>0x1]	240	1			T46	2		T62	4		T168	4
all_pins[7]	transitions[0x1=>0x0]	3717	1			T46	1		T62	297		T63	1