Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	8567	1			T9	16		T29	30		T90	10
values[1]	9168	1			T49	14		T227	24		T88	14
values[2]	9087	1			T8	26		T17	20		T44	18
values[3]	9764	1			T4	35		T74	10		T17	34
values[4]	8909	1			T17	20		T33	8		T32	67
values[5]	10184	1			T3	32		T31	10		T17	40
values[6]	9472	1			T10	6		T22	104		T17	47
values[7]	7684	1			T12	4		T34	28		T89	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	9757	1			T17	41		T198	10		T30	20
values[1]	8654	1			T88	14		T17	54		T30	46
values[2]	10108	1			T8	26		T17	40		T32	67
values[3]	8772	1			T22	104		T89	4		T17	22
values[4]	8830	1			T3	32		T9	16		T49	14
values[5]	8478	1			T4	35		T17	27		T30	110
values[6]	9597	1			T10	6		T12	4		T227	24
values[7]	8639	1			T34	28		T74	10		T31	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71708

1

T3

32

T4

32

T8

26

auto[1]

1127

1

T4

3

T17

6

T29

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	1008	1			T248	4		T41	23		T23	39
auto[0]	values[0]	values[1]	979	1			T209	29		T223	32		T188	40
auto[0]	values[0]	values[2]	1322	1			T30	19		T23	34		T260	14
auto[0]	values[0]	values[3]	1214	1			T29	26		T203	12		T256	14
auto[0]	values[0]	values[4]	975	1			T9	16		T30	26		T36	20
auto[0]	values[0]	values[5]	1206	1			T37	46		T138	20		T23	36
auto[0]	values[0]	values[6]	900	1			T90	10		T25	20		T192	20
auto[0]	values[0]	values[7]	811	1			T170	20		T264	2		T199	4
auto[0]	values[1]	values[0]	1145	1			T17	21		T198	10		T30	20
auto[0]	values[1]	values[1]	1113	1			T88	14		T35	45		T195	30
auto[0]	values[1]	values[2]	837	1			T247	10		T265	8		T154	19
auto[0]	values[1]	values[3]	901	1			T17	21		T30	20		T157	40
auto[0]	values[1]	values[4]	801	1			T49	14		T30	21		T266	12
auto[0]	values[1]	values[5]	1250	1			T35	47		T138	28		T50	19
auto[0]	values[1]	values[6]	1701	1			T227	24		T35	20		T36	30
auto[0]	values[1]	values[7]	1283	1			T36	20		T39	20		T170	20
auto[0]	values[2]	values[0]	1034	1			T36	20		T39	46		T154	73
auto[0]	values[2]	values[1]	1241	1			T17	20		T36	20		T192	22
auto[0]	values[2]	values[2]	1102	1			T8	26		T39	20		T230	8
auto[0]	values[2]	values[3]	1225	1			T228	6		T241	10		T138	20
auto[0]	values[2]	values[4]	1184	1			T44	18		T30	56		T37	35
auto[0]	values[2]	values[5]	980	1			T224	24		T240	2		T39	20
auto[0]	values[2]	values[6]	1299	1			T35	19		T37	20		T39	89
auto[0]	values[2]	values[7]	879	1			T35	30		T36	40		T222	18
auto[0]	values[3]	values[0]	965	1			T255	20		T187	46		T221	20
auto[0]	values[3]	values[1]	1333	1			T17	34		T30	45		T238	10
auto[0]	values[3]	values[2]	1293	1			T37	40		T197	14		T157	23
auto[0]	values[3]	values[3]	1087	1			T219	20		T242	30		T41	27
auto[0]	values[3]	values[4]	1468	1			T118	4		T36	26		T23	20
auto[0]	values[3]	values[5]	1036	1			T4	32		T37	20		T39	20
auto[0]	values[3]	values[6]	1273	1			T30	20		T37	66		T50	20
auto[0]	values[3]	values[7]	1178	1			T74	10		T36	20		T138	22
auto[0]	values[4]	values[0]	1603	1			T36	27		T154	114		T209	19
auto[0]	values[4]	values[1]	919	1			T35	19		T36	24		T37	20
auto[0]	values[4]	values[2]	1613	1			T32	67		T37	20		T196	34
auto[0]	values[4]	values[3]	906	1			T39	20		T190	61		T209	20
auto[0]	values[4]	values[4]	1036	1			T17	18		T35	51		T23	33
auto[0]	values[4]	values[5]	782	1			T30	21		T36	25		T23	26
auto[0]	values[4]	values[6]	889	1			T33	8		T30	25		T249	16
auto[0]	values[4]	values[7]	1035	1			T35	20		T37	20		T138	20
auto[0]	values[5]	values[0]	1288	1			T17	18		T35	21		T37	37
auto[0]	values[5]	values[1]	807	1			T36	35		T210	16		T23	23
auto[0]	values[5]	values[2]	1494	1			T17	20		T169	10		T231	12
auto[0]	values[5]	values[3]	1015	1			T30	20		T36	48		T39	30
auto[0]	values[5]	values[4]	1432	1			T3	32		T30	20		T36	21
auto[0]	values[5]	values[5]	1454	1			T30	67		T37	24		T191	32
auto[0]	values[5]	values[6]	1043	1			T244	28		T23	23		T267	8
auto[0]	values[5]	values[7]	1511	1			T31	10		T35	20		T23	20
auto[0]	values[6]	values[0]	1446	1			T36	45		T37	28		T39	20
auto[0]	values[6]	values[1]	1131	1			T35	22		T36	20		T23	39
auto[0]	values[6]	values[2]	1268	1			T17	20		T30	23		T229	6
auto[0]	values[6]	values[3]	1326	1			T22	104		T35	20		T36	20
auto[0]	values[6]	values[4]	1116	1			T36	20		T37	22		T38	26
auto[0]	values[6]	values[5]	877	1			T17	26		T37	20		T25	20
auto[0]	values[6]	values[6]	1184	1			T10	6		T37	25		T41	24
auto[0]	values[6]	values[7]	962	1			T35	20		T36	20		T223	42
auto[0]	values[7]	values[0]	1110	1			T41	20		T23	20		T25	32
auto[0]	values[7]	values[1]	1007	1			T36	44		T37	19		T41	24
auto[0]	values[7]	values[2]	1028	1			T36	20		T239	8		T50	21
auto[0]	values[7]	values[3]	960	1			T89	4		T206	102		T41	20
auto[0]	values[7]	values[4]	687	1			T17	20		T35	17		T37	75
auto[0]	values[7]	values[5]	741	1			T30	20		T37	20		T268	39
auto[0]	values[7]	values[6]	1148	1			T12	4		T43	10		T39	20
auto[0]	values[7]	values[7]	867	1			T34	28		T17	20		T171	10
auto[1]	values[0]	values[0]	23	1			T23	1		T233	4		T187	1
auto[1]	values[0]	values[1]	21	1			T188	2		T269	4		T205	3
auto[1]	values[0]	values[2]	18	1			T30	1		T187	3		T252	2
auto[1]	values[0]	values[3]	19	1			T29	4		T256	2		T233	1
auto[1]	values[0]	values[4]	20	1			T270	1		T271	2		T272	1
auto[1]	values[0]	values[5]	25	1			T37	1		T23	1		T154	3
auto[1]	values[0]	values[6]	14	1			T273	3		T274	1		T275	2
auto[1]	values[0]	values[7]	12	1			T273	1		T276	1		T277	2
auto[1]	values[1]	values[0]	25	1			T41	2		T25	2		T258	2
auto[1]	values[1]	values[1]	14	1			T187	1		T257	2		T278	3
auto[1]	values[1]	values[2]	18	1			T154	1		T209	2		T270	3
auto[1]	values[1]	values[3]	18	1			T17	1		T30	1		T157	1
auto[1]	values[1]	values[4]	11	1			T25	2		T279	1		T52	1
auto[1]	values[1]	values[5]	22	1			T35	2		T138	1		T50	1
auto[1]	values[1]	values[6]	22	1			T154	1		T50	4		T255	2
auto[1]	values[1]	values[7]	7	1			T280	1		T281	1		T282	3
auto[1]	values[2]	values[0]	21	1			T154	1		T255	1		T200	1
auto[1]	values[2]	values[1]	23	1			T216	2		T283	4		T270	3
auto[1]	values[2]	values[2]	14	1			T252	1		T270	3		T279	2
auto[1]	values[2]	values[3]	25	1			T261	1		T187	1		T188	1
auto[1]	values[2]	values[4]	17	1			T37	2		T209	3		T187	2
auto[1]	values[2]	values[5]	17	1			T284	1		T285	6		T286	1
auto[1]	values[2]	values[6]	18	1			T35	1		T39	1		T287	1
auto[1]	values[2]	values[7]	8	1			T35	1		T36	1		T154	3
auto[1]	values[3]	values[0]	14	1			T187	2		T288	1		T289	2
auto[1]	values[3]	values[1]	9	1			T30	1		T187	1		T186	1
auto[1]	values[3]	values[2]	14	1			T253	1		T189	3		T52	2
auto[1]	values[3]	values[3]	13	1			T217	2		T288	2		T205	1
auto[1]	values[3]	values[4]	20	1			T286	1		T290	1		T291	1
auto[1]	values[3]	values[5]	12	1			T4	3		T292	1		T293	1
auto[1]	values[3]	values[6]	28	1			T37	4		T50	1		T216	1
auto[1]	values[3]	values[7]	21	1			T209	2		T255	1		T279	1
auto[1]	values[4]	values[0]	16	1			T209	1		T216	1		T294	3
auto[1]	values[4]	values[1]	21	1			T35	1		T41	4		T295	2
auto[1]	values[4]	values[2]	20	1			T154	2		T233	3		T296	3
auto[1]	values[4]	values[3]	8	1			T187	1		T216	1		T297	3
auto[1]	values[4]	values[4]	10	1			T17	2		T23	2		T170	1
auto[1]	values[4]	values[5]	16	1			T30	2		T36	2		T259	2
auto[1]	values[4]	values[6]	25	1			T200	1		T298	2		T299	2
auto[1]	values[4]	values[7]	10	1			T204	1		T52	1		T288	1
auto[1]	values[5]	values[0]	14	1			T17	2		T257	1		T279	1
auto[1]	values[5]	values[1]	11	1			T25	2		T279	1		T200	1
auto[1]	values[5]	values[2]	30	1			T35	1		T287	1		T217	1
auto[1]	values[5]	values[3]	19	1			T36	1		T209	3		T192	1
auto[1]	values[5]	values[4]	15	1			T187	2		T200	3		T276	1
auto[1]	values[5]	values[5]	25	1			T37	1		T209	2		T255	2
auto[1]	values[5]	values[6]	12	1			T290	1		T53	1		T300	2
auto[1]	values[5]	values[7]	14	1			T288	2		T274	2		T301	1
auto[1]	values[6]	values[0]	26	1			T36	2		T170	4		T253	1
auto[1]	values[6]	values[1]	10	1			T23	1		T187	1		T286	2
auto[1]	values[6]	values[2]	14	1			T55	2		T302	1		T303	1
auto[1]	values[6]	values[3]	26	1			T286	1		T292	1		T304	3
auto[1]	values[6]	values[4]	21	1			T38	8		T270	1		T159	1
auto[1]	values[6]	values[5]	17	1			T17	1		T25	1		T286	1
auto[1]	values[6]	values[6]	24	1			T37	1		T221	2		T305	2
auto[1]	values[6]	values[7]	24	1			T252	2		T189	3		T296	2
auto[1]	values[7]	values[0]	19	1			T25	2		T294	1		T53	2
auto[1]	values[7]	values[1]	15	1			T37	1		T205	3		T306	2
auto[1]	values[7]	values[2]	23	1			T307	8		T279	3		T308	2
auto[1]	values[7]	values[3]	10	1			T252	2		T309	1		T298	1
auto[1]	values[7]	values[4]	17	1			T35	3		T37	1		T154	3
auto[1]	values[7]	values[5]	18	1			T223	2		T310	1		T221	1
auto[1]	values[7]	values[6]	17	1			T270	1		T305	4		T296	4
auto[1]	values[7]	values[7]	17	1			T138	1		T40	2		T202	2