Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5060

1

T5

7

T7

11

T14

9

auto[1]

5099

1

T5

10

T7

11

T14

15

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5500

1

T5

17

T7

22

T14

19

auto[1]

4659

1

T14

5

T16

42

T18

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8069

1

T5

10

T7

15

T14

13

auto[1]

2090

1

T5

7

T7

7

T14

11

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	2088	1			T5	7		T7	8		T14	6
valid[1]	2018	1			T5	1		T7	5		T14	4
valid[2]	2090	1			T5	3		T7	3		T14	4
valid[3]	2012	1			T5	1		T7	4		T14	6
valid[4]	1951	1			T5	5		T7	2		T14	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	350	1			T7	4		T14	1		T15	2
auto[0]	auto[0]	valid[0]	auto[1]	482	1			T14	1		T16	6		T42	3
auto[0]	auto[0]	valid[1]	auto[0]	344	1			T7	2		T15	3		T17	2
auto[0]	auto[0]	valid[1]	auto[1]	478	1			T16	3		T18	1		T42	2
auto[0]	auto[0]	valid[2]	auto[0]	330	1			T5	1		T7	1		T15	1
auto[0]	auto[0]	valid[2]	auto[1]	463	1			T14	1		T16	5		T18	1
auto[0]	auto[0]	valid[3]	auto[0]	359	1			T7	1		T15	2		T17	1
auto[0]	auto[0]	valid[3]	auto[1]	459	1			T16	5		T46	1		T86	3
auto[0]	auto[0]	valid[4]	auto[0]	332	1			T5	1		T15	1		T17	1
auto[0]	auto[0]	valid[4]	auto[1]	436	1			T14	1		T16	4		T18	1
auto[0]	auto[1]	valid[0]	auto[0]	350	1			T5	4		T7	1		T17	1
auto[0]	auto[1]	valid[0]	auto[1]	478	1			T16	1		T42	1		T86	1
auto[0]	auto[1]	valid[1]	auto[0]	332	1			T7	1		T15	2		T17	1
auto[0]	auto[1]	valid[1]	auto[1]	438	1			T14	1		T16	7		T18	1
auto[0]	auto[1]	valid[2]	auto[0]	350	1			T5	1		T7	2		T14	1
auto[0]	auto[1]	valid[2]	auto[1]	509	1			T16	7		T42	1		T30	2
auto[0]	auto[1]	valid[3]	auto[0]	329	1			T5	1		T7	1		T14	4
auto[0]	auto[1]	valid[3]	auto[1]	458	1			T14	1		T16	3		T18	2
auto[0]	auto[1]	valid[4]	auto[0]	334	1			T5	2		T7	2		T14	2
auto[0]	auto[1]	valid[4]	auto[1]	458	1			T16	1		T323	3		T138	1
auto[1]	auto[0]	valid[0]	auto[0]	199	1			T5	2		T7	1		T14	2
auto[1]	auto[0]	valid[1]	auto[0]	197	1			T5	1		T7	1		T14	1
auto[1]	auto[0]	valid[2]	auto[0]	219	1			T14	1		T15	2		T320	2
auto[1]	auto[0]	valid[3]	auto[0]	222	1			T7	1		T17	1		T19	2
auto[1]	auto[0]	valid[4]	auto[0]	190	1			T5	2		T14	1		T19	1
auto[1]	auto[1]	valid[0]	auto[0]	229	1			T5	1		T7	2		T14	2
auto[1]	auto[1]	valid[1]	auto[0]	229	1			T7	1		T14	2		T18	1
auto[1]	auto[1]	valid[2]	auto[0]	219	1			T5	1		T14	1		T15	2
auto[1]	auto[1]	valid[3]	auto[0]	185	1			T7	1		T14	1		T46	1
auto[1]	auto[1]	valid[4]	auto[0]	201	1			T15	1		T17	1		T46	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal