Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138801

1

T5

680

T7

547

T14

371

auto[1]

48310

1

T14

79

T16

658

T18

52

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136599

1

T5

468

T7

374

T14

301

auto[1]

50512

1

T5

212

T7

173

T14

149

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	95911	1			T5	357		T7	281		T14	230
others[1]	15812	1			T5	52		T7	46		T14	39
others[2]	15904	1			T5	57		T7	48		T14	37
others[3]	18023	1			T5	65		T7	57		T14	40
interest[1]	10395	1			T5	30		T7	26		T14	31
interest[4]	62830	1			T5	235		T7	178		T14	161
interest[64]	31066	1			T5	119		T7	89		T14	73

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	45092	1			T5	252		T7	191		T14	119
auto[0]	auto[0]	others[1]	7498	1			T5	37		T7	31		T14	17
auto[0]	auto[0]	others[2]	7555	1			T5	41		T7	23		T14	18
auto[0]	auto[0]	others[3]	8589	1			T5	44		T7	41		T14	19
auto[0]	auto[0]	interest[1]	4896	1			T5	16		T7	17		T14	18
auto[0]	auto[0]	interest[4]	29387	1			T5	160		T7	121		T14	86
auto[0]	auto[0]	interest[64]	14659	1			T5	78		T7	71		T14	31
auto[0]	auto[1]	others[0]	25072	1			T14	41		T16	341		T18	27
auto[0]	auto[1]	others[1]	4017	1			T14	9		T16	54		T18	3
auto[0]	auto[1]	others[2]	4084	1			T14	5		T16	65		T18	5
auto[0]	auto[1]	others[3]	4653	1			T14	6		T16	49		T18	7
auto[0]	auto[1]	interest[1]	2623	1			T14	5		T16	44		T18	2
auto[0]	auto[1]	interest[4]	16646	1			T14	28		T16	216		T18	16
auto[0]	auto[1]	interest[64]	7861	1			T14	13		T16	105		T18	8
auto[1]	auto[0]	others[0]	25747	1			T5	105		T7	90		T14	70
auto[1]	auto[0]	others[1]	4297	1			T5	15		T7	15		T14	13
auto[1]	auto[0]	others[2]	4265	1			T5	16		T7	25		T14	14
auto[1]	auto[0]	others[3]	4781	1			T5	21		T7	16		T14	15
auto[1]	auto[0]	interest[1]	2876	1			T5	14		T7	9		T14	8
auto[1]	auto[0]	interest[4]	16797	1			T5	75		T7	57		T14	47
auto[1]	auto[0]	interest[64]	8546	1			T5	41		T7	18		T14	29

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal