Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1686	1			T46	14		T62	15		T63	10
all_values[1]	1686	1			T46	14		T62	15		T63	10
all_values[2]	1686	1			T46	14		T62	15		T63	10
all_values[3]	1686	1			T46	14		T62	15		T63	10
all_values[4]	1686	1			T46	14		T62	15		T63	10
all_values[5]	1686	1			T46	14		T62	15		T63	10
all_values[6]	1686	1			T46	14		T62	15		T63	10
all_values[7]	1686	1			T46	14		T62	15		T63	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7258

1

T46

55

T62

69

T63

41

auto[1]

6230

1

T46

57

T62

51

T63

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5472

1

T46

53

T62

62

T63

27

auto[1]

8016

1

T46

59

T62

58

T63

53

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7737

1

T46

72

T62

76

T63

49

auto[1]

5751

1

T46

40

T62

44

T63

31

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	322	1			T46	8		T62	3		T63	1
all_values[0]	auto[0]	auto[0]	auto[1]	165	1			T62	2		T168	4		T23	3
all_values[0]	auto[0]	auto[1]	auto[0]	249	1			T46	1		T62	3		T168	3
all_values[0]	auto[0]	auto[1]	auto[1]	180	1			T62	1		T63	2		T168	2
all_values[0]	auto[1]	auto[0]	auto[1]	410	1			T46	4		T62	5		T63	6
all_values[0]	auto[1]	auto[1]	auto[1]	360	1			T46	1		T62	1		T63	1
all_values[1]	auto[0]	auto[0]	auto[0]	329	1			T46	2		T62	8		T63	2
all_values[1]	auto[0]	auto[0]	auto[1]	163	1			T46	2		T168	2		T23	2
all_values[1]	auto[0]	auto[1]	auto[0]	337	1			T46	2		T62	3		T63	1
all_values[1]	auto[0]	auto[1]	auto[1]	160	1			T46	4		T63	3		T168	6
all_values[1]	auto[1]	auto[0]	auto[1]	382	1			T46	3		T62	3		T168	4
all_values[1]	auto[1]	auto[1]	auto[1]	315	1			T46	1		T62	1		T63	4
all_values[2]	auto[0]	auto[0]	auto[0]	351	1			T46	2		T62	2		T63	2
all_values[2]	auto[0]	auto[0]	auto[1]	156	1			T46	1		T62	1		T63	5
all_values[2]	auto[0]	auto[1]	auto[0]	283	1			T46	3		T62	5		T168	6
all_values[2]	auto[0]	auto[1]	auto[1]	171	1			T46	3		T62	2		T168	3
all_values[2]	auto[1]	auto[0]	auto[1]	423	1			T46	3		T62	2		T63	3
all_values[2]	auto[1]	auto[1]	auto[1]	302	1			T46	2		T62	3		T168	5
all_values[3]	auto[0]	auto[0]	auto[0]	387	1			T46	4		T62	10		T63	1
all_values[3]	auto[0]	auto[0]	auto[1]	171	1			T46	1		T62	1		T63	2
all_values[3]	auto[0]	auto[1]	auto[0]	273	1			T46	2		T63	4		T168	7
all_values[3]	auto[0]	auto[1]	auto[1]	139	1			T63	1		T168	3		T41	2
all_values[3]	auto[1]	auto[0]	auto[1]	397	1			T46	4		T62	4		T63	1
all_values[3]	auto[1]	auto[1]	auto[1]	319	1			T46	3		T63	1		T168	5
all_values[4]	auto[0]	auto[0]	auto[0]	346	1			T46	2		T62	4		T63	3
all_values[4]	auto[0]	auto[0]	auto[1]	166	1			T62	1		T168	2		T23	1
all_values[4]	auto[0]	auto[1]	auto[0]	301	1			T46	9		T62	4		T63	2
all_values[4]	auto[0]	auto[1]	auto[1]	166	1			T46	1		T62	1		T63	2
all_values[4]	auto[1]	auto[0]	auto[1]	368	1			T46	1		T62	2		T63	1
all_values[4]	auto[1]	auto[1]	auto[1]	339	1			T46	1		T62	3		T63	2
all_values[5]	auto[0]	auto[0]	auto[0]	536	1			T46	4		T62	3		T63	3
all_values[5]	auto[0]	auto[1]	auto[0]	446	1			T46	6		T62	3		T63	2
all_values[5]	auto[1]	auto[0]	auto[1]	386	1			T46	1		T62	5		T63	2
all_values[5]	auto[1]	auto[1]	auto[1]	318	1			T46	3		T62	4		T63	3
all_values[6]	auto[0]	auto[0]	auto[0]	320	1			T46	1		T62	5		T63	1
all_values[6]	auto[0]	auto[0]	auto[1]	157	1			T168	2		T41	1		T23	1
all_values[6]	auto[0]	auto[1]	auto[0]	351	1			T46	4		T62	4		T63	1
all_values[6]	auto[0]	auto[1]	auto[1]	167	1			T46	3		T62	1		T63	4
all_values[6]	auto[1]	auto[0]	auto[1]	403	1			T46	4		T62	2		T63	3
all_values[6]	auto[1]	auto[1]	auto[1]	288	1			T46	2		T62	3		T63	1
all_values[7]	auto[0]	auto[0]	auto[0]	346	1			T46	2		T62	3		T63	1
all_values[7]	auto[0]	auto[0]	auto[1]	166	1			T46	2		T62	1		T63	2
all_values[7]	auto[0]	auto[1]	auto[0]	295	1			T46	1		T62	2		T63	3
all_values[7]	auto[0]	auto[1]	auto[1]	138	1			T46	2		T62	3		T63	1
all_values[7]	auto[1]	auto[0]	auto[1]	408	1			T46	4		T62	2		T63	2
all_values[7]	auto[1]	auto[1]	auto[1]	333	1			T46	3		T62	4		T63	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal