Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7074732	1			T20	2662		T21	1		T22	351
all_values[1]	7074732	1			T20	2662		T21	1		T22	351
all_values[2]	7074732	1			T20	2662		T21	1		T22	351
all_values[3]	7074732	1			T20	2662		T21	1		T22	351
all_values[4]	7074732	1			T20	2662		T21	1		T22	351
all_values[5]	7074732	1			T20	2662		T21	1		T22	351
all_values[6]	7074732	1			T20	2662		T21	1		T22	351
all_values[7]	7074732	1			T20	2662		T21	1		T22	351

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53908220

1

T20

21296

T21

8

T22

2808

auto[1]

2689636

1

T28

111

T1

47

T2

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56526549

1

T20

21221

T21

8

T22

2808

auto[1]

71307

1

T20

75

T28

108

T30

619

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6442929	1			T20	2617		T21	1		T22	351
all_values[0]	auto[0]	auto[1]	39555	1			T20	45		T28	6		T30	377
all_values[0]	auto[1]	auto[0]	589680	1			T28	7		T1	6		T2	1
all_values[0]	auto[1]	auto[1]	2568	1			T28	7		T1	3		T56	5
all_values[1]	auto[0]	auto[0]	6858882	1			T20	2647		T21	1		T22	351
all_values[1]	auto[0]	auto[1]	20123	1			T20	15		T28	12		T30	168
all_values[1]	auto[1]	auto[0]	195198	1			T28	5		T1	8		T2	1
all_values[1]	auto[1]	auto[1]	529	1			T28	5		T1	3		T2	3
all_values[2]	auto[0]	auto[0]	6700032	1			T20	2647		T21	1		T22	351
all_values[2]	auto[0]	auto[1]	7121	1			T20	15		T28	7		T30	74
all_values[2]	auto[1]	auto[0]	367342	1			T28	11		T56	3		T65	3
all_values[2]	auto[1]	auto[1]	237	1			T28	4		T1	1		T2	1
all_values[3]	auto[0]	auto[0]	6886498	1			T20	2662		T21	1		T22	351
all_values[3]	auto[0]	auto[1]	93	1			T28	4		T1	1		T2	4
all_values[3]	auto[1]	auto[0]	188051	1			T28	7		T1	9		T56	2
all_values[3]	auto[1]	auto[1]	90	1			T28	11		T56	5		T3	2
all_values[4]	auto[0]	auto[0]	6629720	1			T20	2662		T21	1		T22	351
all_values[4]	auto[0]	auto[1]	109	1			T28	6		T1	3		T111	1
all_values[4]	auto[1]	auto[0]	444804	1			T28	8		T56	4		T65	4
all_values[4]	auto[1]	auto[1]	99	1			T28	5		T1	1		T56	4
all_values[5]	auto[0]	auto[0]	6630977	1			T20	2662		T21	1		T22	351
all_values[5]	auto[0]	auto[1]	276	1			T28	3		T1	3		T11	2
all_values[5]	auto[1]	auto[0]	443370	1			T28	7		T1	2		T56	5
all_values[5]	auto[1]	auto[1]	109	1			T28	10		T1	1		T56	1
all_values[6]	auto[0]	auto[0]	6802093	1			T20	2662		T21	1		T22	351
all_values[6]	auto[0]	auto[1]	90	1			T28	8		T56	1		T65	1
all_values[6]	auto[1]	auto[0]	272448	1			T28	4		T1	8		T2	1
all_values[6]	auto[1]	auto[1]	101	1			T28	4		T1	2		T2	3
all_values[7]	auto[0]	auto[0]	6889619	1			T20	2662		T21	1		T22	351
all_values[7]	auto[0]	auto[1]	103	1			T28	7		T1	1		T2	1
all_values[7]	auto[1]	auto[0]	184906	1			T28	7		T2	1		T56	5
all_values[7]	auto[1]	auto[1]	104	1			T28	9		T1	3		T2	3