Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	38435	1			T20	66		T22	12		T23	2
auto[SpiFlashAddrCfg]	8789	1			T20	29		T21	4		T23	10
auto[SpiFlashAddr3b]	10710	1			T20	35		T24	10		T30	85
auto[SpiFlashAddr4b]	8880	1			T20	23		T21	4		T22	14

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38241

1

T20

79

T22

26

T27

8

auto[1]

28573

1

T20

74

T21

8

T23

16

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35858

1

T20

101

T21

4

T22

18

auto[1]

30956

1

T20

52

T21

4

T22

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	43994	1			T20	84		T21	4		T22	12
values[1]	1299	1			T20	6		T22	8		T30	6
values[2]	1670	1			T20	10		T23	2		T24	4
values[3]	1663	1			T20	7		T23	2		T30	10
values[4]	1733	1			T20	5		T23	2		T30	12
values[5]	1704	1			T20	8		T30	19		T34	7
values[6]	1617	1			T21	2		T22	4		T23	4
values[7]	1749	1			T20	1		T23	4		T30	18
values[8]	11385	1			T20	32		T21	2		T22	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33037

1

T21

8

T22

26

T23

16

auto[1]

33777

1

T20

153

T30

419

T53

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

64295

1

T20

150

T21

4

T22

26

write

2519

1

T20

3

T21

4

T30

27

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

23056

1

T20

71

T21

2

T22

6

valids[0x1]

43758

1

T20

82

T21

6

T22

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1894	1			T20	7		T22	2		T30	18
internal_process_ops[0x5a]	1825	1			T20	5		T30	11		T32	2
internal_process_ops[0x05]	22299	1			T20	17		T22	4		T24	2
internal_process_ops[0x35]	1866	1			T20	5		T23	2		T30	12
internal_process_ops[0x15]	1843	1			T20	3		T22	2		T24	4
internal_process_ops[0x03]	1236	1			T22	2		T30	4		T34	6
internal_process_ops[0x0b]	1241	1			T22	2		T23	2		T30	4
internal_process_ops[0x3b]	1302	1			T20	1		T22	2		T23	4
internal_process_ops[0x6b]	1334	1			T20	2		T23	2		T30	4
internal_process_ops[0xbb]	1302	1			T20	1		T24	4		T30	6
internal_process_ops[0xeb]	1144	1			T30	4		T32	2		T53	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65580

1

T20

152

T21

4

T22

26

auto[1]

1234

1

T20

1

T21

4

T30

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64470

1

T20

150

T21

8

T22

26

auto[1]

2344

1

T20

3

T30

21

T34

18

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11016

1

T22

12

T27

4

T34

26

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6392

1

T23

2

T24

6

T34

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2506

1

T27

2

T32

2

T34

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2044

1

T21

4

T23

10

T24

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2934

1

T32

2

T34

7

T99

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2465

1

T24

10

T34

14

T44

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2353

1

T22

14

T27

2

T32

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2106

1

T23

4

T24

6

T29

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

107

1

T15

2

T45

1

T3

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

77

1

T34

2

T43

1

T45

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

83

1

T43

1

T115

1

T116

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

89

1

T34

2

T44

2

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

80

1

T98

2

T15

2

T47

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

63

1

T43

4

T103

3

T117

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

80

1

T43

1

T70

1

T115

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

83

1

T43

1

T48

4

T45

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

77

1

T34

1

T3

3

T118

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

75

1

T45

1

T3

1

T103

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

48

1

T119

2

T120

1

T5

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

74

1

T3

1

T103

1

T116

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T43

1

T115

2

T121

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

68

1

T47

1

T3

1

T103

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

63

1

T43

1

T3

3

T106

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

59

1

T21

4

T46

2

T43

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11691

1

T20

40

T30

137

T34

59

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8656

1

T20

26

T30

66

T34

57

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1883

1

T20

15

T30

29

T53

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1706

1

T20

12

T30

34

T34

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2513

1

T20

14

T30

34

T53

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2215

1

T20

20

T30

42

T34

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2025

1

T20

10

T30

28

T34

27

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1790

1

T20

13

T30

22

T34

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

91

1

T30

2

T73

1

T56

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T30

3

T34

4

T73

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

69

1

T34

1

T2

1

T73

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

77

1

T73

3

T56

2

T122

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

65

1

T30

2

T2

2

T73

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

103

1

T34

1

T65

2

T122

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

90

1

T20

2

T34

3

T73

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T30

1

T34

2

T2

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T30

5

T34

4

T73

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

63

1

T73

1

T65

3

T123

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

84

1

T30

3

T34

1

T2

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

74

1

T20

1

T30

1

T73

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

102

1

T30

6

T2

1

T73

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

79

1

T30

1

T73

3

T56

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

63

1

T2

2

T73

2

T75

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

77

1

T30

3

T2

2

T56

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4737	1			T22	4		T27	2		T34	23
auto[0]	values[0]	valids[0x1]	15886	1			T21	4		T22	8		T23	2
auto[0]	values[1]	valids[0x1]	658	1			T22	8		T34	2		T43	5
auto[0]	values[2]	valids[0x0]	596	1			T23	2		T24	4		T34	8
auto[0]	values[2]	valids[0x1]	343	1			T34	1		T56	1		T50	1
auto[0]	values[3]	valids[0x0]	558	1			T34	1		T43	5		T50	1
auto[0]	values[3]	valids[0x1]	337	1			T23	2		T34	1		T43	4
auto[0]	values[4]	valids[0x0]	640	1			T34	2		T46	8		T43	7
auto[0]	values[4]	valids[0x1]	314	1			T23	2		T34	1		T99	2
auto[0]	values[5]	valids[0x0]	613	1			T34	1		T99	2		T44	2
auto[0]	values[5]	valids[0x1]	335	1			T43	6		T98	6		T2	1
auto[0]	values[6]	valids[0x0]	592	1			T21	2		T23	4		T29	2
auto[0]	values[6]	valids[0x1]	308	1			T22	4		T24	10		T50	2
auto[0]	values[7]	valids[0x0]	631	1			T32	2		T34	3		T44	6
auto[0]	values[7]	valids[0x1]	302	1			T23	4		T34	1		T43	4
auto[0]	values[8]	valids[0x0]	4006	1			T22	2		T24	8		T34	23
auto[0]	values[8]	valids[0x1]	2181	1			T21	2		T24	2		T27	2
auto[1]	values[0]	valids[0x0]	4818	1			T20	33		T30	83		T34	51
auto[1]	values[0]	valids[0x1]	18553	1			T20	51		T30	177		T34	94
auto[1]	values[1]	valids[0x1]	641	1			T20	6		T30	6		T34	6
auto[1]	values[2]	valids[0x0]	449	1			T20	10		T30	7		T34	4
auto[1]	values[2]	valids[0x1]	282	1			T30	9		T34	1		T100	5
auto[1]	values[3]	valids[0x0]	498	1			T20	6		T30	6		T34	7
auto[1]	values[3]	valids[0x1]	270	1			T20	1		T30	4		T34	2
auto[1]	values[4]	valids[0x0]	457	1			T20	3		T30	1		T34	3
auto[1]	values[4]	valids[0x1]	322	1			T20	2		T30	11		T34	3
auto[1]	values[5]	valids[0x0]	448	1			T20	6		T30	12		T34	5
auto[1]	values[5]	valids[0x1]	308	1			T20	2		T30	7		T34	1
auto[1]	values[6]	valids[0x0]	432	1			T30	5		T53	5		T34	5
auto[1]	values[6]	valids[0x1]	285	1			T30	5		T53	4		T34	2
auto[1]	values[7]	valids[0x0]	521	1			T20	1		T30	11		T34	4
auto[1]	values[7]	valids[0x1]	295	1			T30	7		T2	3		T73	6
auto[1]	values[8]	valids[0x0]	3060	1			T20	12		T30	41		T53	2
auto[1]	values[8]	valids[0x1]	2138	1			T20	20		T30	27		T34	15