Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18900

1

T20

46

T21

1

T22

7

auto[1]

22553

1

T20

16

T30

79

T34

54

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15773

1

T20

37

T21

1

T22

1

auto[1]

25680

1

T20

25

T22

6

T27

2

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	6172	1			T20	24		T21	1		T22	7
auto[524288:1048575]	4899	1			T20	5		T30	55		T96	2
auto[1048576:1572863]	5482	1			T20	5		T30	10		T34	44
auto[1572864:2097151]	4926	1			T20	12		T30	32		T96	1
auto[2097152:2621439]	4659	1			T20	6		T30	16		T34	16
auto[2621440:3145727]	5358	1			T20	1		T30	13		T34	18
auto[3145728:3670015]	5296	1			T30	34		T53	1		T34	28
auto[3670016:4194303]	4661	1			T20	9		T30	44		T53	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40593

1

T20

62

T21

1

T22

7

auto[1]

860

1

T30

1

T34

1

T43

14

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33119

1

T20

47

T21

1

T22

7

auto[1]

8334

1

T20

15

T30

84

T34

35

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1906	1			T20	9		T21	1		T22	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	746	1			T20	2		T22	6		T27	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1256	1			T20	3		T30	8		T96	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	516	1			T30	3		T34	2		T43	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1238	1			T20	2		T30	4		T34	19
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	501	1			T20	1		T30	3		T34	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1323	1			T20	4		T30	12		T96	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	551	1			T20	2		T30	8		T34	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1290	1			T20	4		T30	4		T34	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	514	1			T30	2		T34	3		T43	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1317	1			T30	4		T34	4		T43	12
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	514	1			T20	1		T30	2		T43	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1325	1			T30	12		T53	1		T34	10
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	511	1			T30	6		T34	6		T43	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1198	1			T20	2		T30	6		T53	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	465	1			T20	1		T30	3		T34	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	330	1			T20	5		T30	3		T2	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	141	1			T20	1		T30	1		T73	5
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	323	1			T20	1		T30	11		T34	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	139	1			T20	1		T30	8		T34	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	319	1			T20	1		T30	2		T34	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	132	1			T20	1		T30	1		T34	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	295	1			T20	1		T30	2		T34	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	142	1			T20	2		T30	1		T2	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	321	1			T20	2		T30	2		T34	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	134	1			T30	3		T34	2		T56	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	338	1			T30	4		T34	7		T43	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	164	1			T30	1		T34	2		T73	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	353	1			T30	3		T34	1		T2	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	172	1			T30	1		T122	6		T115	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	296	1			T30	10		T2	1		T73	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	130	1			T30	1		T73	3		T65	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	299	1			T20	1		T34	2		T43	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2318	1			T20	6		T34	3		T43	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	226	1			T30	2		T34	3		T73	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1825	1			T30	2		T34	6		T73	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	229	1			T34	4		T2	5		T73	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2399	1			T34	11		T2	8		T73	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	227	1			T20	1		T30	2		T34	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1940	1			T20	2		T30	7		T34	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	211	1			T43	1		T74	1		T50	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1738	1			T43	10		T74	5		T50	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	221	1			T30	1		T34	1		T43	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2023	1			T30	1		T34	2		T43	16
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	259	1			T30	5		T34	3		T43	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1997	1			T30	7		T34	5		T43	19
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	192	1			T20	1		T30	1		T43	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1844	1			T20	5		T30	21		T43	24
auto[1]	auto[1]	auto[0:524287]	auto[0]	59	1			T30	1		T73	2		T65	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	373	1			T30	1		T73	7		T65	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	76	1			T30	6		T73	1		T47	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	538	1			T30	15		T73	9		T47	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	55	1			T34	1		T43	2		T3	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	609	1			T34	1		T43	23		T3	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	56	1			T2	1		T73	1		T56	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	392	1			T2	1		T73	2		T56	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	49	1			T30	2		T56	2		T3	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	402	1			T30	3		T56	3		T3	19
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	70	1			T34	1		T43	1		T73	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	711	1			T34	1		T43	5		T73	21
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	56	1			T34	1		T2	2		T122	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	623	1			T34	2		T2	2		T122	79
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	60	1			T30	1		T65	4		T3	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	476	1			T30	1		T65	85		T3	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	14823	1			T20	31		T21	1		T22	7
auto[0]	auto[0]	auto[1]	348	1			T43	4		T73	3		T74	1
auto[0]	auto[1]	auto[0]	3644	1			T20	15		T30	54		T34	28
auto[0]	auto[1]	auto[1]	85	1			T43	3		T65	2		T122	3
auto[1]	auto[0]	auto[0]	17603	1			T20	16		T30	48		T34	46
auto[1]	auto[0]	auto[1]	345	1			T30	1		T34	1		T43	5
auto[1]	auto[1]	auto[0]	4523	1			T30	30		T34	7		T43	29
auto[1]	auto[1]	auto[1]	82	1			T43	2		T122	2		T45	1