Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19451

1

T22

26

T27

8

T32

6

auto[1]

13586

1

T21

8

T23

16

T24

30

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3759	1			T24	30		T29	2		T43	22
values[1]	4107	1			T43	136		T12	8		T50	22
values[2]	5020	1			T32	6		T34	21		T43	20
values[3]	4042	1			T21	8		T34	24		T43	78
values[4]	3143	1			T22	26		T43	69		T15	14
values[5]	4414	1			T34	42		T46	18		T43	25
values[6]	4109	1			T23	16		T34	20		T99	12
values[7]	4443	1			T27	8		T44	24		T18	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4136	1			T29	2		T43	56		T15	14
values[1]	4975	1			T21	8		T43	20		T18	2
values[2]	3705	1			T34	41		T46	18		T43	25
values[3]	3525	1			T22	26		T34	20		T43	85
values[4]	4232	1			T23	16		T34	22		T43	20
values[5]	3957	1			T24	30		T32	6		T99	12
values[6]	4116	1			T27	8		T43	77		T48	20
values[7]	4391	1			T34	24		T43	43		T16	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	222	1			T50	6		T116	9		T5	12
auto[0]	values[0]	values[1]	420	1			T45	17		T116	9		T106	115
auto[0]	values[0]	values[2]	206	1			T77	16		T171	6		T172	16
auto[0]	values[0]	values[3]	270	1			T43	12		T47	18		T173	12
auto[0]	values[0]	values[4]	244	1			T117	57		T107	16		T147	12
auto[0]	values[0]	values[5]	216	1			T116	20		T119	12		T106	9
auto[0]	values[0]	values[6]	207	1			T56	14		T147	13		T174	12
auto[0]	values[0]	values[7]	334	1			T3	28		T103	23		T89	10
auto[0]	values[1]	values[0]	392	1			T43	48		T116	78		T106	11
auto[0]	values[1]	values[1]	351	1			T3	60		T155	12		T106	29
auto[0]	values[1]	values[2]	332	1			T47	16		T3	21		T175	6
auto[0]	values[1]	values[3]	233	1			T176	16		T125	43		T119	12
auto[0]	values[1]	values[4]	187	1			T12	8		T120	30		T107	22
auto[0]	values[1]	values[5]	263	1			T43	38		T163	8		T116	17
auto[0]	values[1]	values[6]	486	1			T43	10		T177	12		T3	50
auto[0]	values[1]	values[7]	271	1			T50	7		T3	13		T87	17
auto[0]	values[2]	values[0]	301	1			T131	12		T3	16		T119	11
auto[0]	values[2]	values[1]	486	1			T2	16		T47	20		T3	21
auto[0]	values[2]	values[2]	286	1			T34	15		T103	10		T169	8
auto[0]	values[2]	values[3]	260	1			T119	12		T106	21		T89	9
auto[0]	values[2]	values[4]	414	1			T43	10		T3	10		T178	10
auto[0]	values[2]	values[5]	349	1			T32	6		T3	20		T153	103
auto[0]	values[2]	values[6]	312	1			T115	11		T103	18		T117	11
auto[0]	values[2]	values[7]	527	1			T3	10		T107	13		T5	58
auto[0]	values[3]	values[0]	351	1			T116	12		T179	22		T107	16
auto[0]	values[3]	values[1]	367	1			T43	14		T116	10		T5	26
auto[0]	values[3]	values[2]	135	1			T180	2		T3	12		T121	6
auto[0]	values[3]	values[3]	206	1			T43	28		T45	8		T181	2
auto[0]	values[3]	values[4]	240	1			T145	12		T3	9		T103	14
auto[0]	values[3]	values[5]	318	1			T45	11		T103	11		T119	14
auto[0]	values[3]	values[6]	238	1			T43	13		T45	43		T3	11
auto[0]	values[3]	values[7]	374	1			T34	10		T116	82		T120	10
auto[0]	values[4]	values[0]	299	1			T15	14		T155	10		T107	27
auto[0]	values[4]	values[1]	98	1			T70	8		T117	15		T124	11
auto[0]	values[4]	values[2]	225	1			T156	7		T89	13		T107	16
auto[0]	values[4]	values[3]	162	1			T22	26		T43	9		T87	8
auto[0]	values[4]	values[4]	378	1			T116	61		T182	2		T5	26
auto[0]	values[4]	values[5]	221	1			T43	14		T183	2		T184	10
auto[0]	values[4]	values[6]	245	1			T43	14		T185	10		T47	26
auto[0]	values[4]	values[7]	386	1			T186	8		T146	11		T120	15
auto[0]	values[5]	values[0]	333	1			T187	14		T119	13		T135	21
auto[0]	values[5]	values[1]	460	1			T86	4		T120	79		T107	4
auto[0]	values[5]	values[2]	245	1			T34	11		T43	13		T118	37
auto[0]	values[5]	values[3]	196	1			T106	25		T124	11		T135	11
auto[0]	values[5]	values[4]	345	1			T34	13		T97	22		T3	16
auto[0]	values[5]	values[5]	250	1			T45	11		T3	14		T106	12
auto[0]	values[5]	values[6]	504	1			T71	14		T3	11		T107	12
auto[0]	values[5]	values[7]	189	1			T159	14		T188	12		T172	38
auto[0]	values[6]	values[0]	242	1			T115	10		T120	9		T107	20
auto[0]	values[6]	values[1]	425	1			T3	12		T105	14		T134	10
auto[0]	values[6]	values[2]	321	1			T2	16		T189	26		T116	13
auto[0]	values[6]	values[3]	306	1			T34	9		T98	26		T3	15
auto[0]	values[6]	values[4]	378	1			T107	10		T5	30		T140	28
auto[0]	values[6]	values[5]	264	1			T99	12		T45	5		T161	8
auto[0]	values[6]	values[6]	217	1			T164	24		T103	17		T190	12
auto[0]	values[6]	values[7]	274	1			T43	32		T47	16		T45	21
auto[0]	values[7]	values[0]	338	1			T191	4		T192	32		T193	9
auto[0]	values[7]	values[1]	256	1			T18	2		T103	11		T117	12
auto[0]	values[7]	values[2]	334	1			T102	22		T194	6		T45	52
auto[0]	values[7]	values[3]	405	1			T45	17		T3	12		T119	27
auto[0]	values[7]	values[4]	378	1			T195	4		T196	73		T5	23
auto[0]	values[7]	values[5]	445	1			T45	13		T103	22		T5	29
auto[0]	values[7]	values[6]	314	1			T27	8		T141	4		T155	24
auto[0]	values[7]	values[7]	220	1			T120	18		T5	9		T135	5
auto[1]	values[0]	values[0]	177	1			T29	2		T50	14		T116	11
auto[1]	values[0]	values[1]	266	1			T45	17		T116	11		T106	2
auto[1]	values[0]	values[2]	92	1			T77	7		T172	4		T197	15
auto[1]	values[0]	values[3]	230	1			T43	10		T47	10		T155	15
auto[1]	values[0]	values[4]	206	1			T117	33		T107	5		T147	8
auto[1]	values[0]	values[5]	240	1			T24	30		T116	20		T119	8
auto[1]	values[0]	values[6]	133	1			T48	20		T56	6		T147	12
auto[1]	values[0]	values[7]	296	1			T16	20		T3	16		T103	3
auto[1]	values[1]	values[0]	210	1			T43	8		T116	11		T106	10
auto[1]	values[1]	values[1]	201	1			T3	21		T155	13		T106	16
auto[1]	values[1]	values[2]	199	1			T47	4		T3	30		T116	6
auto[1]	values[1]	values[3]	164	1			T119	42		T130	9		T172	8
auto[1]	values[1]	values[4]	150	1			T120	5		T107	5		T135	27
auto[1]	values[1]	values[5]	192	1			T43	9		T116	6		T5	16
auto[1]	values[1]	values[6]	248	1			T43	23		T3	33		T116	9
auto[1]	values[1]	values[7]	228	1			T50	15		T3	51		T87	4
auto[1]	values[2]	values[0]	221	1			T3	9		T119	9		T106	11
auto[1]	values[2]	values[1]	356	1			T2	7		T47	7		T3	32
auto[1]	values[2]	values[2]	253	1			T34	6		T103	12		T155	11
auto[1]	values[2]	values[3]	282	1			T119	11		T106	8		T89	16
auto[1]	values[2]	values[4]	361	1			T43	10		T3	19		T116	77
auto[1]	values[2]	values[5]	112	1			T3	12		T153	11		T147	7
auto[1]	values[2]	values[6]	252	1			T115	69		T103	2		T117	9
auto[1]	values[2]	values[7]	248	1			T3	32		T107	7		T5	8
auto[1]	values[3]	values[0]	255	1			T116	21		T107	5		T5	12
auto[1]	values[3]	values[1]	294	1			T21	8		T43	6		T116	10
auto[1]	values[3]	values[2]	202	1			T3	8		T198	2		T199	8
auto[1]	values[3]	values[3]	139	1			T43	6		T45	15		T89	13
auto[1]	values[3]	values[4]	153	1			T3	15		T103	6		T106	6
auto[1]	values[3]	values[5]	239	1			T45	9		T103	12		T119	8
auto[1]	values[3]	values[6]	248	1			T43	11		T45	7		T3	30
auto[1]	values[3]	values[7]	283	1			T34	14		T116	10		T120	63
auto[1]	values[4]	values[0]	121	1			T155	10		T107	28		T5	10
auto[1]	values[4]	values[1]	176	1			T70	12		T117	8		T124	9
auto[1]	values[4]	values[2]	116	1			T156	13		T89	7		T107	6
auto[1]	values[4]	values[3]	71	1			T43	20		T87	12		T5	9
auto[1]	values[4]	values[4]	110	1			T116	5		T200	12		T5	10
auto[1]	values[4]	values[5]	205	1			T43	6		T49	10		T153	11
auto[1]	values[4]	values[6]	133	1			T43	6		T47	9		T38	7
auto[1]	values[4]	values[7]	197	1			T146	17		T120	5		T107	10
auto[1]	values[5]	values[0]	241	1			T119	8		T135	9		T201	7
auto[1]	values[5]	values[1]	278	1			T120	30		T107	19		T124	7
auto[1]	values[5]	values[2]	236	1			T34	9		T46	18		T43	12
auto[1]	values[5]	values[3]	160	1			T106	8		T124	9		T202	6
auto[1]	values[5]	values[4]	303	1			T34	9		T3	4		T119	32
auto[1]	values[5]	values[5]	155	1			T45	9		T3	7		T106	51
auto[1]	values[5]	values[6]	331	1			T3	41		T107	8		T5	12
auto[1]	values[5]	values[7]	188	1			T159	8		T172	16		T157	6
auto[1]	values[6]	values[0]	329	1			T115	92		T120	86		T107	10
auto[1]	values[6]	values[1]	290	1			T3	10		T105	10		T89	36
auto[1]	values[6]	values[2]	300	1			T2	4		T116	38		T126	32
auto[1]	values[6]	values[3]	137	1			T34	11		T3	5		T116	12
auto[1]	values[6]	values[4]	222	1			T23	16		T107	10		T5	21
auto[1]	values[6]	values[5]	178	1			T45	15		T116	6		T106	11
auto[1]	values[6]	values[6]	82	1			T103	7		T190	8		T172	10
auto[1]	values[6]	values[7]	144	1			T43	11		T47	4		T45	5
auto[1]	values[7]	values[0]	104	1			T193	11		T203	39		T204	6
auto[1]	values[7]	values[1]	251	1			T103	9		T117	9		T120	76
auto[1]	values[7]	values[2]	223	1			T45	8		T116	11		T5	7
auto[1]	values[7]	values[3]	304	1			T45	3		T3	8		T119	13
auto[1]	values[7]	values[4]	163	1			T5	21		T159	7		T157	7
auto[1]	values[7]	values[5]	310	1			T44	24		T45	7		T103	5
auto[1]	values[7]	values[6]	166	1			T155	6		T135	8		T205	13
auto[1]	values[7]	values[7]	232	1			T120	46		T5	13		T135	15