Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	423	1			T34	3		T43	2		T2	1
auto[ReadAddrCrossIntoMailbox]	321	1			T34	1		T50	1		T164	2
auto[ReadAddrCrossOutOfMailbox]	354	1			T43	2		T2	1		T56	1
auto[ReadAddrCrossAllMailbox]	263	1			T34	2		T43	1		T50	1
auto[ReadAddrOutsideMailbox]	3991	1			T22	6		T23	8		T24	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2615

1

T22

3

T23

4

T24

2

auto[1]

2737

1

T22

3

T23

4

T24

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	865	1			T22	2		T34	4		T43	5
read_ops[0x0b]	866	1			T22	2		T23	2		T32	2
read_ops[0x3b]	952	1			T22	2		T23	4		T34	2
read_ops[0x6b]	930	1			T23	2		T34	3		T44	2
read_ops[0xbb]	913	1			T24	4		T34	5		T44	2
read_ops[0xeb]	826	1			T32	2		T34	5		T44	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T47	1		T3	1		T103	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T3	1		T106	1		T89	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T34	1		T3	1		T119	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T3	1		T119	1		T106	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T70	1		T173	1		T169	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	41	1			T56	1		T3	1		T173	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T153	1		T159	1		T201	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T43	1		T117	1		T120	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T22	1		T43	3		T98	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T22	1		T34	3		T43	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T165	1		T155	1		T106	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T34	2		T3	1		T117	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T3	1		T173	1		T169	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T173	1		T169	1		T116	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T103	1		T117	1		T120	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T50	1		T45	1		T3	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T3	2		T119	1		T155	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T3	1		T106	2		T206	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	308	1			T22	1		T23	1		T32	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	331	1			T22	1		T23	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T43	1		T3	1		T103	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T156	1		T116	1		T5	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T3	2		T173	1		T103	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T3	2		T173	1		T207	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T43	1		T3	1		T103	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T70	1		T47	1		T3	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T173	1		T161	1		T116	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T47	1		T173	1		T161	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T22	1		T23	2		T34	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	378	1			T22	1		T23	2		T46	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T117	1		T106	1		T87	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T2	1		T50	1		T47	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T45	1		T3	1		T103	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T3	2		T154	1		T155	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T164	1		T116	1		T86	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T50	1		T164	1		T119	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	37	1			T70	1		T164	2		T45	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T34	1		T164	2		T107	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	336	1			T23	1		T44	1		T43	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	350	1			T23	1		T34	2		T44	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T43	1		T164	1		T3	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T164	1		T165	3		T155	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T164	1		T3	1		T116	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T50	1		T164	1		T3	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T119	1		T106	1		T182	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T116	1		T182	1		T87	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T34	1		T5	1		T205	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T50	1		T3	2		T116	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	334	1			T24	2		T34	1		T44	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	356	1			T24	2		T34	3		T44	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T173	1		T116	1		T155	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T34	1		T47	1		T3	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T3	1		T147	1		T159	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T103	1		T116	1		T5	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T50	1		T164	1		T103	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T43	1		T2	1		T164	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T116	1		T135	1		T149	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T3	1		T156	1		T116	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T32	1		T44	1		T46	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T32	1		T34	4		T44	1