Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7074732	1			T20	2662		T21	1		T22	351
all_pins[1]	7074732	1			T20	2662		T21	1		T22	351
all_pins[2]	7074732	1			T20	2662		T21	1		T22	351
all_pins[3]	7074732	1			T20	2662		T21	1		T22	351
all_pins[4]	7074732	1			T20	2662		T21	1		T22	351
all_pins[5]	7074732	1			T20	2662		T21	1		T22	351
all_pins[6]	7074732	1			T20	2662		T21	1		T22	351
all_pins[7]	7074732	1			T20	2662		T21	1		T22	351

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	56315770	1			T20	21296		T21	8		T22	2808
values[0x1]	282086	1			T28	55		T1	14		T2	10
transitions[0x0=>0x1]	278192	1			T28	44		T1	11		T2	8
transitions[0x1=>0x0]	278195	1			T28	44		T1	11		T2	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7072045	1			T20	2662		T21	1		T22	351
all_pins[0]	values[0x1]	2687	1			T28	7		T1	3		T56	5
all_pins[0]	transitions[0x0=>0x1]	2206	1			T28	6		T1	3		T56	3
all_pins[0]	transitions[0x1=>0x0]	79	1			T28	4		T1	3		T2	3
all_pins[1]	values[0x0]	7074172	1			T20	2662		T21	1		T22	351
all_pins[1]	values[0x1]	560	1			T28	5		T1	3		T2	3
all_pins[1]	transitions[0x0=>0x1]	470	1			T28	3		T1	2		T2	3
all_pins[1]	transitions[0x1=>0x0]	159	1			T28	2		T2	1		T56	2
all_pins[2]	values[0x0]	7074483	1			T20	2662		T21	1		T22	351
all_pins[2]	values[0x1]	249	1			T28	4		T1	1		T2	1
all_pins[2]	transitions[0x0=>0x1]	220	1			T28	4		T1	1		T2	1
all_pins[2]	transitions[0x1=>0x0]	61	1			T28	11		T56	1		T104	1
all_pins[3]	values[0x0]	7074642	1			T20	2662		T21	1		T22	351
all_pins[3]	values[0x1]	90	1			T28	11		T56	5		T3	2
all_pins[3]	transitions[0x0=>0x1]	67	1			T28	10		T56	1		T3	2
all_pins[3]	transitions[0x1=>0x0]	76	1			T28	4		T1	1		T65	1
all_pins[4]	values[0x0]	7074633	1			T20	2662		T21	1		T22	351
all_pins[4]	values[0x1]	99	1			T28	5		T1	1		T56	4
all_pins[4]	transitions[0x0=>0x1]	72	1			T28	3		T1	1		T56	4
all_pins[4]	transitions[0x1=>0x0]	6002	1			T28	8		T1	1		T56	1
all_pins[5]	values[0x0]	7068703	1			T20	2662		T21	1		T22	351
all_pins[5]	values[0x1]	6029	1			T28	10		T1	1		T56	1
all_pins[5]	transitions[0x0=>0x1]	2832	1			T28	7		T1	1		T3	581
all_pins[5]	transitions[0x1=>0x0]	269071	1			T28	1		T1	2		T2	3
all_pins[6]	values[0x0]	6802464	1			T20	2662		T21	1		T22	351
all_pins[6]	values[0x1]	272268	1			T28	4		T1	2		T2	3
all_pins[6]	transitions[0x0=>0x1]	272243	1			T28	4		T1	1		T2	1
all_pins[6]	transitions[0x1=>0x0]	79	1			T28	9		T1	2		T2	1
all_pins[7]	values[0x0]	7074628	1			T20	2662		T21	1		T22	351
all_pins[7]	values[0x1]	104	1			T28	9		T1	3		T2	3
all_pins[7]	transitions[0x0=>0x1]	82	1			T28	7		T1	2		T2	3
all_pins[7]	transitions[0x1=>0x0]	2668	1			T28	5		T1	2		T56	3