Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4574	1			T23	16		T29	2		T99	12
values[1]	4503	1			T21	8		T24	30		T32	6
values[2]	3868	1			T34	42		T46	18		T12	8
values[3]	3646	1			T34	24		T45	20		T3	64
values[4]	3822	1			T34	41		T43	43		T102	22
values[5]	4807	1			T43	55		T16	20		T97	22
values[6]	3966	1			T22	26		T44	24		T43	29
values[7]	3851	1			T27	8		T43	199		T98	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4336	1			T43	65		T47	20		T164	24
values[1]	4729	1			T24	30		T43	47		T48	20
values[2]	3848	1			T12	8		T50	20		T183	2
values[3]	4386	1			T22	26		T27	8		T34	45
values[4]	3603	1			T32	6		T43	20		T18	2
values[5]	3902	1			T21	8		T23	16		T29	2
values[6]	4084	1			T34	42		T43	73		T15	14
values[7]	4149	1			T34	20		T46	18		T43	121

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32449

1

T21

4

T22

26

T23

16

auto[1]

588

1

T21

4

T34

4

T44

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	536	1			T169	8		T89	25		T120	82
auto[0]	values[0]	values[1]	881	1			T43	47		T119	20		T89	20
auto[0]	values[0]	values[2]	521	1			T3	20		T208	12		T106	20
auto[0]	values[0]	values[3]	381	1			T99	12		T45	28		T187	14
auto[0]	values[0]	values[4]	401	1			T106	20		T87	20		T120	20
auto[0]	values[0]	values[5]	481	1			T23	16		T29	2		T116	20
auto[0]	values[0]	values[6]	766	1			T43	20		T15	14		T3	20
auto[0]	values[0]	values[7]	525	1			T177	12		T135	20		T199	20
auto[0]	values[1]	values[0]	466	1			T3	41		T106	21		T120	80
auto[0]	values[1]	values[1]	573	1			T24	30		T3	58		T189	26
auto[0]	values[1]	values[2]	657	1			T45	20		T155	24		T106	116
auto[0]	values[1]	values[3]	772	1			T195	4		T105	22		T5	21
auto[0]	values[1]	values[4]	517	1			T32	6		T146	27		T120	53
auto[0]	values[1]	values[5]	453	1			T21	4		T116	88		T209	2
auto[0]	values[1]	values[6]	444	1			T180	2		T116	89		T210	18
auto[0]	values[1]	values[7]	549	1			T115	101		T103	18		T117	20
auto[0]	values[2]	values[0]	637	1			T47	20		T3	48		T211	6
auto[0]	values[2]	values[1]	524	1			T178	10		T106	20		T212	24
auto[0]	values[2]	values[2]	446	1			T12	8		T116	23		T213	2
auto[0]	values[2]	values[3]	497	1			T47	28		T125	43		T146	20
auto[0]	values[2]	values[4]	447	1			T18	2		T3	49		T106	29
auto[0]	values[2]	values[5]	429	1			T56	20		T116	20		T155	28
auto[0]	values[2]	values[6]	374	1			T34	42		T107	24		T5	19
auto[0]	values[2]	values[7]	455	1			T46	16		T120	28		T5	30
auto[0]	values[3]	values[0]	508	1			T3	24		T124	20		T143	12
auto[0]	values[3]	values[1]	427	1			T106	20		T5	65		T159	21
auto[0]	values[3]	values[2]	310	1			T3	20		T116	20		T155	25
auto[0]	values[3]	values[3]	405	1			T34	22		T103	21		T116	20
auto[0]	values[3]	values[4]	418	1			T3	20		T117	51		T214	8
auto[0]	values[3]	values[5]	514	1			T175	6		T106	63		T120	73
auto[0]	values[3]	values[6]	634	1			T103	42		T87	21		T5	19
auto[0]	values[3]	values[7]	349	1			T45	20		T154	20		T106	40
auto[0]	values[4]	values[0]	572	1			T43	43		T3	30		T89	20
auto[0]	values[4]	values[1]	416	1			T47	26		T176	16		T117	23
auto[0]	values[4]	values[2]	540	1			T124	19		T135	19		T147	19
auto[0]	values[4]	values[3]	570	1			T34	21		T103	20		T161	8
auto[0]	values[4]	values[4]	316	1			T119	20		T89	18		T120	20
auto[0]	values[4]	values[5]	469	1			T124	37		T135	50		T174	12
auto[0]	values[4]	values[6]	434	1			T3	25		T121	6		T119	53
auto[0]	values[4]	values[7]	427	1			T34	18		T102	22		T118	37
auto[0]	values[5]	values[0]	615	1			T43	22		T45	49		T3	20
auto[0]	values[5]	values[1]	589	1			T3	64		T49	6		T116	20
auto[0]	values[5]	values[2]	463	1			T50	20		T173	12		T184	10
auto[0]	values[5]	values[3]	823	1			T50	22		T71	14		T185	10
auto[0]	values[5]	values[4]	647	1			T97	22		T47	18		T131	12
auto[0]	values[5]	values[5]	630	1			T43	33		T145	12		T47	35
auto[0]	values[5]	values[6]	504	1			T45	22		T116	18		T146	21
auto[0]	values[5]	values[7]	454	1			T16	20		T45	20		T106	25
auto[0]	values[6]	values[0]	543	1			T155	20		T5	25		T159	94
auto[0]	values[6]	values[1]	652	1			T48	16		T115	80		T3	38
auto[0]	values[6]	values[2]	475	1			T183	2		T186	8		T126	32
auto[0]	values[6]	values[3]	413	1			T22	26		T2	20		T207	4
auto[0]	values[6]	values[4]	444	1			T5	20		T205	22		T215	4
auto[0]	values[6]	values[5]	437	1			T44	22		T194	6		T45	20
auto[0]	values[6]	values[6]	454	1			T43	28		T45	58		T89	24
auto[0]	values[6]	values[7]	478	1			T191	4		T116	18		T155	27
auto[0]	values[7]	values[0]	380	1			T164	24		T116	20		T159	20
auto[0]	values[7]	values[1]	596	1			T3	20		T182	2		T179	22
auto[0]	values[7]	values[2]	366	1			T120	43		T5	20		T216	20
auto[0]	values[7]	values[3]	426	1			T27	8		T98	26		T3	42
auto[0]	values[7]	values[4]	358	1			T43	20		T119	19		T132	2
auto[0]	values[7]	values[5]	431	1			T43	33		T2	23		T106	20
auto[0]	values[7]	values[6]	395	1			T43	21		T70	20		T3	32
auto[0]	values[7]	values[7]	835	1			T43	118		T3	28		T106	23
auto[1]	values[0]	values[0]	13	1			T120	2		T135	2		T205	3
auto[1]	values[0]	values[1]	13	1			T138	3		T199	1		T77	2
auto[1]	values[0]	values[2]	10	1			T5	1		T135	2		T159	1
auto[1]	values[0]	values[3]	12	1			T45	6		T7	1		T130	1
auto[1]	values[0]	values[4]	7	1			T107	1		T5	4		T204	1
auto[1]	values[0]	values[5]	7	1			T159	1		T138	1		T150	1
auto[1]	values[0]	values[6]	17	1			T3	1		T120	2		T147	1
auto[1]	values[0]	values[7]	3	1			T217	2		T218	1		-	-
auto[1]	values[1]	values[0]	10	1			T3	1		T5	2		T138	4
auto[1]	values[1]	values[1]	8	1			T3	3		T219	2		T203	1
auto[1]	values[1]	values[2]	14	1			T155	1		T106	1		T220	2
auto[1]	values[1]	values[3]	13	1			T105	2		T153	1		T190	1
auto[1]	values[1]	values[4]	5	1			T146	1		T135	1		T144	2
auto[1]	values[1]	values[5]	11	1			T21	4		T116	1		T135	1
auto[1]	values[1]	values[6]	2	1			T5	1		T38	1		-	-
auto[1]	values[1]	values[7]	9	1			T115	1		T103	2		T117	1
auto[1]	values[2]	values[0]	18	1			T3	1		T5	4		T135	1
auto[1]	values[2]	values[1]	5	1			T221	2		T217	3		-	-
auto[1]	values[2]	values[2]	4	1			T107	1		T5	2		T135	1
auto[1]	values[2]	values[3]	7	1			T199	1		T190	2		T78	1
auto[1]	values[2]	values[4]	8	1			T222	1		T167	4		T223	2
auto[1]	values[2]	values[5]	1	1			T7	1		-	-		-	-
auto[1]	values[2]	values[6]	7	1			T107	3		T5	1		T162	1
auto[1]	values[2]	values[7]	9	1			T46	2		T120	1		T5	1
auto[1]	values[3]	values[0]	12	1			T7	1		T199	1		T157	1
auto[1]	values[3]	values[1]	2	1			T159	1		T136	1		-	-
auto[1]	values[3]	values[2]	7	1			T155	1		T89	1		T224	1
auto[1]	values[3]	values[3]	17	1			T34	2		T103	5		T107	6
auto[1]	values[3]	values[4]	4	1			T219	1		T225	1		T226	2
auto[1]	values[3]	values[5]	11	1			T197	3		T162	3		T224	3
auto[1]	values[3]	values[6]	16	1			T103	1		T5	1		T201	3
auto[1]	values[3]	values[7]	12	1			T107	3		T135	4		T227	1
auto[1]	values[4]	values[0]	5	1			T3	1		T38	2		T138	1
auto[1]	values[4]	values[1]	8	1			T47	1		T38	1		T172	2
auto[1]	values[4]	values[2]	12	1			T124	1		T135	1		T147	1
auto[1]	values[4]	values[3]	15	1			T103	2		T106	1		T77	2
auto[1]	values[4]	values[4]	5	1			T89	2		T7	1		T172	1
auto[1]	values[4]	values[5]	15	1			T124	1		T205	1		T162	6
auto[1]	values[4]	values[6]	8	1			T119	1		T120	1		T202	2
auto[1]	values[4]	values[7]	10	1			T34	2		T219	3		T228	2
auto[1]	values[5]	values[0]	15	1			T45	1		T103	3		T229	1
auto[1]	values[5]	values[1]	8	1			T49	4		T147	2		T193	1
auto[1]	values[5]	values[2]	6	1			T203	3		T230	2		T231	1
auto[1]	values[5]	values[3]	24	1			T3	3		T117	5		T7	1
auto[1]	values[5]	values[4]	8	1			T47	2		T116	1		T147	1
auto[1]	values[5]	values[5]	4	1			T157	1		T232	3		-	-
auto[1]	values[5]	values[6]	11	1			T45	1		T116	2		T199	1
auto[1]	values[5]	values[7]	6	1			T138	1		T78	1		T224	1
auto[1]	values[6]	values[0]	4	1			T204	3		T221	1		-	-
auto[1]	values[6]	values[1]	18	1			T48	4		T116	1		T203	2
auto[1]	values[6]	values[2]	3	1			T157	1		T136	1		T233	1
auto[1]	values[6]	values[3]	3	1			T107	1		T5	1		T159	1
auto[1]	values[6]	values[4]	14	1			T205	2		T77	1		T172	1
auto[1]	values[6]	values[5]	5	1			T44	2		T77	2		T190	1
auto[1]	values[6]	values[6]	8	1			T43	1		T45	2		T89	1
auto[1]	values[6]	values[7]	15	1			T116	2		T155	3		T234	2
auto[1]	values[7]	values[0]	2	1			T78	1		T203	1		-	-
auto[1]	values[7]	values[1]	9	1			T162	1		T229	1		T91	2
auto[1]	values[7]	values[2]	14	1			T120	1		T216	6		T235	4
auto[1]	values[7]	values[3]	8	1			T205	4		T130	1		T150	1
auto[1]	values[7]	values[4]	4	1			T119	1		T228	1		T229	1
auto[1]	values[7]	values[5]	4	1			T43	1		T130	1		T162	1
auto[1]	values[7]	values[6]	10	1			T43	3		T103	3		T135	1
auto[1]	values[7]	values[7]	13	1			T43	3		T205	1		T77	1