Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2565

1

T20

8

T25

16

T30

4

auto[1]

2563

1

T20

7

T25

1

T30

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2690

1

T20

13

T30

15

T33

6

auto[1]

2438

1

T20

2

T25

17

T33

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4079

1

T20

5

T25

17

T30

8

auto[1]

1049

1

T20

10

T30

7

T33

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	980	1			T20	3		T25	3		T30	3
valid[1]	1036	1			T20	5		T25	4		T30	1
valid[2]	1057	1			T20	3		T25	3		T30	2
valid[3]	1021	1			T20	1		T25	2		T30	4
valid[4]	1034	1			T20	3		T25	5		T30	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	158	1			T30	2		T34	1		T36	1
auto[0]	auto[0]	valid[0]	auto[1]	234	1			T25	3		T35	1		T93	2
auto[0]	auto[0]	valid[1]	auto[0]	159	1			T20	1		T34	7		T37	4
auto[0]	auto[0]	valid[1]	auto[1]	256	1			T25	4		T33	1		T35	2
auto[0]	auto[0]	valid[2]	auto[0]	158	1			T33	1		T34	4		T36	3
auto[0]	auto[0]	valid[2]	auto[1]	271	1			T25	2		T35	7		T94	3
auto[0]	auto[0]	valid[3]	auto[0]	174	1			T34	4		T36	1		T73	6
auto[0]	auto[0]	valid[3]	auto[1]	250	1			T25	2		T35	2		T93	1
auto[0]	auto[0]	valid[4]	auto[0]	172	1			T20	1		T34	3		T36	2
auto[0]	auto[0]	valid[4]	auto[1]	232	1			T25	5		T34	1		T35	1
auto[0]	auto[1]	valid[0]	auto[0]	152	1			T34	4		T36	2		T37	2
auto[0]	auto[1]	valid[0]	auto[1]	218	1			T33	1		T35	3		T2	1
auto[0]	auto[1]	valid[1]	auto[0]	156	1			T20	1		T34	1		T36	1
auto[0]	auto[1]	valid[1]	auto[1]	253	1			T20	1		T33	1		T35	6
auto[0]	auto[1]	valid[2]	auto[0]	187	1			T30	1		T33	1		T34	6
auto[0]	auto[1]	valid[2]	auto[1]	234	1			T25	1		T35	3		T2	1
auto[0]	auto[1]	valid[3]	auto[0]	154	1			T30	2		T34	3		T37	3
auto[0]	auto[1]	valid[3]	auto[1]	225	1			T35	4		T93	2		T94	1
auto[0]	auto[1]	valid[4]	auto[0]	171	1			T30	3		T34	3		T37	1
auto[0]	auto[1]	valid[4]	auto[1]	265	1			T20	1		T35	6		T2	1
auto[1]	auto[0]	valid[0]	auto[0]	111	1			T20	2		T33	1		T36	1
auto[1]	auto[0]	valid[1]	auto[0]	99	1			T20	1		T34	3		T36	2
auto[1]	auto[0]	valid[2]	auto[0]	95	1			T20	3		T34	1		T37	1
auto[1]	auto[0]	valid[3]	auto[0]	110	1			T30	1		T34	1		T37	2
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T30	1		T33	1		T34	1
auto[1]	auto[1]	valid[0]	auto[0]	107	1			T20	1		T30	1		T36	2
auto[1]	auto[1]	valid[1]	auto[0]	113	1			T20	1		T30	1		T34	2
auto[1]	auto[1]	valid[2]	auto[0]	112	1			T30	1		T34	2		T37	1
auto[1]	auto[1]	valid[3]	auto[0]	108	1			T20	1		T30	1		T33	2
auto[1]	auto[1]	valid[4]	auto[0]	108	1			T20	1		T30	1		T34	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal