Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67801

1

T20

239

T30

410

T33

187

auto[1]

24088

1

T20

44

T25

194

T33

40

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66901

1

T20

184

T25

194

T30

280

auto[1]

24988

1

T20

99

T30

130

T33

74

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	47225	1			T20	143		T25	107		T30	222
others[1]	7778	1			T20	28		T25	16		T30	27
others[2]	7631	1			T20	26		T25	15		T30	32
others[3]	8690	1			T20	30		T25	14		T30	44
interest[1]	5115	1			T20	17		T25	16		T30	21
interest[4]	31079	1			T20	94		T25	69		T30	140
interest[64]	15450	1			T20	39		T25	26		T30	64

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	21895	1			T20	73		T30	153		T33	60
auto[0]	auto[0]	others[1]	3688	1			T20	8		T30	16		T33	9
auto[0]	auto[0]	others[2]	3558	1			T20	14		T30	19		T33	7
auto[0]	auto[0]	others[3]	4133	1			T20	15		T30	32		T33	14
auto[0]	auto[0]	interest[1]	2330	1			T20	10		T30	15		T33	6
auto[0]	auto[0]	interest[4]	14392	1			T20	52		T30	101		T33	41
auto[0]	auto[0]	interest[64]	7209	1			T20	20		T30	45		T33	17
auto[0]	auto[1]	others[0]	12594	1			T20	17		T25	107		T33	24
auto[0]	auto[1]	others[1]	1987	1			T20	6		T25	16		T33	2
auto[0]	auto[1]	others[2]	1963	1			T20	7		T25	15		T33	4
auto[0]	auto[1]	others[3]	2175	1			T20	6		T25	14		T33	1
auto[0]	auto[1]	interest[1]	1378	1			T25	16		T33	2		T34	4
auto[0]	auto[1]	interest[4]	8476	1			T20	11		T25	69		T33	19
auto[0]	auto[1]	interest[64]	3991	1			T20	8		T25	26		T33	7
auto[1]	auto[0]	others[0]	12736	1			T20	53		T30	69		T33	41
auto[1]	auto[0]	others[1]	2103	1			T20	14		T30	11		T33	4
auto[1]	auto[0]	others[2]	2110	1			T20	5		T30	13		T33	4
auto[1]	auto[0]	others[3]	2382	1			T20	9		T30	12		T33	10
auto[1]	auto[0]	interest[1]	1407	1			T20	7		T30	6		T33	4
auto[1]	auto[0]	interest[4]	8211	1			T20	31		T30	39		T33	30
auto[1]	auto[0]	interest[64]	4250	1			T20	11		T30	19		T33	11

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal