Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	415	1			T28	24		T1	7		T2	4
all_values[1]	415	1			T28	24		T1	7		T2	4
all_values[2]	415	1			T28	24		T1	7		T2	4
all_values[3]	415	1			T28	24		T1	7		T2	4
all_values[4]	415	1			T28	24		T1	7		T2	4
all_values[5]	415	1			T28	24		T1	7		T2	4
all_values[6]	415	1			T28	24		T1	7		T2	4
all_values[7]	415	1			T28	24		T1	7		T2	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1738

1

T28

102

T1

31

T2

24

auto[1]

1582

1

T28

90

T1

25

T2

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1296

1

T28

57

T1

20

T2

8

auto[1]

2024

1

T28

135

T1

36

T2

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1882

1

T28

96

T1

30

T2

17

auto[1]

1438

1

T28

96

T1

26

T2

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	67	1			T28	2		T2	3		T56	1
all_values[0]	auto[0]	auto[0]	auto[1]	54	1			T28	1		T1	1		T56	1
all_values[0]	auto[0]	auto[1]	auto[0]	78	1			T28	3		T3	2		T114	1
all_values[0]	auto[0]	auto[1]	auto[1]	34	1			T28	5		T1	1		T56	1
all_values[0]	auto[1]	auto[0]	auto[1]	111	1			T28	9		T1	2		T56	1
all_values[0]	auto[1]	auto[1]	auto[1]	71	1			T28	4		T1	3		T2	1
all_values[1]	auto[0]	auto[0]	auto[0]	73	1			T28	4		T56	1		T3	2
all_values[1]	auto[0]	auto[0]	auto[1]	42	1			T28	6		T56	1		T104	3
all_values[1]	auto[0]	auto[1]	auto[0]	77	1			T28	1		T1	2		T56	1
all_values[1]	auto[0]	auto[1]	auto[1]	43	1			T28	3		T1	1		T2	1
all_values[1]	auto[1]	auto[0]	auto[1]	98	1			T28	9		T1	2		T2	2
all_values[1]	auto[1]	auto[1]	auto[1]	82	1			T28	1		T1	2		T2	1
all_values[2]	auto[0]	auto[0]	auto[0]	78	1			T28	3		T1	4		T56	2
all_values[2]	auto[0]	auto[0]	auto[1]	46	1			T28	2		T2	2		T104	1
all_values[2]	auto[0]	auto[1]	auto[0]	68	1			T28	5		T65	1		T104	3
all_values[2]	auto[0]	auto[1]	auto[1]	38	1			T28	3		T56	2		T3	1
all_values[2]	auto[1]	auto[0]	auto[1]	97	1			T28	4		T1	1		T2	1
all_values[2]	auto[1]	auto[1]	auto[1]	88	1			T28	7		T1	2		T2	1
all_values[3]	auto[0]	auto[0]	auto[0]	92	1			T28	3		T1	2		T56	1
all_values[3]	auto[0]	auto[0]	auto[1]	41	1			T28	3		T1	1		T2	2
all_values[3]	auto[0]	auto[1]	auto[0]	81	1			T28	5		T1	2		T104	1
all_values[3]	auto[0]	auto[1]	auto[1]	39	1			T28	3		T56	2		T3	1
all_values[3]	auto[1]	auto[0]	auto[1]	92	1			T28	5		T1	1		T2	2
all_values[3]	auto[1]	auto[1]	auto[1]	70	1			T28	5		T1	1		T56	3
all_values[4]	auto[0]	auto[0]	auto[0]	86	1			T28	4		T1	1		T2	3
all_values[4]	auto[0]	auto[0]	auto[1]	41	1			T28	3		T1	2		T104	2
all_values[4]	auto[0]	auto[1]	auto[0]	75	1			T28	3		T56	2		T65	2
all_values[4]	auto[0]	auto[1]	auto[1]	44	1			T28	1		T56	2		T104	3
all_values[4]	auto[1]	auto[0]	auto[1]	92	1			T28	8		T1	3		T2	1
all_values[4]	auto[1]	auto[1]	auto[1]	77	1			T28	5		T1	1		T56	1
all_values[5]	auto[0]	auto[0]	auto[0]	104	1			T28	4		T1	1		T2	2
all_values[5]	auto[0]	auto[1]	auto[0]	117	1			T28	7		T1	2		T56	3
all_values[5]	auto[1]	auto[0]	auto[1]	95	1			T28	3		T1	3		T2	2
all_values[5]	auto[1]	auto[1]	auto[1]	99	1			T28	10		T1	1		T56	1
all_values[6]	auto[0]	auto[0]	auto[0]	81	1			T28	6		T1	2		T56	2
all_values[6]	auto[0]	auto[0]	auto[1]	35	1			T28	2		T56	1		T3	2
all_values[6]	auto[0]	auto[1]	auto[0]	82	1			T28	2		T1	2		T56	3
all_values[6]	auto[0]	auto[1]	auto[1]	38	1			T28	1		T1	2		T2	1
all_values[6]	auto[1]	auto[0]	auto[1]	90	1			T28	9		T2	2		T56	2
all_values[6]	auto[1]	auto[1]	auto[1]	89	1			T28	4		T1	1		T2	1
all_values[7]	auto[0]	auto[0]	auto[0]	77	1			T28	4		T1	2		T56	1
all_values[7]	auto[0]	auto[0]	auto[1]	44	1			T28	3		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	auto[0]	60	1			T28	1		T56	2		T104	2
all_values[7]	auto[0]	auto[1]	auto[1]	47	1			T28	3		T1	2		T2	2
all_values[7]	auto[1]	auto[0]	auto[1]	102	1			T28	5		T1	3		T2	1
all_values[7]	auto[1]	auto[1]	auto[1]	85	1			T28	8		T56	2		T104	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal