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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.94 98.37 93.30 98.21 89.36 97.03 86.17 95.10


Total test records in report: 939
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T762 /workspace/coverage/default/10.spi_device_cfg_cmd.1652122738 Mar 14 01:25:24 PM PDT 24 Mar 14 01:25:28 PM PDT 24 2081981406 ps
T763 /workspace/coverage/default/45.spi_device_mailbox.622434248 Mar 14 01:27:32 PM PDT 24 Mar 14 01:28:13 PM PDT 24 57449117946 ps
T764 /workspace/coverage/default/13.spi_device_flash_mode.1029996678 Mar 14 01:25:39 PM PDT 24 Mar 14 01:26:04 PM PDT 24 48507292794 ps
T765 /workspace/coverage/default/40.spi_device_alert_test.1528169077 Mar 14 01:27:04 PM PDT 24 Mar 14 01:27:05 PM PDT 24 58207875 ps
T766 /workspace/coverage/default/38.spi_device_mailbox.2649805463 Mar 14 01:27:08 PM PDT 24 Mar 14 01:27:20 PM PDT 24 2788921256 ps
T767 /workspace/coverage/default/23.spi_device_alert_test.48199459 Mar 14 01:26:14 PM PDT 24 Mar 14 01:26:15 PM PDT 24 15663184 ps
T91 /workspace/coverage/default/6.spi_device_stress_all.3173090160 Mar 14 01:25:03 PM PDT 24 Mar 14 01:28:24 PM PDT 24 59831407893 ps
T768 /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2405983908 Mar 14 01:26:51 PM PDT 24 Mar 14 01:26:59 PM PDT 24 976395307 ps
T769 /workspace/coverage/default/42.spi_device_flash_mode.3600676843 Mar 14 01:27:14 PM PDT 24 Mar 14 01:27:35 PM PDT 24 2408423427 ps
T770 /workspace/coverage/default/33.spi_device_flash_mode.3433402488 Mar 14 01:26:48 PM PDT 24 Mar 14 01:27:16 PM PDT 24 5314681300 ps
T771 /workspace/coverage/default/39.spi_device_tpm_sts_read.1342141414 Mar 14 01:27:10 PM PDT 24 Mar 14 01:27:11 PM PDT 24 38947167 ps
T772 /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3165125553 Mar 14 01:27:02 PM PDT 24 Mar 14 01:27:35 PM PDT 24 18108898690 ps
T232 /workspace/coverage/default/0.spi_device_flash_all.2991329829 Mar 14 01:24:51 PM PDT 24 Mar 14 01:28:08 PM PDT 24 72273555782 ps
T773 /workspace/coverage/default/38.spi_device_flash_mode.1723251648 Mar 14 01:27:08 PM PDT 24 Mar 14 01:27:23 PM PDT 24 1551107635 ps
T774 /workspace/coverage/default/49.spi_device_flash_mode.3032079363 Mar 14 01:27:46 PM PDT 24 Mar 14 01:28:00 PM PDT 24 2331829986 ps
T64 /workspace/coverage/default/4.spi_device_sec_cm.130185352 Mar 14 01:24:59 PM PDT 24 Mar 14 01:25:00 PM PDT 24 252173593 ps
T775 /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4031570918 Mar 14 01:26:39 PM PDT 24 Mar 14 01:26:42 PM PDT 24 772990845 ps
T776 /workspace/coverage/default/1.spi_device_csb_read.2301639384 Mar 14 01:24:50 PM PDT 24 Mar 14 01:24:51 PM PDT 24 38177576 ps
T777 /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4018184180 Mar 14 01:24:50 PM PDT 24 Mar 14 01:24:56 PM PDT 24 1501838546 ps
T778 /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2983873480 Mar 14 01:26:38 PM PDT 24 Mar 14 01:31:09 PM PDT 24 190990420077 ps
T779 /workspace/coverage/default/4.spi_device_tpm_all.1481906413 Mar 14 01:25:01 PM PDT 24 Mar 14 01:25:28 PM PDT 24 17073718357 ps
T780 /workspace/coverage/default/18.spi_device_ram_cfg.2503700363 Mar 14 01:25:54 PM PDT 24 Mar 14 01:25:55 PM PDT 24 18116395 ps
T217 /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3359882245 Mar 14 01:24:46 PM PDT 24 Mar 14 01:27:58 PM PDT 24 15452225681 ps
T781 /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2902813230 Mar 14 01:27:00 PM PDT 24 Mar 14 01:27:23 PM PDT 24 36526494894 ps
T782 /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2753652114 Mar 14 01:24:55 PM PDT 24 Mar 14 01:25:30 PM PDT 24 5773171033 ps
T226 /workspace/coverage/default/32.spi_device_stress_all.4053118667 Mar 14 01:26:37 PM PDT 24 Mar 14 01:37:36 PM PDT 24 393073192497 ps
T783 /workspace/coverage/default/34.spi_device_tpm_sts_read.2689360933 Mar 14 01:26:49 PM PDT 24 Mar 14 01:26:50 PM PDT 24 163557253 ps
T784 /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3075014944 Mar 14 01:25:40 PM PDT 24 Mar 14 01:27:04 PM PDT 24 18047358785 ps
T785 /workspace/coverage/default/29.spi_device_intercept.346331445 Mar 14 01:26:38 PM PDT 24 Mar 14 01:26:49 PM PDT 24 3975381982 ps
T786 /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3140747715 Mar 14 01:26:02 PM PDT 24 Mar 14 01:26:05 PM PDT 24 415245859 ps
T787 /workspace/coverage/default/48.spi_device_upload.3763324736 Mar 14 01:27:46 PM PDT 24 Mar 14 01:27:53 PM PDT 24 2299759323 ps
T788 /workspace/coverage/default/42.spi_device_read_buffer_direct.2583783019 Mar 14 01:27:19 PM PDT 24 Mar 14 01:27:24 PM PDT 24 714896406 ps
T789 /workspace/coverage/default/7.spi_device_upload.870855770 Mar 14 01:25:25 PM PDT 24 Mar 14 01:25:37 PM PDT 24 11666209516 ps
T790 /workspace/coverage/default/45.spi_device_tpm_all.3744990044 Mar 14 01:27:31 PM PDT 24 Mar 14 01:27:39 PM PDT 24 500132678 ps
T791 /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3936176202 Mar 14 01:27:42 PM PDT 24 Mar 14 01:28:30 PM PDT 24 2919847675 ps
T792 /workspace/coverage/default/7.spi_device_tpm_sts_read.653241249 Mar 14 01:25:04 PM PDT 24 Mar 14 01:25:05 PM PDT 24 338829632 ps
T793 /workspace/coverage/default/10.spi_device_alert_test.4132591911 Mar 14 01:25:28 PM PDT 24 Mar 14 01:25:29 PM PDT 24 18071694 ps
T794 /workspace/coverage/default/44.spi_device_cfg_cmd.1081277727 Mar 14 01:27:14 PM PDT 24 Mar 14 01:27:18 PM PDT 24 586468977 ps
T795 /workspace/coverage/default/5.spi_device_intercept.2320826759 Mar 14 01:24:59 PM PDT 24 Mar 14 01:25:06 PM PDT 24 6917835577 ps
T796 /workspace/coverage/default/13.spi_device_flash_all.2241188594 Mar 14 01:25:37 PM PDT 24 Mar 14 01:27:26 PM PDT 24 38740242204 ps
T797 /workspace/coverage/default/14.spi_device_flash_all.457561514 Mar 14 01:25:38 PM PDT 24 Mar 14 01:26:16 PM PDT 24 29291024125 ps
T798 /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3699710613 Mar 14 01:26:29 PM PDT 24 Mar 14 01:30:30 PM PDT 24 40117597953 ps
T799 /workspace/coverage/default/21.spi_device_upload.977345848 Mar 14 01:26:04 PM PDT 24 Mar 14 01:26:28 PM PDT 24 23345410751 ps
T800 /workspace/coverage/default/43.spi_device_alert_test.1242161131 Mar 14 01:27:18 PM PDT 24 Mar 14 01:27:20 PM PDT 24 13775096 ps
T801 /workspace/coverage/default/7.spi_device_stress_all.583151750 Mar 14 01:25:19 PM PDT 24 Mar 14 01:26:51 PM PDT 24 18041443320 ps
T802 /workspace/coverage/default/22.spi_device_mailbox.170862482 Mar 14 01:26:06 PM PDT 24 Mar 14 01:26:13 PM PDT 24 1050745044 ps
T803 /workspace/coverage/default/46.spi_device_tpm_rw.2476843662 Mar 14 01:27:39 PM PDT 24 Mar 14 01:27:41 PM PDT 24 328400688 ps
T804 /workspace/coverage/default/36.spi_device_alert_test.1051181972 Mar 14 01:26:52 PM PDT 24 Mar 14 01:26:53 PM PDT 24 24433442 ps
T805 /workspace/coverage/default/39.spi_device_stress_all.876381324 Mar 14 01:27:01 PM PDT 24 Mar 14 01:38:20 PM PDT 24 355833581640 ps
T806 /workspace/coverage/default/30.spi_device_alert_test.4170977127 Mar 14 01:26:34 PM PDT 24 Mar 14 01:26:35 PM PDT 24 34895002 ps
T807 /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3346177069 Mar 14 01:26:25 PM PDT 24 Mar 14 01:26:33 PM PDT 24 5101529446 ps
T808 /workspace/coverage/default/26.spi_device_upload.1909762360 Mar 14 01:26:24 PM PDT 24 Mar 14 01:26:39 PM PDT 24 24408236828 ps
T809 /workspace/coverage/default/48.spi_device_tpm_sts_read.513792810 Mar 14 01:27:43 PM PDT 24 Mar 14 01:27:44 PM PDT 24 87330544 ps
T810 /workspace/coverage/default/48.spi_device_csb_read.4126466455 Mar 14 01:27:44 PM PDT 24 Mar 14 01:27:45 PM PDT 24 54252225 ps
T811 /workspace/coverage/default/19.spi_device_mailbox.694477976 Mar 14 01:25:55 PM PDT 24 Mar 14 01:26:01 PM PDT 24 297786754 ps
T812 /workspace/coverage/default/25.spi_device_csb_read.3893054479 Mar 14 01:26:19 PM PDT 24 Mar 14 01:26:20 PM PDT 24 22644700 ps
T813 /workspace/coverage/default/32.spi_device_alert_test.2714282513 Mar 14 01:26:43 PM PDT 24 Mar 14 01:26:44 PM PDT 24 23281011 ps
T814 /workspace/coverage/default/23.spi_device_tpm_rw.2543953785 Mar 14 01:26:07 PM PDT 24 Mar 14 01:26:20 PM PDT 24 609182547 ps
T815 /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.692894907 Mar 14 01:25:07 PM PDT 24 Mar 14 01:25:20 PM PDT 24 14773218958 ps
T816 /workspace/coverage/default/2.spi_device_intercept.4283810650 Mar 14 01:24:50 PM PDT 24 Mar 14 01:24:53 PM PDT 24 430024630 ps
T817 /workspace/coverage/default/36.spi_device_tpm_rw.1670164695 Mar 14 01:26:54 PM PDT 24 Mar 14 01:26:57 PM PDT 24 84695869 ps
T818 /workspace/coverage/default/14.spi_device_csb_read.1558989681 Mar 14 01:25:35 PM PDT 24 Mar 14 01:25:36 PM PDT 24 33624482 ps
T819 /workspace/coverage/default/21.spi_device_flash_all.3217835271 Mar 14 01:26:04 PM PDT 24 Mar 14 01:27:35 PM PDT 24 53793664836 ps
T820 /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3379668698 Mar 14 01:26:48 PM PDT 24 Mar 14 01:27:50 PM PDT 24 4428475672 ps
T821 /workspace/coverage/default/45.spi_device_alert_test.836046816 Mar 14 01:27:32 PM PDT 24 Mar 14 01:27:33 PM PDT 24 27576678 ps
T822 /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3859540365 Mar 14 01:27:00 PM PDT 24 Mar 14 01:28:36 PM PDT 24 5240721370 ps
T823 /workspace/coverage/default/49.spi_device_mailbox.3048069818 Mar 14 01:27:52 PM PDT 24 Mar 14 01:27:59 PM PDT 24 996275690 ps
T824 /workspace/coverage/default/43.spi_device_intercept.2925001608 Mar 14 01:27:14 PM PDT 24 Mar 14 01:27:18 PM PDT 24 401552218 ps
T825 /workspace/coverage/default/2.spi_device_pass_cmd_filtering.897870771 Mar 14 01:24:51 PM PDT 24 Mar 14 01:25:16 PM PDT 24 28523622191 ps
T826 /workspace/coverage/default/15.spi_device_cfg_cmd.608250594 Mar 14 01:25:38 PM PDT 24 Mar 14 01:25:45 PM PDT 24 5354652888 ps
T827 /workspace/coverage/default/16.spi_device_flash_and_tpm.415312826 Mar 14 01:25:41 PM PDT 24 Mar 14 01:28:20 PM PDT 24 92170343182 ps
T828 /workspace/coverage/default/10.spi_device_mem_parity.256894839 Mar 14 01:25:25 PM PDT 24 Mar 14 01:25:27 PM PDT 24 245699734 ps
T829 /workspace/coverage/default/43.spi_device_mailbox.193444779 Mar 14 01:27:12 PM PDT 24 Mar 14 01:27:32 PM PDT 24 24501020050 ps
T830 /workspace/coverage/default/48.spi_device_cfg_cmd.2507284244 Mar 14 01:27:46 PM PDT 24 Mar 14 01:27:51 PM PDT 24 3313636436 ps
T831 /workspace/coverage/default/15.spi_device_ram_cfg.1721128955 Mar 14 01:25:37 PM PDT 24 Mar 14 01:25:39 PM PDT 24 50693852 ps
T832 /workspace/coverage/default/3.spi_device_upload.3835502681 Mar 14 01:25:07 PM PDT 24 Mar 14 01:25:29 PM PDT 24 8334444408 ps
T233 /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.854603314 Mar 14 01:25:25 PM PDT 24 Mar 14 01:28:22 PM PDT 24 63139951211 ps
T833 /workspace/coverage/default/44.spi_device_read_buffer_direct.2372107412 Mar 14 01:27:16 PM PDT 24 Mar 14 01:27:21 PM PDT 24 327804474 ps
T834 /workspace/coverage/default/46.spi_device_flash_and_tpm.357204007 Mar 14 01:27:40 PM PDT 24 Mar 14 01:28:26 PM PDT 24 31839502645 ps
T835 /workspace/coverage/default/24.spi_device_cfg_cmd.1192734465 Mar 14 01:26:09 PM PDT 24 Mar 14 01:26:15 PM PDT 24 1878847955 ps
T836 /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2475484375 Mar 14 01:27:03 PM PDT 24 Mar 14 01:27:27 PM PDT 24 6565350332 ps
T837 /workspace/coverage/default/42.spi_device_mailbox.789126104 Mar 14 01:27:14 PM PDT 24 Mar 14 01:27:26 PM PDT 24 5360270338 ps
T838 /workspace/coverage/default/19.spi_device_read_buffer_direct.4192104021 Mar 14 01:25:59 PM PDT 24 Mar 14 01:26:05 PM PDT 24 1059056016 ps
T839 /workspace/coverage/default/38.spi_device_flash_and_tpm.2483346585 Mar 14 01:27:02 PM PDT 24 Mar 14 01:27:56 PM PDT 24 23960063992 ps
T840 /workspace/coverage/default/46.spi_device_cfg_cmd.897459865 Mar 14 01:27:33 PM PDT 24 Mar 14 01:27:39 PM PDT 24 8541582455 ps
T841 /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2889559354 Mar 14 01:26:38 PM PDT 24 Mar 14 01:28:49 PM PDT 24 7505694319 ps
T842 /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1330451327 Mar 14 01:25:21 PM PDT 24 Mar 14 01:25:38 PM PDT 24 7213300503 ps
T843 /workspace/coverage/default/12.spi_device_flash_and_tpm.3972073266 Mar 14 01:25:36 PM PDT 24 Mar 14 01:27:25 PM PDT 24 14870660111 ps
T844 /workspace/coverage/default/23.spi_device_intercept.2592571467 Mar 14 01:26:05 PM PDT 24 Mar 14 01:26:17 PM PDT 24 7621482405 ps
T845 /workspace/coverage/default/17.spi_device_cfg_cmd.1268620585 Mar 14 01:25:55 PM PDT 24 Mar 14 01:25:57 PM PDT 24 160374176 ps
T846 /workspace/coverage/default/7.spi_device_flash_all.3985030296 Mar 14 01:25:19 PM PDT 24 Mar 14 01:26:08 PM PDT 24 7572669871 ps
T847 /workspace/coverage/default/2.spi_device_flash_mode.411797846 Mar 14 01:24:50 PM PDT 24 Mar 14 01:25:02 PM PDT 24 1149489332 ps
T848 /workspace/coverage/default/30.spi_device_tpm_rw.63849972 Mar 14 01:26:43 PM PDT 24 Mar 14 01:26:45 PM PDT 24 75207436 ps
T168 /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2981210932 Mar 14 01:26:38 PM PDT 24 Mar 14 01:26:46 PM PDT 24 472500486 ps
T849 /workspace/coverage/default/36.spi_device_csb_read.4160845597 Mar 14 01:26:49 PM PDT 24 Mar 14 01:26:50 PM PDT 24 42008345 ps
T850 /workspace/coverage/default/31.spi_device_stress_all.952755519 Mar 14 01:26:28 PM PDT 24 Mar 14 01:30:20 PM PDT 24 102647160678 ps
T851 /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1609623540 Mar 14 01:24:53 PM PDT 24 Mar 14 01:25:00 PM PDT 24 4242934199 ps
T852 /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4225944225 Mar 14 01:27:39 PM PDT 24 Mar 14 01:27:44 PM PDT 24 1833142594 ps
T853 /workspace/coverage/default/45.spi_device_tpm_rw.2933993256 Mar 14 01:27:32 PM PDT 24 Mar 14 01:27:35 PM PDT 24 306030806 ps
T231 /workspace/coverage/default/43.spi_device_stress_all.1921981706 Mar 14 01:27:15 PM PDT 24 Mar 14 01:28:50 PM PDT 24 7675161076 ps
T854 /workspace/coverage/default/14.spi_device_intercept.1593826441 Mar 14 01:25:37 PM PDT 24 Mar 14 01:25:43 PM PDT 24 372020552 ps
T855 /workspace/coverage/default/1.spi_device_mailbox.2952590942 Mar 14 01:24:49 PM PDT 24 Mar 14 01:25:29 PM PDT 24 33654400985 ps
T856 /workspace/coverage/default/37.spi_device_upload.1625354292 Mar 14 01:27:01 PM PDT 24 Mar 14 01:27:16 PM PDT 24 3421493173 ps
T857 /workspace/coverage/default/9.spi_device_upload.2724380443 Mar 14 01:25:21 PM PDT 24 Mar 14 01:25:29 PM PDT 24 6903948613 ps
T858 /workspace/coverage/default/5.spi_device_stress_all.4166883931 Mar 14 01:25:07 PM PDT 24 Mar 14 01:27:33 PM PDT 24 13829547028 ps
T859 /workspace/coverage/default/43.spi_device_upload.1839644136 Mar 14 01:27:22 PM PDT 24 Mar 14 01:27:40 PM PDT 24 29336114656 ps
T860 /workspace/coverage/default/6.spi_device_tpm_all.3152522264 Mar 14 01:25:05 PM PDT 24 Mar 14 01:25:43 PM PDT 24 9267772922 ps
T861 /workspace/coverage/default/30.spi_device_upload.2393845567 Mar 14 01:26:36 PM PDT 24 Mar 14 01:26:43 PM PDT 24 381252473 ps
T862 /workspace/coverage/default/0.spi_device_tpm_all.2288824915 Mar 14 01:24:47 PM PDT 24 Mar 14 01:25:05 PM PDT 24 3115049182 ps
T863 /workspace/coverage/default/5.spi_device_cfg_cmd.2401305850 Mar 14 01:25:05 PM PDT 24 Mar 14 01:25:12 PM PDT 24 5229947595 ps
T864 /workspace/coverage/default/2.spi_device_tpm_rw.1826518665 Mar 14 01:24:48 PM PDT 24 Mar 14 01:24:58 PM PDT 24 515967235 ps
T865 /workspace/coverage/default/20.spi_device_upload.2197858056 Mar 14 01:25:59 PM PDT 24 Mar 14 01:26:04 PM PDT 24 785511360 ps
T866 /workspace/coverage/default/1.spi_device_pass_cmd_filtering.935426759 Mar 14 01:24:55 PM PDT 24 Mar 14 01:25:00 PM PDT 24 267271902 ps
T867 /workspace/coverage/default/30.spi_device_csb_read.3812864562 Mar 14 01:26:36 PM PDT 24 Mar 14 01:26:37 PM PDT 24 149313380 ps
T868 /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2239128718 Mar 14 01:27:02 PM PDT 24 Mar 14 01:27:16 PM PDT 24 8316696675 ps
T869 /workspace/coverage/default/33.spi_device_csb_read.182173733 Mar 14 01:26:33 PM PDT 24 Mar 14 01:26:34 PM PDT 24 16056052 ps
T870 /workspace/coverage/default/14.spi_device_cfg_cmd.2016637494 Mar 14 01:25:39 PM PDT 24 Mar 14 01:25:45 PM PDT 24 8990745983 ps
T871 /workspace/coverage/default/30.spi_device_flash_all.1758911016 Mar 14 01:26:32 PM PDT 24 Mar 14 01:26:41 PM PDT 24 1474882730 ps
T872 /workspace/coverage/default/46.spi_device_tpm_sts_read.1699588614 Mar 14 01:27:35 PM PDT 24 Mar 14 01:27:36 PM PDT 24 153658863 ps
T873 /workspace/coverage/default/34.spi_device_tpm_all.849302863 Mar 14 01:26:49 PM PDT 24 Mar 14 01:27:07 PM PDT 24 17571735598 ps
T874 /workspace/coverage/default/41.spi_device_intercept.2993035079 Mar 14 01:27:08 PM PDT 24 Mar 14 01:27:15 PM PDT 24 1403524890 ps
T875 /workspace/coverage/default/6.spi_device_csb_read.277763967 Mar 14 01:25:04 PM PDT 24 Mar 14 01:25:05 PM PDT 24 29244927 ps
T80 /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2858188047 Mar 14 01:25:40 PM PDT 24 Mar 14 01:31:14 PM PDT 24 174311949185 ps
T876 /workspace/coverage/default/49.spi_device_flash_and_tpm.3234959452 Mar 14 01:27:49 PM PDT 24 Mar 14 01:30:12 PM PDT 24 15462546425 ps
T877 /workspace/coverage/default/11.spi_device_flash_all.1939132528 Mar 14 01:25:27 PM PDT 24 Mar 14 01:25:58 PM PDT 24 9272908019 ps
T878 /workspace/coverage/default/29.spi_device_alert_test.2712379602 Mar 14 01:26:36 PM PDT 24 Mar 14 01:26:37 PM PDT 24 17458819 ps
T879 /workspace/coverage/default/42.spi_device_upload.1736367941 Mar 14 01:27:13 PM PDT 24 Mar 14 01:27:46 PM PDT 24 8790712628 ps
T880 /workspace/coverage/default/10.spi_device_intercept.1293214342 Mar 14 01:25:21 PM PDT 24 Mar 14 01:25:27 PM PDT 24 335102521 ps
T881 /workspace/coverage/default/25.spi_device_stress_all.183777622 Mar 14 01:26:20 PM PDT 24 Mar 14 01:27:46 PM PDT 24 66404877080 ps
T882 /workspace/coverage/default/21.spi_device_read_buffer_direct.1841732597 Mar 14 01:26:04 PM PDT 24 Mar 14 01:26:09 PM PDT 24 1364318737 ps
T883 /workspace/coverage/default/11.spi_device_tpm_sts_read.15347148 Mar 14 01:25:25 PM PDT 24 Mar 14 01:25:27 PM PDT 24 71511172 ps
T218 /workspace/coverage/default/3.spi_device_flash_all.3631212027 Mar 14 01:24:58 PM PDT 24 Mar 14 01:26:24 PM PDT 24 9402780462 ps
T884 /workspace/coverage/default/17.spi_device_flash_mode.357648465 Mar 14 01:25:55 PM PDT 24 Mar 14 01:26:24 PM PDT 24 48925115682 ps
T885 /workspace/coverage/default/40.spi_device_cfg_cmd.1195088936 Mar 14 01:27:03 PM PDT 24 Mar 14 01:27:10 PM PDT 24 1932090984 ps
T886 /workspace/coverage/default/44.spi_device_csb_read.140198712 Mar 14 01:27:18 PM PDT 24 Mar 14 01:27:19 PM PDT 24 18736945 ps
T887 /workspace/coverage/default/3.spi_device_flash_and_tpm.1918835700 Mar 14 01:24:58 PM PDT 24 Mar 14 01:27:50 PM PDT 24 24981700366 ps
T888 /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2631818444 Mar 14 01:26:50 PM PDT 24 Mar 14 01:26:57 PM PDT 24 1248889033 ps
T889 /workspace/coverage/default/13.spi_device_tpm_sts_read.2415668980 Mar 14 01:25:39 PM PDT 24 Mar 14 01:25:41 PM PDT 24 59087644 ps
T890 /workspace/coverage/default/13.spi_device_alert_test.359161124 Mar 14 01:25:38 PM PDT 24 Mar 14 01:25:40 PM PDT 24 15012632 ps
T891 /workspace/coverage/default/2.spi_device_flash_all.1866257828 Mar 14 01:24:55 PM PDT 24 Mar 14 01:25:06 PM PDT 24 3142954116 ps
T892 /workspace/coverage/default/22.spi_device_tpm_rw.1240146613 Mar 14 01:26:07 PM PDT 24 Mar 14 01:26:12 PM PDT 24 830860927 ps
T893 /workspace/coverage/default/10.spi_device_flash_all.67378061 Mar 14 01:25:24 PM PDT 24 Mar 14 01:31:52 PM PDT 24 79730958429 ps
T894 /workspace/coverage/default/34.spi_device_upload.337905441 Mar 14 01:26:51 PM PDT 24 Mar 14 01:26:54 PM PDT 24 45905799 ps
T895 /workspace/coverage/default/22.spi_device_stress_all.4089795388 Mar 14 01:26:07 PM PDT 24 Mar 14 01:26:10 PM PDT 24 315482224 ps
T896 /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2936057190 Mar 14 01:26:20 PM PDT 24 Mar 14 01:26:28 PM PDT 24 10911974513 ps
T897 /workspace/coverage/default/33.spi_device_cfg_cmd.3278593071 Mar 14 01:26:48 PM PDT 24 Mar 14 01:26:52 PM PDT 24 315512847 ps
T898 /workspace/coverage/default/4.spi_device_flash_all.3182908605 Mar 14 01:25:07 PM PDT 24 Mar 14 01:27:47 PM PDT 24 355362820901 ps
T899 /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1320823502 Mar 14 01:27:41 PM PDT 24 Mar 14 01:27:43 PM PDT 24 124390956 ps
T900 /workspace/coverage/default/17.spi_device_flash_and_tpm.1123241240 Mar 14 01:25:50 PM PDT 24 Mar 14 01:30:50 PM PDT 24 140062072973 ps
T901 /workspace/coverage/default/47.spi_device_tpm_rw.3345000617 Mar 14 01:27:36 PM PDT 24 Mar 14 01:27:37 PM PDT 24 75653622 ps
T902 /workspace/coverage/default/11.spi_device_stress_all.3947426782 Mar 14 01:25:27 PM PDT 24 Mar 14 01:26:34 PM PDT 24 81790692585 ps
T903 /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3827276324 Mar 14 01:27:49 PM PDT 24 Mar 14 01:27:55 PM PDT 24 1583815472 ps
T904 /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3673962471 Mar 14 01:25:59 PM PDT 24 Mar 14 01:26:02 PM PDT 24 190009021 ps
T905 /workspace/coverage/default/39.spi_device_flash_and_tpm.2738735717 Mar 14 01:27:03 PM PDT 24 Mar 14 01:27:39 PM PDT 24 28603530495 ps
T906 /workspace/coverage/default/27.spi_device_tpm_sts_read.1531634197 Mar 14 01:26:24 PM PDT 24 Mar 14 01:26:25 PM PDT 24 78186383 ps
T907 /workspace/coverage/default/5.spi_device_mailbox.2036327106 Mar 14 01:24:58 PM PDT 24 Mar 14 01:25:11 PM PDT 24 5539170282 ps
T908 /workspace/coverage/default/31.spi_device_cfg_cmd.497069017 Mar 14 01:26:39 PM PDT 24 Mar 14 01:26:46 PM PDT 24 16233889560 ps
T909 /workspace/coverage/default/11.spi_device_alert_test.3383875301 Mar 14 01:25:25 PM PDT 24 Mar 14 01:25:25 PM PDT 24 42876010 ps
T92 /workspace/coverage/default/39.spi_device_tpm_all.84379714 Mar 14 01:27:10 PM PDT 24 Mar 14 01:27:24 PM PDT 24 7379419765 ps
T910 /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3789729255 Mar 14 01:25:40 PM PDT 24 Mar 14 01:25:45 PM PDT 24 4615722511 ps
T911 /workspace/coverage/default/16.spi_device_intercept.1401193927 Mar 14 01:25:37 PM PDT 24 Mar 14 01:25:45 PM PDT 24 900498099 ps
T912 /workspace/coverage/default/28.spi_device_tpm_all.1310654472 Mar 14 01:26:22 PM PDT 24 Mar 14 01:27:06 PM PDT 24 16521049407 ps
T913 /workspace/coverage/default/29.spi_device_mailbox.3763659226 Mar 14 01:26:35 PM PDT 24 Mar 14 01:26:47 PM PDT 24 696920191 ps
T914 /workspace/coverage/default/21.spi_device_cfg_cmd.1913841272 Mar 14 01:26:04 PM PDT 24 Mar 14 01:26:09 PM PDT 24 385017235 ps
T915 /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4058467424 Mar 14 01:25:37 PM PDT 24 Mar 14 01:25:47 PM PDT 24 1461198187 ps
T916 /workspace/coverage/default/40.spi_device_csb_read.4026839776 Mar 14 01:26:58 PM PDT 24 Mar 14 01:26:59 PM PDT 24 31943441 ps
T917 /workspace/coverage/default/4.spi_device_mem_parity.4236446535 Mar 14 01:25:01 PM PDT 24 Mar 14 01:25:03 PM PDT 24 94260587 ps
T918 /workspace/coverage/default/26.spi_device_mailbox.1416859959 Mar 14 01:26:22 PM PDT 24 Mar 14 01:27:17 PM PDT 24 43072273738 ps
T919 /workspace/coverage/default/16.spi_device_stress_all.542296861 Mar 14 01:25:46 PM PDT 24 Mar 14 01:25:47 PM PDT 24 182387099 ps
T920 /workspace/coverage/default/37.spi_device_tpm_rw.526351194 Mar 14 01:27:03 PM PDT 24 Mar 14 01:27:06 PM PDT 24 206460610 ps
T921 /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2760007575 Mar 14 01:25:05 PM PDT 24 Mar 14 01:25:19 PM PDT 24 3794427632 ps
T922 /workspace/coverage/default/23.spi_device_tpm_all.1912024934 Mar 14 01:26:06 PM PDT 24 Mar 14 01:26:40 PM PDT 24 132116254827 ps
T923 /workspace/coverage/default/19.spi_device_flash_and_tpm.1973911969 Mar 14 01:25:51 PM PDT 24 Mar 14 01:30:20 PM PDT 24 54396884980 ps
T924 /workspace/coverage/default/48.spi_device_mailbox.3794121901 Mar 14 01:27:43 PM PDT 24 Mar 14 01:27:52 PM PDT 24 4825799796 ps
T925 /workspace/coverage/default/12.spi_device_alert_test.2544134897 Mar 14 01:25:38 PM PDT 24 Mar 14 01:25:40 PM PDT 24 12625137 ps
T926 /workspace/coverage/default/34.spi_device_alert_test.4077118686 Mar 14 01:26:49 PM PDT 24 Mar 14 01:26:50 PM PDT 24 43976440 ps
T927 /workspace/coverage/default/20.spi_device_tpm_rw.2440705535 Mar 14 01:26:03 PM PDT 24 Mar 14 01:26:05 PM PDT 24 88852764 ps
T928 /workspace/coverage/default/44.spi_device_flash_and_tpm.2978974902 Mar 14 01:27:15 PM PDT 24 Mar 14 01:31:43 PM PDT 24 30531088532 ps
T929 /workspace/coverage/default/31.spi_device_tpm_sts_read.565901625 Mar 14 01:26:38 PM PDT 24 Mar 14 01:26:39 PM PDT 24 71989341 ps
T930 /workspace/coverage/default/6.spi_device_tpm_rw.3935578040 Mar 14 01:25:02 PM PDT 24 Mar 14 01:25:04 PM PDT 24 48022800 ps
T931 /workspace/coverage/default/4.spi_device_alert_test.650072760 Mar 14 01:25:03 PM PDT 24 Mar 14 01:25:04 PM PDT 24 14084945 ps
T932 /workspace/coverage/default/0.spi_device_tpm_sts_read.2138335411 Mar 14 01:24:49 PM PDT 24 Mar 14 01:24:50 PM PDT 24 105130099 ps
T933 /workspace/coverage/default/26.spi_device_tpm_sts_read.1529720284 Mar 14 01:26:21 PM PDT 24 Mar 14 01:26:23 PM PDT 24 246299385 ps
T934 /workspace/coverage/default/11.spi_device_mailbox.214826333 Mar 14 01:25:28 PM PDT 24 Mar 14 01:25:40 PM PDT 24 12799889533 ps
T935 /workspace/coverage/default/45.spi_device_upload.2003328345 Mar 14 01:27:32 PM PDT 24 Mar 14 01:27:40 PM PDT 24 1513130405 ps
T936 /workspace/coverage/default/7.spi_device_intercept.1285720507 Mar 14 01:25:21 PM PDT 24 Mar 14 01:25:25 PM PDT 24 6635147092 ps
T937 /workspace/coverage/default/14.spi_device_flash_and_tpm.3982301005 Mar 14 01:25:41 PM PDT 24 Mar 14 01:31:18 PM PDT 24 131871777464 ps
T938 /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.781663662 Mar 14 01:26:21 PM PDT 24 Mar 14 01:26:25 PM PDT 24 452605759 ps
T939 /workspace/coverage/default/27.spi_device_cfg_cmd.147242287 Mar 14 01:26:24 PM PDT 24 Mar 14 01:26:29 PM PDT 24 784267737 ps

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1967968261
Short name T20
Test name
Test status
Simulation time 6146541900 ps
CPU time 40.35 seconds
Started Mar 14 01:26:23 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 240784 kb
Host smart-49b60665-52e2-4d88-897e-346b210852d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967968261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1967968261
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.4086276148
Short name T34
Test name
Test status
Simulation time 38161630164 ps
CPU time 302.2 seconds
Started Mar 14 01:25:54 PM PDT 24
Finished Mar 14 01:30:57 PM PDT 24
Peak memory 256316 kb
Host smart-f305c32e-b944-4524-9d6a-961fb1b315e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086276148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4086276148
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.280494204
Short name T53
Test name
Test status
Simulation time 10786930818 ps
CPU time 52.13 seconds
Started Mar 14 01:27:14 PM PDT 24
Finished Mar 14 01:28:06 PM PDT 24
Peak memory 243556 kb
Host smart-6283cd7c-1cc5-4f05-9d2a-e440379516c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280494204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.280494204
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2088483798
Short name T3
Test name
Test status
Simulation time 435972846472 ps
CPU time 710.16 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:38:25 PM PDT 24
Peak memory 281548 kb
Host smart-e8fce2cc-d59c-4de3-ae4f-e5a30149dcf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088483798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2088483798
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.452091657
Short name T5
Test name
Test status
Simulation time 188782981032 ps
CPU time 824.84 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:41:37 PM PDT 24
Peak memory 297816 kb
Host smart-ad692edc-ce0f-4798-b663-099e80d2a6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452091657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.452091657
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1900703658
Short name T56
Test name
Test status
Simulation time 33122569636 ps
CPU time 205.31 seconds
Started Mar 14 01:27:34 PM PDT 24
Finished Mar 14 01:30:59 PM PDT 24
Peak memory 250988 kb
Host smart-5a11e4bb-6d6f-4374-a2ec-26a32666a04a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900703658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1900703658
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3161098776
Short name T58
Test name
Test status
Simulation time 42028136 ps
CPU time 0.74 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:24:50 PM PDT 24
Peak memory 215844 kb
Host smart-118de396-6cab-4457-ac6a-1a02ddbe1c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161098776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3161098776
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2817502537
Short name T45
Test name
Test status
Simulation time 37519615202 ps
CPU time 86.76 seconds
Started Mar 14 01:25:45 PM PDT 24
Finished Mar 14 01:27:13 PM PDT 24
Peak memory 261336 kb
Host smart-d2591d27-b676-4097-8840-cdfcfdbd3640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817502537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2817502537
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3085539243
Short name T61
Test name
Test status
Simulation time 108177319 ps
CPU time 1.18 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:52 PM PDT 24
Peak memory 235256 kb
Host smart-18a97ab9-f892-4d02-a175-37e4acaed12a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085539243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3085539243
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3117493978
Short name T135
Test name
Test status
Simulation time 87336068021 ps
CPU time 372.05 seconds
Started Mar 14 01:26:34 PM PDT 24
Finished Mar 14 01:32:46 PM PDT 24
Peak memory 265184 kb
Host smart-7325937a-da0c-4afa-8571-22212d950a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117493978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3117493978
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3039407215
Short name T106
Test name
Test status
Simulation time 71489387279 ps
CPU time 404.8 seconds
Started Mar 14 01:26:00 PM PDT 24
Finished Mar 14 01:32:45 PM PDT 24
Peak memory 273424 kb
Host smart-d2084a38-5f13-485e-9aa2-8d02e497a6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039407215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3039407215
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3086987618
Short name T162
Test name
Test status
Simulation time 94958000482 ps
CPU time 642.12 seconds
Started Mar 14 01:26:56 PM PDT 24
Finished Mar 14 01:37:38 PM PDT 24
Peak memory 286560 kb
Host smart-44af7497-78fc-46f2-ab3f-044ddaac11d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086987618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3086987618
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2299047429
Short name T26
Test name
Test status
Simulation time 45206157 ps
CPU time 1.02 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:40 PM PDT 24
Peak memory 217712 kb
Host smart-0401f97e-c85b-4164-825f-3477aef3ae06
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299047429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2299047429
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3049837513
Short name T77
Test name
Test status
Simulation time 117114791562 ps
CPU time 454.64 seconds
Started Mar 14 01:27:00 PM PDT 24
Finished Mar 14 01:34:35 PM PDT 24
Peak memory 254668 kb
Host smart-e2b50556-0a30-4c91-a88c-856142781856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049837513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3049837513
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4126143187
Short name T2
Test name
Test status
Simulation time 310969533015 ps
CPU time 232.3 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 252648 kb
Host smart-2a7c82a7-b734-4a9f-aee4-9ab2bbded46e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126143187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4126143187
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1781859624
Short name T203
Test name
Test status
Simulation time 952959272271 ps
CPU time 1288.16 seconds
Started Mar 14 01:27:43 PM PDT 24
Finished Mar 14 01:49:11 PM PDT 24
Peak memory 301060 kb
Host smart-e4fa71e1-dc81-48f2-8e9b-4443c30f05f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781859624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1781859624
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3654447254
Short name T47
Test name
Test status
Simulation time 1243418795 ps
CPU time 29.65 seconds
Started Mar 14 01:24:53 PM PDT 24
Finished Mar 14 01:25:23 PM PDT 24
Peak memory 250376 kb
Host smart-c8041a5e-560a-4328-80a5-a83ee688bc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654447254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3654447254
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.950773453
Short name T136
Test name
Test status
Simulation time 46989387905 ps
CPU time 467.85 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:33:41 PM PDT 24
Peak memory 289776 kb
Host smart-ef2e61aa-1216-4d1d-a8b7-477ccc2d35a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950773453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.950773453
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2885185383
Short name T7
Test name
Test status
Simulation time 65227970847 ps
CPU time 418.18 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 266252 kb
Host smart-ac79983b-a4e1-4028-8729-1fcd19d9262d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885185383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2885185383
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3723693577
Short name T255
Test name
Test status
Simulation time 51951225 ps
CPU time 0.71 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 204428 kb
Host smart-4403c493-b0fa-4cd7-bf27-f62f9a657607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723693577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3723693577
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3564169019
Short name T190
Test name
Test status
Simulation time 123118575690 ps
CPU time 217.08 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:28:59 PM PDT 24
Peak memory 265160 kb
Host smart-d31dcffb-4825-4589-9923-6994638a113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564169019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3564169019
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3663688302
Short name T33
Test name
Test status
Simulation time 3881419616 ps
CPU time 13.65 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:49 PM PDT 24
Peak memory 215952 kb
Host smart-00996a9c-801b-4c57-ad9f-625b095f771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663688302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3663688302
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3543066270
Short name T107
Test name
Test status
Simulation time 82287310002 ps
CPU time 612.89 seconds
Started Mar 14 01:26:50 PM PDT 24
Finished Mar 14 01:37:03 PM PDT 24
Peak memory 281468 kb
Host smart-dff4e0cb-248d-487e-a4e1-eb6870cd6356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543066270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3543066270
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3199301145
Short name T119
Test name
Test status
Simulation time 150275172607 ps
CPU time 276.74 seconds
Started Mar 14 01:27:18 PM PDT 24
Finished Mar 14 01:31:56 PM PDT 24
Peak memory 254964 kb
Host smart-8755cdce-492b-4c1b-9a15-ee6fbf385765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199301145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3199301145
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1691409531
Short name T221
Test name
Test status
Simulation time 23067232427 ps
CPU time 133.15 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:27:54 PM PDT 24
Peak memory 265020 kb
Host smart-e9ce679a-c2fc-434e-8ef3-e0984a587770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691409531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1691409531
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.515608769
Short name T167
Test name
Test status
Simulation time 45296580857 ps
CPU time 330.39 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:31:24 PM PDT 24
Peak memory 264208 kb
Host smart-d13b70d2-50d5-4842-a69b-0723ae7f6fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515608769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.515608769
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2183826628
Short name T90
Test name
Test status
Simulation time 53915058383 ps
CPU time 208.92 seconds
Started Mar 14 01:26:28 PM PDT 24
Finished Mar 14 01:29:57 PM PDT 24
Peak memory 285788 kb
Host smart-ea2248a1-942d-43a0-b2ce-4607ab7e2f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183826628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2183826628
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2949568903
Short name T44
Test name
Test status
Simulation time 7185861103 ps
CPU time 22.29 seconds
Started Mar 14 01:27:14 PM PDT 24
Finished Mar 14 01:27:36 PM PDT 24
Peak memory 239564 kb
Host smart-ebdf815f-aaa2-446e-9799-0494c5f84ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949568903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2949568903
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3225340645
Short name T160
Test name
Test status
Simulation time 3780959428 ps
CPU time 27.33 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:25:15 PM PDT 24
Peak memory 240488 kb
Host smart-a32d8987-c471-4ed3-aab6-ab3924481beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225340645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3225340645
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3367135420
Short name T757
Test name
Test status
Simulation time 520789046136 ps
CPU time 901.71 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:39:49 PM PDT 24
Peak memory 265200 kb
Host smart-29abc775-0772-4613-823a-134c480dca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367135420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3367135420
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2326816153
Short name T120
Test name
Test status
Simulation time 82529955553 ps
CPU time 122.02 seconds
Started Mar 14 01:25:45 PM PDT 24
Finished Mar 14 01:27:48 PM PDT 24
Peak memory 265120 kb
Host smart-3516ec3f-6b9e-47a2-8461-d1d3933afdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326816153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2326816153
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2991329829
Short name T232
Test name
Test status
Simulation time 72273555782 ps
CPU time 196.71 seconds
Started Mar 14 01:24:51 PM PDT 24
Finished Mar 14 01:28:08 PM PDT 24
Peak memory 250684 kb
Host smart-6a1327a0-a149-4e90-8a46-3a1bac0b5d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991329829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2991329829
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3592762638
Short name T454
Test name
Test status
Simulation time 2053168002 ps
CPU time 21.4 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:26:04 PM PDT 24
Peak memory 239856 kb
Host smart-17fc234a-1c10-4c60-976e-dcafa6f55e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592762638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3592762638
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3359882245
Short name T217
Test name
Test status
Simulation time 15452225681 ps
CPU time 191.36 seconds
Started Mar 14 01:24:46 PM PDT 24
Finished Mar 14 01:27:58 PM PDT 24
Peak memory 270188 kb
Host smart-f471bf7c-2f80-4844-a754-a4ae68ad6d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359882245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3359882245
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4184568627
Short name T219
Test name
Test status
Simulation time 13508072763 ps
CPU time 71.08 seconds
Started Mar 14 01:25:57 PM PDT 24
Finished Mar 14 01:27:08 PM PDT 24
Peak memory 256008 kb
Host smart-7c2ed436-a24d-40d7-bee1-62f17e39cfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184568627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4184568627
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2694382954
Short name T23
Test name
Test status
Simulation time 13875165174 ps
CPU time 14.06 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:25:02 PM PDT 24
Peak memory 227896 kb
Host smart-c4212ea2-86c3-4c71-bf7b-34a3674b4a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694382954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2694382954
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3558046297
Short name T38
Test name
Test status
Simulation time 95832699755 ps
CPU time 182.32 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:29:23 PM PDT 24
Peak memory 253028 kb
Host smart-2197f7c7-a8e2-4399-abbc-888389387642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558046297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3558046297
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2181386204
Short name T378
Test name
Test status
Simulation time 37000247 ps
CPU time 0.72 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:48 PM PDT 24
Peak memory 204980 kb
Host smart-30a50285-6b22-45d8-9100-a5edda240c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181386204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
181386204
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.486409932
Short name T593
Test name
Test status
Simulation time 291791895 ps
CPU time 2.96 seconds
Started Mar 14 01:24:54 PM PDT 24
Finished Mar 14 01:24:57 PM PDT 24
Peak memory 216116 kb
Host smart-670831ea-cead-4a1e-b415-f6e13ea5c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486409932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.486409932
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1315804199
Short name T249
Test name
Test status
Simulation time 39105675 ps
CPU time 0.81 seconds
Started Mar 14 01:24:48 PM PDT 24
Finished Mar 14 01:24:49 PM PDT 24
Peak memory 206068 kb
Host smart-42cfc870-3d38-4768-96ce-12fd1312c41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315804199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1315804199
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1331088916
Short name T700
Test name
Test status
Simulation time 26986406314 ps
CPU time 81.73 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:26:09 PM PDT 24
Peak memory 250012 kb
Host smart-5734b77f-2349-4571-b653-945e09831a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331088916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1331088916
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2406788843
Short name T703
Test name
Test status
Simulation time 3855624601 ps
CPU time 5.41 seconds
Started Mar 14 01:24:48 PM PDT 24
Finished Mar 14 01:24:54 PM PDT 24
Peak memory 232628 kb
Host smart-495e6367-d81e-4a0c-97b6-e2b330b8cca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406788843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2406788843
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4148105041
Short name T480
Test name
Test status
Simulation time 2641745303 ps
CPU time 11.98 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:59 PM PDT 24
Peak memory 235796 kb
Host smart-f319a834-9261-4ecf-b540-32664634330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148105041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4148105041
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1074189559
Short name T574
Test name
Test status
Simulation time 161888096 ps
CPU time 1.11 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:24:51 PM PDT 24
Peak memory 216476 kb
Host smart-aa9f6b94-42c4-4178-a994-fb92a551d4ee
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074189559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1074189559
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2139970013
Short name T745
Test name
Test status
Simulation time 406414078 ps
CPU time 3.4 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:50 PM PDT 24
Peak memory 233284 kb
Host smart-fe3e344d-59a9-4ad3-814c-79481ad7e038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139970013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2139970013
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1609623540
Short name T851
Test name
Test status
Simulation time 4242934199 ps
CPU time 7.12 seconds
Started Mar 14 01:24:53 PM PDT 24
Finished Mar 14 01:25:00 PM PDT 24
Peak memory 234220 kb
Host smart-a060b5e2-090a-4b98-a721-81cad86fb630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609623540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1609623540
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2191276773
Short name T724
Test name
Test status
Simulation time 43690617 ps
CPU time 0.74 seconds
Started Mar 14 01:24:46 PM PDT 24
Finished Mar 14 01:24:47 PM PDT 24
Peak memory 215876 kb
Host smart-93809e1c-ccca-46dc-b538-f5b0520536a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191276773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2191276773
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2997053911
Short name T101
Test name
Test status
Simulation time 188801108 ps
CPU time 3.51 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:50 PM PDT 24
Peak memory 218468 kb
Host smart-98938d65-9817-430f-872b-e26c64567bc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2997053911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2997053911
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.277602091
Short name T229
Test name
Test status
Simulation time 255763117123 ps
CPU time 357.09 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:30:44 PM PDT 24
Peak memory 256080 kb
Host smart-1ddc45f5-33f2-40b5-99c7-3906a08dade7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277602091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.277602091
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2288824915
Short name T862
Test name
Test status
Simulation time 3115049182 ps
CPU time 17.01 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:25:05 PM PDT 24
Peak memory 216060 kb
Host smart-65e23b7d-972a-47a5-adea-1628b9bf84ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288824915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2288824915
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3413459942
Short name T488
Test name
Test status
Simulation time 14920214437 ps
CPU time 7.37 seconds
Started Mar 14 01:24:46 PM PDT 24
Finished Mar 14 01:24:54 PM PDT 24
Peak memory 216020 kb
Host smart-705c53b2-a15b-48b6-af91-abed8689c6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413459942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3413459942
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1606953965
Short name T342
Test name
Test status
Simulation time 865011012 ps
CPU time 2.22 seconds
Started Mar 14 01:24:51 PM PDT 24
Finished Mar 14 01:24:53 PM PDT 24
Peak memory 217328 kb
Host smart-7bb0cd47-8859-4cb1-b5e8-dc4d05573b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606953965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1606953965
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2138335411
Short name T932
Test name
Test status
Simulation time 105130099 ps
CPU time 0.97 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:24:50 PM PDT 24
Peak memory 206328 kb
Host smart-23c20c39-9c8d-4be8-9210-763e9165c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138335411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2138335411
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2858414332
Short name T501
Test name
Test status
Simulation time 1089507408 ps
CPU time 4.39 seconds
Started Mar 14 01:24:48 PM PDT 24
Finished Mar 14 01:24:52 PM PDT 24
Peak memory 221228 kb
Host smart-411d65b2-ee99-4f9a-b0d4-ea2028edc285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858414332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2858414332
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3258814861
Short name T634
Test name
Test status
Simulation time 14769665 ps
CPU time 0.8 seconds
Started Mar 14 01:24:56 PM PDT 24
Finished Mar 14 01:24:56 PM PDT 24
Peak memory 204952 kb
Host smart-1ac52570-11fd-4b7f-a6fa-ea203b7707ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258814861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
258814861
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1524052518
Short name T756
Test name
Test status
Simulation time 1709350087 ps
CPU time 7.78 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:24:57 PM PDT 24
Peak memory 218076 kb
Host smart-ea796596-399a-479b-b518-f8e89b4ecbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524052518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1524052518
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2301639384
Short name T776
Test name
Test status
Simulation time 38177576 ps
CPU time 0.81 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:51 PM PDT 24
Peak memory 206084 kb
Host smart-0bd45f1f-3743-4519-9549-6053baf1f0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301639384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2301639384
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3348312683
Short name T503
Test name
Test status
Simulation time 1033313683 ps
CPU time 9.73 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:57 PM PDT 24
Peak memory 236812 kb
Host smart-ff17d6b6-9593-46af-aad9-916803f86f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348312683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3348312683
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2753652114
Short name T782
Test name
Test status
Simulation time 5773171033 ps
CPU time 35.1 seconds
Started Mar 14 01:24:55 PM PDT 24
Finished Mar 14 01:25:30 PM PDT 24
Peak memory 240600 kb
Host smart-0a576ae0-fd4c-4e07-be78-b8ef96bb4282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753652114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2753652114
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4071041942
Short name T422
Test name
Test status
Simulation time 17424504919 ps
CPU time 15.59 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:25:05 PM PDT 24
Peak memory 224140 kb
Host smart-a981f361-6a08-4d0f-a41a-79a47247acc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071041942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4071041942
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2922466571
Short name T142
Test name
Test status
Simulation time 3709504482 ps
CPU time 8.12 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:59 PM PDT 24
Peak memory 220260 kb
Host smart-f7d6e0d0-c42c-45ed-8437-0d7fc6b5cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922466571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2922466571
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2952590942
Short name T855
Test name
Test status
Simulation time 33654400985 ps
CPU time 39.4 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:25:29 PM PDT 24
Peak memory 261244 kb
Host smart-912a83e0-7eeb-41f2-81c9-bfa079caed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952590942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2952590942
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.951555093
Short name T382
Test name
Test status
Simulation time 25760885 ps
CPU time 1.09 seconds
Started Mar 14 01:24:55 PM PDT 24
Finished Mar 14 01:24:56 PM PDT 24
Peak memory 217704 kb
Host smart-7cb6e7b7-8d5e-489b-9af5-e6a3da948214
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951555093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.951555093
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.935426759
Short name T866
Test name
Test status
Simulation time 267271902 ps
CPU time 4.87 seconds
Started Mar 14 01:24:55 PM PDT 24
Finished Mar 14 01:25:00 PM PDT 24
Peak memory 219904 kb
Host smart-01b74a0b-a1a3-452c-9d29-54339559580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935426759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.935426759
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1342825675
Short name T525
Test name
Test status
Simulation time 707960024 ps
CPU time 3.98 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:54 PM PDT 24
Peak memory 222532 kb
Host smart-2d8fbb68-92b2-43bd-8b48-ce429620cacc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1342825675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1342825675
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.637081703
Short name T60
Test name
Test status
Simulation time 35233786 ps
CPU time 0.98 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:24:50 PM PDT 24
Peak memory 234156 kb
Host smart-7bdd2ea6-4f8c-4c58-9cba-024ac6bbda4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637081703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.637081703
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2150956997
Short name T78
Test name
Test status
Simulation time 26208359272 ps
CPU time 307.29 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:29:58 PM PDT 24
Peak memory 273340 kb
Host smart-f93de0d1-c5b9-46e4-ba7b-ce738cddfb2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150956997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2150956997
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2298402103
Short name T265
Test name
Test status
Simulation time 6886290869 ps
CPU time 35.31 seconds
Started Mar 14 01:24:51 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 215972 kb
Host smart-b9e26983-0ede-4da6-94ae-0f6b4396c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298402103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2298402103
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4018184180
Short name T777
Test name
Test status
Simulation time 1501838546 ps
CPU time 5.75 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:56 PM PDT 24
Peak memory 215888 kb
Host smart-703bbc52-75a4-4228-ba59-56fe6d591a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018184180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4018184180
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1090197762
Short name T318
Test name
Test status
Simulation time 194282021 ps
CPU time 2.7 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:50 PM PDT 24
Peak memory 216064 kb
Host smart-3e193077-4931-4dca-8a0a-d8d3c37c3a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090197762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1090197762
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2744154778
Short name T522
Test name
Test status
Simulation time 35337913 ps
CPU time 0.86 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:48 PM PDT 24
Peak memory 205348 kb
Host smart-4b71c20e-c7c2-4dae-a804-c02f88057d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744154778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2744154778
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3954595927
Short name T648
Test name
Test status
Simulation time 15114258208 ps
CPU time 6.65 seconds
Started Mar 14 01:24:48 PM PDT 24
Finished Mar 14 01:24:55 PM PDT 24
Peak memory 217996 kb
Host smart-bf5ced12-8477-4b0d-80ff-3622d059b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954595927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3954595927
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4132591911
Short name T793
Test name
Test status
Simulation time 18071694 ps
CPU time 0.72 seconds
Started Mar 14 01:25:28 PM PDT 24
Finished Mar 14 01:25:29 PM PDT 24
Peak memory 204368 kb
Host smart-4634f094-6b18-4d16-82d0-d3414eda943b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132591911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4132591911
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1652122738
Short name T762
Test name
Test status
Simulation time 2081981406 ps
CPU time 3.75 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:25:28 PM PDT 24
Peak memory 218204 kb
Host smart-737fc0d3-5621-499a-a815-db4ae89e2457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652122738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1652122738
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3946167306
Short name T245
Test name
Test status
Simulation time 37601658 ps
CPU time 0.79 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:24 PM PDT 24
Peak memory 206388 kb
Host smart-977c41cf-5fce-47f9-8909-9bb164b4dc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946167306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3946167306
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.67378061
Short name T893
Test name
Test status
Simulation time 79730958429 ps
CPU time 387.62 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:31:52 PM PDT 24
Peak memory 271872 kb
Host smart-72655b68-3bfb-4537-96be-2176bad494f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67378061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.67378061
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.854603314
Short name T233
Test name
Test status
Simulation time 63139951211 ps
CPU time 177.01 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:28:22 PM PDT 24
Peak memory 258044 kb
Host smart-4f0ef16e-6aab-4d13-b217-b1b7267aed13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854603314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.854603314
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3073311999
Short name T661
Test name
Test status
Simulation time 1216343554 ps
CPU time 17.44 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:39 PM PDT 24
Peak memory 248212 kb
Host smart-272acb66-bac6-4686-8d08-aebda1659a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073311999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3073311999
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1293214342
Short name T880
Test name
Test status
Simulation time 335102521 ps
CPU time 5.41 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 218932 kb
Host smart-10fce642-aa9d-49d7-947d-624a56bf2697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293214342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1293214342
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1361679035
Short name T214
Test name
Test status
Simulation time 3264354714 ps
CPU time 12.38 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:25:36 PM PDT 24
Peak memory 233952 kb
Host smart-37668bbc-7ade-4045-aeb8-08d3e337f932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361679035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1361679035
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.256894839
Short name T828
Test name
Test status
Simulation time 245699734 ps
CPU time 1.12 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 216504 kb
Host smart-25cb6c64-8fca-48f4-b6e1-127aea4a3660
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256894839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.256894839
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1800557168
Short name T133
Test name
Test status
Simulation time 1856143705 ps
CPU time 8.15 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:32 PM PDT 24
Peak memory 233164 kb
Host smart-f1c493e2-0a6d-4361-bd6c-e66d17fdcc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800557168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1800557168
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4159267867
Short name T148
Test name
Test status
Simulation time 4336602270 ps
CPU time 6.05 seconds
Started Mar 14 01:25:20 PM PDT 24
Finished Mar 14 01:25:26 PM PDT 24
Peak memory 224172 kb
Host smart-59ef6bf7-98b2-438d-96f5-e48f9aaaf80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159267867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4159267867
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2411622315
Short name T302
Test name
Test status
Simulation time 30788953 ps
CPU time 0.74 seconds
Started Mar 14 01:25:18 PM PDT 24
Finished Mar 14 01:25:19 PM PDT 24
Peak memory 215916 kb
Host smart-ee79dd37-ba3c-454f-9bfa-a2c401d317bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411622315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2411622315
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1957249037
Short name T645
Test name
Test status
Simulation time 429334358 ps
CPU time 4.35 seconds
Started Mar 14 01:25:22 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 219412 kb
Host smart-f7cafb3f-e3d5-4981-8052-ce4aa009a371
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957249037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1957249037
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3575127296
Short name T8
Test name
Test status
Simulation time 18383816045 ps
CPU time 171.72 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:28:17 PM PDT 24
Peak memory 256960 kb
Host smart-db716dad-0e0f-4d4b-887c-016d11b8f8d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575127296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3575127296
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3753910321
Short name T240
Test name
Test status
Simulation time 8121434442 ps
CPU time 29.65 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:51 PM PDT 24
Peak memory 215948 kb
Host smart-b07e978c-1853-42e9-a442-677bfcfb948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753910321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3753910321
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1597197874
Short name T248
Test name
Test status
Simulation time 9011395238 ps
CPU time 6.82 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:30 PM PDT 24
Peak memory 215880 kb
Host smart-df244aee-e9e9-49a7-836d-caab36feae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597197874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1597197874
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1839528791
Short name T312
Test name
Test status
Simulation time 143390080 ps
CPU time 0.97 seconds
Started Mar 14 01:25:20 PM PDT 24
Finished Mar 14 01:25:21 PM PDT 24
Peak memory 206444 kb
Host smart-2c7502e5-0e73-44d0-8d09-568b01ae36b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839528791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1839528791
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2275000379
Short name T691
Test name
Test status
Simulation time 34231286 ps
CPU time 0.89 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:25:25 PM PDT 24
Peak memory 206324 kb
Host smart-12f31be5-3379-4bc3-8c98-86ce98f15db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275000379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2275000379
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3394728413
Short name T608
Test name
Test status
Simulation time 10555891007 ps
CPU time 11.25 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:33 PM PDT 24
Peak memory 230128 kb
Host smart-adfd9291-b61b-4566-abd7-e078c93e0045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394728413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3394728413
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3383875301
Short name T909
Test name
Test status
Simulation time 42876010 ps
CPU time 0.76 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:25 PM PDT 24
Peak memory 204904 kb
Host smart-01ba1d61-5fbc-42af-afb9-9fb7507ee24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383875301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3383875301
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2807894822
Short name T683
Test name
Test status
Simulation time 196813566 ps
CPU time 2.85 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:28 PM PDT 24
Peak memory 224108 kb
Host smart-ca00f895-3dc3-4316-99af-cffaa04c31db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807894822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2807894822
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1148702476
Short name T246
Test name
Test status
Simulation time 18932818 ps
CPU time 0.84 seconds
Started Mar 14 01:25:26 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 206060 kb
Host smart-122343da-21fe-4d81-afdf-6dc0e1d2c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148702476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1148702476
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1939132528
Short name T877
Test name
Test status
Simulation time 9272908019 ps
CPU time 31.55 seconds
Started Mar 14 01:25:27 PM PDT 24
Finished Mar 14 01:25:58 PM PDT 24
Peak memory 249276 kb
Host smart-f35b2e6a-bb06-4851-b74e-9900bdd18135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939132528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1939132528
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.24901821
Short name T228
Test name
Test status
Simulation time 58682225912 ps
CPU time 179.18 seconds
Started Mar 14 01:25:27 PM PDT 24
Finished Mar 14 01:28:27 PM PDT 24
Peak memory 269976 kb
Host smart-16dcbe3f-c0c3-41ea-8458-bf1722c1e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24901821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.24901821
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1847176171
Short name T659
Test name
Test status
Simulation time 4682819167 ps
CPU time 22.21 seconds
Started Mar 14 01:25:27 PM PDT 24
Finished Mar 14 01:25:49 PM PDT 24
Peak memory 236996 kb
Host smart-64bd8679-b237-44a9-950e-d5f5e52013c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847176171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1847176171
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3261689975
Short name T534
Test name
Test status
Simulation time 357441449 ps
CPU time 4.3 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:30 PM PDT 24
Peak memory 233316 kb
Host smart-4973fd59-c725-4c00-827d-469fb0076c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261689975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3261689975
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.214826333
Short name T934
Test name
Test status
Simulation time 12799889533 ps
CPU time 11.69 seconds
Started Mar 14 01:25:28 PM PDT 24
Finished Mar 14 01:25:40 PM PDT 24
Peak memory 218084 kb
Host smart-acfff757-31ab-4f94-a993-f97362d9b9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214826333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.214826333
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1208862989
Short name T68
Test name
Test status
Simulation time 74311428 ps
CPU time 1.06 seconds
Started Mar 14 01:25:28 PM PDT 24
Finished Mar 14 01:25:29 PM PDT 24
Peak memory 217652 kb
Host smart-6fab8c51-56a9-4313-8867-444d63c10d87
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208862989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1208862989
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3379303672
Short name T322
Test name
Test status
Simulation time 2500982630 ps
CPU time 4.12 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:30 PM PDT 24
Peak memory 232660 kb
Host smart-84e13a64-9eb0-4200-9f51-6fdca62dfe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379303672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3379303672
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2764724145
Short name T725
Test name
Test status
Simulation time 41776781482 ps
CPU time 22.04 seconds
Started Mar 14 01:25:28 PM PDT 24
Finished Mar 14 01:25:50 PM PDT 24
Peak memory 233888 kb
Host smart-58f180dc-61f3-4322-bb02-0dfb847316dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764724145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2764724145
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.4223431083
Short name T654
Test name
Test status
Simulation time 21422417 ps
CPU time 0.77 seconds
Started Mar 14 01:25:26 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 215884 kb
Host smart-c9e35d43-73a9-4f8d-bf1a-1401eb0f0917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223431083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.4223431083
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1925277097
Short name T701
Test name
Test status
Simulation time 393913325 ps
CPU time 3.62 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:28 PM PDT 24
Peak memory 219384 kb
Host smart-8f63d04b-dfdb-4034-9364-05545f3b573b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1925277097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1925277097
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3947426782
Short name T902
Test name
Test status
Simulation time 81790692585 ps
CPU time 66.6 seconds
Started Mar 14 01:25:27 PM PDT 24
Finished Mar 14 01:26:34 PM PDT 24
Peak memory 240560 kb
Host smart-c45d6a43-247c-4919-a9c6-d8a4f50e6c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947426782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3947426782
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2563625939
Short name T433
Test name
Test status
Simulation time 113264617016 ps
CPU time 43.18 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:26:08 PM PDT 24
Peak memory 215932 kb
Host smart-f2f80859-e52d-46a2-baba-cd7c44c68e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563625939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2563625939
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1330451327
Short name T842
Test name
Test status
Simulation time 7213300503 ps
CPU time 16.28 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:38 PM PDT 24
Peak memory 215960 kb
Host smart-c56389c3-6071-45dd-b94c-86ffc53a4215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330451327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1330451327
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3499377674
Short name T257
Test name
Test status
Simulation time 297801357 ps
CPU time 2.18 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:23 PM PDT 24
Peak memory 215884 kb
Host smart-7749dce3-2f13-4e35-a8df-20d464bbbd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499377674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3499377674
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.15347148
Short name T883
Test name
Test status
Simulation time 71511172 ps
CPU time 0.89 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 205280 kb
Host smart-84f3d296-351f-4e21-8777-9b5e25940954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15347148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.15347148
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4192226031
Short name T723
Test name
Test status
Simulation time 15112469425 ps
CPU time 16.28 seconds
Started Mar 14 01:25:28 PM PDT 24
Finished Mar 14 01:25:44 PM PDT 24
Peak memory 230040 kb
Host smart-934af46e-a154-408a-a28e-e0666995cf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192226031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4192226031
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2544134897
Short name T925
Test name
Test status
Simulation time 12625137 ps
CPU time 0.73 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:40 PM PDT 24
Peak memory 205012 kb
Host smart-daa54203-fc57-40b6-a65e-027e2e63bd2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544134897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2544134897
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2067686369
Short name T194
Test name
Test status
Simulation time 38274686 ps
CPU time 2.48 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 233152 kb
Host smart-63afe956-64b9-4088-a55f-414dbfc31154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067686369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2067686369
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1131114740
Short name T72
Test name
Test status
Simulation time 12403995 ps
CPU time 0.73 seconds
Started Mar 14 01:25:35 PM PDT 24
Finished Mar 14 01:25:37 PM PDT 24
Peak memory 205040 kb
Host smart-be034a77-8f33-4d72-87aa-da22c4f44e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131114740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1131114740
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3585458881
Short name T314
Test name
Test status
Simulation time 5367708938 ps
CPU time 43.43 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:26:23 PM PDT 24
Peak memory 253220 kb
Host smart-dfddb801-2b56-4b2f-b839-742f974acf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585458881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3585458881
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3972073266
Short name T843
Test name
Test status
Simulation time 14870660111 ps
CPU time 107.49 seconds
Started Mar 14 01:25:36 PM PDT 24
Finished Mar 14 01:27:25 PM PDT 24
Peak memory 224528 kb
Host smart-f2643e30-56d3-42c6-b5e1-bb7e31644465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972073266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3972073266
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3075014944
Short name T784
Test name
Test status
Simulation time 18047358785 ps
CPU time 83.51 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:27:04 PM PDT 24
Peak memory 257096 kb
Host smart-2275ac83-573c-464e-bb3a-64088fa7dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075014944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3075014944
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.522335937
Short name T517
Test name
Test status
Simulation time 7056713611 ps
CPU time 21.02 seconds
Started Mar 14 01:25:36 PM PDT 24
Finished Mar 14 01:25:57 PM PDT 24
Peak memory 234104 kb
Host smart-e9446181-e772-42f9-8c39-cb48809b5c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522335937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.522335937
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3666645070
Short name T12
Test name
Test status
Simulation time 8135959824 ps
CPU time 6.64 seconds
Started Mar 14 01:25:36 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 219060 kb
Host smart-524f6020-8f29-4580-ae21-4afbbf951e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666645070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3666645070
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3862470937
Short name T179
Test name
Test status
Simulation time 104419764525 ps
CPU time 34.06 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 240432 kb
Host smart-7b51d0a5-2f9a-4fed-871a-368422109944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862470937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3862470937
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3265320950
Short name T330
Test name
Test status
Simulation time 15172738 ps
CPU time 1.11 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 216252 kb
Host smart-6714c16f-109a-4731-bac7-b65104570e44
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265320950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3265320950
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2066219057
Short name T753
Test name
Test status
Simulation time 534800387 ps
CPU time 5.9 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:47 PM PDT 24
Peak memory 217588 kb
Host smart-bd399c1f-e687-458f-bfdb-24570950299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066219057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2066219057
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3427222864
Short name T640
Test name
Test status
Simulation time 259615179 ps
CPU time 2.68 seconds
Started Mar 14 01:25:36 PM PDT 24
Finished Mar 14 01:25:41 PM PDT 24
Peak memory 216524 kb
Host smart-fba01d43-1e4d-4e09-afdb-ba0f5033b7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427222864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3427222864
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.2611218077
Short name T537
Test name
Test status
Simulation time 21179383 ps
CPU time 0.74 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 215808 kb
Host smart-b94f71e1-0941-4f33-a790-239ca1224f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611218077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.2611218077
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2163618872
Short name T397
Test name
Test status
Simulation time 6697386233 ps
CPU time 5.48 seconds
Started Mar 14 01:25:36 PM PDT 24
Finished Mar 14 01:25:43 PM PDT 24
Peak memory 219372 kb
Host smart-bce634d8-0751-4db5-9a03-4654318bf99d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2163618872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2163618872
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.577485582
Short name T736
Test name
Test status
Simulation time 255424101 ps
CPU time 1.16 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 206484 kb
Host smart-4e042fb0-8229-485a-b3f9-d1f870575bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577485582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.577485582
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3952345207
Short name T274
Test name
Test status
Simulation time 2745383370 ps
CPU time 30.11 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:26:10 PM PDT 24
Peak memory 215888 kb
Host smart-6ef17826-fb9a-40e3-9bd9-6fa69b5aa13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952345207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3952345207
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3355212868
Short name T363
Test name
Test status
Simulation time 4079825972 ps
CPU time 13.71 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:25:54 PM PDT 24
Peak memory 215928 kb
Host smart-f3f58d8f-ef92-4568-9898-31ddc040dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355212868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3355212868
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3984571651
Short name T551
Test name
Test status
Simulation time 84090824 ps
CPU time 1.39 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 215788 kb
Host smart-4176f3f0-15bc-4081-ab00-325ee8583374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984571651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3984571651
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3101930845
Short name T464
Test name
Test status
Simulation time 26711900 ps
CPU time 0.81 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:40 PM PDT 24
Peak memory 205284 kb
Host smart-79ae4f9d-8519-4b6f-91f9-507d68fc056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101930845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3101930845
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2135262049
Short name T568
Test name
Test status
Simulation time 876668829 ps
CPU time 4.04 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 218120 kb
Host smart-d156687e-419f-4638-86da-e1d088eb64b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135262049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2135262049
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.359161124
Short name T890
Test name
Test status
Simulation time 15012632 ps
CPU time 0.76 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:40 PM PDT 24
Peak memory 205272 kb
Host smart-3a728d96-288a-4a64-bf30-36b26efdbace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359161124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.359161124
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.458452721
Short name T746
Test name
Test status
Simulation time 152887961 ps
CPU time 2.89 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 232960 kb
Host smart-a36c482c-ac3d-4ec9-b30c-ac988e01a098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458452721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.458452721
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.549100788
Short name T651
Test name
Test status
Simulation time 17652041 ps
CPU time 0.9 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:39 PM PDT 24
Peak memory 205364 kb
Host smart-4da53f94-5e8d-431b-bcfa-18516ccc5b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549100788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.549100788
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2241188594
Short name T796
Test name
Test status
Simulation time 38740242204 ps
CPU time 107.65 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:27:26 PM PDT 24
Peak memory 248736 kb
Host smart-14a2317d-2d01-4694-9b0e-287f2e8c04e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241188594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2241188594
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.929592210
Short name T435
Test name
Test status
Simulation time 28366882219 ps
CPU time 190.46 seconds
Started Mar 14 01:25:35 PM PDT 24
Finished Mar 14 01:28:46 PM PDT 24
Peak memory 239856 kb
Host smart-4f79a5e1-aed9-4115-a7c5-c2321959fcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929592210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.929592210
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3074685571
Short name T331
Test name
Test status
Simulation time 23323800311 ps
CPU time 56.25 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:26:37 PM PDT 24
Peak memory 238884 kb
Host smart-d14c3884-86cf-47df-b7e3-340152f8f31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074685571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3074685571
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1029996678
Short name T764
Test name
Test status
Simulation time 48507292794 ps
CPU time 24.61 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:26:04 PM PDT 24
Peak memory 240476 kb
Host smart-19a9f97a-74ff-4f13-a579-970faa743ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029996678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1029996678
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1028511018
Short name T613
Test name
Test status
Simulation time 1093396169 ps
CPU time 5.54 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:25:48 PM PDT 24
Peak memory 233092 kb
Host smart-5e11c07e-a2d9-4f17-b54d-55215ac39f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028511018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1028511018
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.303317276
Short name T164
Test name
Test status
Simulation time 131765869518 ps
CPU time 29.34 seconds
Started Mar 14 01:25:43 PM PDT 24
Finished Mar 14 01:26:13 PM PDT 24
Peak memory 248216 kb
Host smart-d2e93aba-f873-4f3b-aafc-d4272f28e4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303317276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.303317276
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1812496779
Short name T428
Test name
Test status
Simulation time 106629124 ps
CPU time 1.04 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 217640 kb
Host smart-1a1e0eee-ed8d-4af1-b63d-a01161d2196e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812496779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1812496779
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.701186134
Short name T407
Test name
Test status
Simulation time 10120016426 ps
CPU time 15.29 seconds
Started Mar 14 01:25:35 PM PDT 24
Finished Mar 14 01:25:51 PM PDT 24
Peak memory 233376 kb
Host smart-f2c62b8f-19bb-4c5c-912a-a18d7470c95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701186134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.701186134
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3576349331
Short name T18
Test name
Test status
Simulation time 825751974 ps
CPU time 4.49 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:43 PM PDT 24
Peak memory 232312 kb
Host smart-63eab908-2d1b-43d9-b73b-0c020ca1a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576349331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3576349331
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2536331683
Short name T424
Test name
Test status
Simulation time 17982423 ps
CPU time 0.71 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:41 PM PDT 24
Peak memory 215896 kb
Host smart-aa104ba1-2700-46d3-aecd-b28e1d38377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536331683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2536331683
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1972710999
Short name T717
Test name
Test status
Simulation time 818210592 ps
CPU time 4.39 seconds
Started Mar 14 01:25:36 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 219532 kb
Host smart-0cee9faf-f8f1-491d-89ca-dba0c6c4e0a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1972710999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1972710999
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2494512329
Short name T451
Test name
Test status
Simulation time 2395462721 ps
CPU time 34.98 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:26:16 PM PDT 24
Peak memory 218240 kb
Host smart-138bca9f-dac3-4950-b64e-a07dc62a1e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494512329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2494512329
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3789729255
Short name T910
Test name
Test status
Simulation time 4615722511 ps
CPU time 3.86 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 215984 kb
Host smart-56bdacff-228f-4dbf-a5c6-4a7b4dd01515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789729255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3789729255
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3684069679
Short name T387
Test name
Test status
Simulation time 583800803 ps
CPU time 5.76 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:47 PM PDT 24
Peak memory 215792 kb
Host smart-2798eb00-70e4-418f-9215-ac12381313c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684069679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3684069679
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2415668980
Short name T889
Test name
Test status
Simulation time 59087644 ps
CPU time 0.8 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:25:41 PM PDT 24
Peak memory 205164 kb
Host smart-76da442b-8740-4ba8-b577-6e9ad218fdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415668980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2415668980
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1815649654
Short name T684
Test name
Test status
Simulation time 3818060343 ps
CPU time 14.02 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:53 PM PDT 24
Peak memory 237472 kb
Host smart-49b881db-c2e5-4796-a00f-0ba8a8f4309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815649654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1815649654
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2016637494
Short name T870
Test name
Test status
Simulation time 8990745983 ps
CPU time 5.51 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 234196 kb
Host smart-d956f01c-01b6-4f45-b12a-dcf4dfbfca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016637494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2016637494
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1558989681
Short name T818
Test name
Test status
Simulation time 33624482 ps
CPU time 0.81 seconds
Started Mar 14 01:25:35 PM PDT 24
Finished Mar 14 01:25:36 PM PDT 24
Peak memory 206412 kb
Host smart-f11898b3-60d6-417b-a626-8c9287ca6a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558989681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1558989681
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.457561514
Short name T797
Test name
Test status
Simulation time 29291024125 ps
CPU time 36.38 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:26:16 PM PDT 24
Peak memory 240532 kb
Host smart-a2e68da4-d249-47e4-96cb-47b61b96444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457561514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.457561514
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3982301005
Short name T937
Test name
Test status
Simulation time 131871777464 ps
CPU time 336.53 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:31:18 PM PDT 24
Peak memory 272636 kb
Host smart-166bdf02-09ca-4c6d-aa49-8ca7a51d8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982301005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3982301005
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3938010501
Short name T50
Test name
Test status
Simulation time 15637840796 ps
CPU time 100.38 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:27:22 PM PDT 24
Peak memory 233508 kb
Host smart-85016db6-b483-4400-8795-c819e4d3fbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938010501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3938010501
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1593826441
Short name T854
Test name
Test status
Simulation time 372020552 ps
CPU time 3.68 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:43 PM PDT 24
Peak memory 219024 kb
Host smart-d12c95ef-8797-4bb1-a408-9426dbe77e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593826441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1593826441
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1486421825
Short name T467
Test name
Test status
Simulation time 1471593201 ps
CPU time 7.17 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:46 PM PDT 24
Peak memory 240480 kb
Host smart-837c708b-04fd-4389-b0a1-2ecf38311472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486421825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1486421825
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.176868399
Short name T271
Test name
Test status
Simulation time 76845536 ps
CPU time 1.02 seconds
Started Mar 14 01:25:36 PM PDT 24
Finished Mar 14 01:25:37 PM PDT 24
Peak memory 217728 kb
Host smart-48539803-1600-48d3-bdb4-0562543f92ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176868399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.176868399
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4058467424
Short name T915
Test name
Test status
Simulation time 1461198187 ps
CPU time 8.06 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:47 PM PDT 24
Peak memory 223996 kb
Host smart-217aa26e-61d0-41d6-9243-25321c35c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058467424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4058467424
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1107046885
Short name T601
Test name
Test status
Simulation time 3248112220 ps
CPU time 13.49 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:52 PM PDT 24
Peak memory 232500 kb
Host smart-2136ceb4-9f16-43ca-a569-93ed5ee16cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107046885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1107046885
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2189063738
Short name T531
Test name
Test status
Simulation time 37798695 ps
CPU time 0.77 seconds
Started Mar 14 01:25:36 PM PDT 24
Finished Mar 14 01:25:39 PM PDT 24
Peak memory 215876 kb
Host smart-f5092ce6-5dfe-4522-b68f-5bc3ba56fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189063738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2189063738
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.832739012
Short name T294
Test name
Test status
Simulation time 145917412 ps
CPU time 3.37 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:43 PM PDT 24
Peak memory 218260 kb
Host smart-44e8ed9a-6320-4f22-8f63-78d5e1f0f4b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=832739012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.832739012
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.654530058
Short name T10
Test name
Test status
Simulation time 6330698591 ps
CPU time 31.03 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:26:13 PM PDT 24
Peak memory 233424 kb
Host smart-abdfd9da-ab78-4217-82ea-7011925a22a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654530058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.654530058
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1016817990
Short name T439
Test name
Test status
Simulation time 11212545641 ps
CPU time 34.41 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 215880 kb
Host smart-43a8414f-85a7-47c9-b6e4-496a1aa474df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016817990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1016817990
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2219473981
Short name T392
Test name
Test status
Simulation time 1569215735 ps
CPU time 8.38 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:49 PM PDT 24
Peak memory 215936 kb
Host smart-096b6038-c4a6-4abf-b7c6-79650b2fcdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219473981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2219473981
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3242944547
Short name T544
Test name
Test status
Simulation time 3335013513 ps
CPU time 3.41 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:44 PM PDT 24
Peak memory 216200 kb
Host smart-95198922-ecef-4d0c-9832-2f6682660035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242944547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3242944547
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3495679327
Short name T366
Test name
Test status
Simulation time 184069659 ps
CPU time 0.8 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:40 PM PDT 24
Peak memory 205252 kb
Host smart-e530af7a-2e62-4fcd-9ac1-6ea98be5449a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495679327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3495679327
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3075427263
Short name T158
Test name
Test status
Simulation time 6225395276 ps
CPU time 6.64 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 218316 kb
Host smart-f3cabbf2-03f5-4728-86b3-c8c20cea8bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075427263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3075427263
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3348920482
Short name T646
Test name
Test status
Simulation time 20415301 ps
CPU time 0.71 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 204952 kb
Host smart-574dbc36-7027-4b7f-9cf0-2285ef671520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348920482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3348920482
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.608250594
Short name T826
Test name
Test status
Simulation time 5354652888 ps
CPU time 5.56 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 233456 kb
Host smart-fe234802-4333-4615-bf60-c755ce1fff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608250594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.608250594
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.116576128
Short name T728
Test name
Test status
Simulation time 61425194 ps
CPU time 0.78 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 205332 kb
Host smart-6fa3d168-719f-4d51-acc8-247e32f60874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116576128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.116576128
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2858188047
Short name T80
Test name
Test status
Simulation time 174311949185 ps
CPU time 332.83 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:31:14 PM PDT 24
Peak memory 265656 kb
Host smart-8ebcbb51-ee27-4343-9e9c-0350b8e27a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858188047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2858188047
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3937884324
Short name T452
Test name
Test status
Simulation time 2758794802 ps
CPU time 13.07 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:25:54 PM PDT 24
Peak memory 251344 kb
Host smart-ce9c5b62-19e6-4b05-a94d-ae5690008a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937884324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3937884324
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2189581616
Short name T610
Test name
Test status
Simulation time 1726184472 ps
CPU time 7.12 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:49 PM PDT 24
Peak memory 224120 kb
Host smart-a63e7d43-8fdf-496d-a1df-49e23417d9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189581616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2189581616
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2021381449
Short name T627
Test name
Test status
Simulation time 128440016 ps
CPU time 2.5 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:44 PM PDT 24
Peak memory 216412 kb
Host smart-b79afddc-416d-4d38-b057-897be853d70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021381449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2021381449
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1434413264
Short name T472
Test name
Test status
Simulation time 98574045 ps
CPU time 1.1 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:39 PM PDT 24
Peak memory 217736 kb
Host smart-48443b10-48cb-47b3-a91f-f8ee71bdae5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434413264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1434413264
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1740545986
Short name T741
Test name
Test status
Simulation time 4583584415 ps
CPU time 7.2 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:25:49 PM PDT 24
Peak memory 223988 kb
Host smart-20a1a735-9043-4e9b-9bff-32edc72301c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740545986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1740545986
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4181574536
Short name T362
Test name
Test status
Simulation time 72040792 ps
CPU time 2.37 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:43 PM PDT 24
Peak memory 232304 kb
Host smart-d9f02f5a-3bbd-49a7-922d-245508e84986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181574536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4181574536
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.1721128955
Short name T831
Test name
Test status
Simulation time 50693852 ps
CPU time 0.78 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:39 PM PDT 24
Peak memory 215904 kb
Host smart-c09f2c84-944a-4156-b988-dc71c0f9f241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721128955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.1721128955
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.756207511
Short name T432
Test name
Test status
Simulation time 116986769 ps
CPU time 3.97 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 222408 kb
Host smart-bd043d82-3fd3-4829-83b7-6ffb441efde2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=756207511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.756207511
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1684059186
Short name T9
Test name
Test status
Simulation time 73581711731 ps
CPU time 269.79 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:30:08 PM PDT 24
Peak memory 248728 kb
Host smart-aac993eb-81c7-4bd3-9111-9470de4b36df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684059186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1684059186
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4219092986
Short name T635
Test name
Test status
Simulation time 1253621403 ps
CPU time 16.85 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:58 PM PDT 24
Peak memory 215824 kb
Host smart-84f59e87-2498-4915-83d1-9ba1476631a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219092986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4219092986
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4111110573
Short name T650
Test name
Test status
Simulation time 4004740093 ps
CPU time 16.29 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:25:59 PM PDT 24
Peak memory 215964 kb
Host smart-0b92d909-aac7-4e74-a8f5-7308aa78fc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111110573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4111110573
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.228413616
Short name T514
Test name
Test status
Simulation time 1358856778 ps
CPU time 12.37 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 216020 kb
Host smart-06ccd118-ed4c-4103-8ff9-e5034f9c1afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228413616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.228413616
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.198522023
Short name T505
Test name
Test status
Simulation time 29771914 ps
CPU time 0.79 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:25:41 PM PDT 24
Peak memory 205284 kb
Host smart-f9aefdbf-2b14-4156-9b0e-4ba1b66c297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198522023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.198522023
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1373442534
Short name T396
Test name
Test status
Simulation time 9285237938 ps
CPU time 17.55 seconds
Started Mar 14 01:25:45 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 240504 kb
Host smart-2d594482-581a-4a0c-b8ea-8f01b4c00a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373442534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1373442534
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3883764078
Short name T510
Test name
Test status
Simulation time 15884282 ps
CPU time 0.72 seconds
Started Mar 14 01:25:45 PM PDT 24
Finished Mar 14 01:25:46 PM PDT 24
Peak memory 204944 kb
Host smart-7066e5af-407e-444d-aae4-cf020234b34e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883764078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3883764078
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1627796606
Short name T183
Test name
Test status
Simulation time 6957174108 ps
CPU time 7.02 seconds
Started Mar 14 01:25:46 PM PDT 24
Finished Mar 14 01:25:53 PM PDT 24
Peak memory 219456 kb
Host smart-cc91bc71-a8c1-46ac-9e06-4db569b3ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627796606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1627796606
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2648574504
Short name T415
Test name
Test status
Simulation time 45891465 ps
CPU time 0.78 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:25:41 PM PDT 24
Peak memory 204964 kb
Host smart-5fb482e8-d71f-4ed8-b6b1-f76d8ef21a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648574504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2648574504
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1319674490
Short name T666
Test name
Test status
Simulation time 110196502730 ps
CPU time 62.5 seconds
Started Mar 14 01:25:43 PM PDT 24
Finished Mar 14 01:26:46 PM PDT 24
Peak memory 249228 kb
Host smart-26628705-cffe-4ae1-8d62-aeeaf9308fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319674490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1319674490
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.415312826
Short name T827
Test name
Test status
Simulation time 92170343182 ps
CPU time 159.39 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:28:20 PM PDT 24
Peak memory 264380 kb
Host smart-7282f1cf-1071-4356-9074-944d54df8bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415312826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.415312826
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1498034677
Short name T170
Test name
Test status
Simulation time 5005210964 ps
CPU time 44.58 seconds
Started Mar 14 01:25:47 PM PDT 24
Finished Mar 14 01:26:32 PM PDT 24
Peak memory 256224 kb
Host smart-aad29a7b-5184-462a-a0f7-e9a2b34c01b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498034677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1498034677
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.70622116
Short name T340
Test name
Test status
Simulation time 6885894954 ps
CPU time 37.15 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:26:19 PM PDT 24
Peak memory 240448 kb
Host smart-7c0ba4f4-7377-49fe-ad69-de4448cb97b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70622116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.70622116
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1401193927
Short name T911
Test name
Test status
Simulation time 900498099 ps
CPU time 5.7 seconds
Started Mar 14 01:25:37 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 224060 kb
Host smart-964d78d4-afb0-489c-8ce8-3ed6286a92c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401193927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1401193927
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4065264580
Short name T696
Test name
Test status
Simulation time 49551961143 ps
CPU time 21.41 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 216548 kb
Host smart-97d049ed-382d-418e-9ec7-697c41ecadd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065264580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4065264580
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1109514436
Short name T540
Test name
Test status
Simulation time 6871118293 ps
CPU time 10.24 seconds
Started Mar 14 01:25:45 PM PDT 24
Finished Mar 14 01:25:56 PM PDT 24
Peak memory 224104 kb
Host smart-89ee4b91-c846-48cd-8800-525e36168677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109514436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1109514436
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1303011539
Short name T102
Test name
Test status
Simulation time 1587811907 ps
CPU time 9.2 seconds
Started Mar 14 01:25:45 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 216576 kb
Host smart-25c27a27-51f9-4d03-b4c5-2ec446cafd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303011539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1303011539
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.4161489259
Short name T442
Test name
Test status
Simulation time 19059625 ps
CPU time 0.75 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 215888 kb
Host smart-457b9327-4c16-41e1-aa47-68b61691a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161489259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.4161489259
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1335863743
Short name T486
Test name
Test status
Simulation time 1288000030 ps
CPU time 5.12 seconds
Started Mar 14 01:25:44 PM PDT 24
Finished Mar 14 01:25:50 PM PDT 24
Peak memory 221800 kb
Host smart-27e14bbe-4e30-426c-9d10-3cede20f03d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1335863743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1335863743
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.542296861
Short name T919
Test name
Test status
Simulation time 182387099 ps
CPU time 0.98 seconds
Started Mar 14 01:25:46 PM PDT 24
Finished Mar 14 01:25:47 PM PDT 24
Peak memory 206296 kb
Host smart-ab3d59c6-abaf-4e9c-a059-10ea13e3cbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542296861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.542296861
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3352230021
Short name T260
Test name
Test status
Simulation time 11429833533 ps
CPU time 14.85 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:25:57 PM PDT 24
Peak memory 215956 kb
Host smart-92740add-8817-4ac6-aa5f-cce7e62cd1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352230021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3352230021
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.411187636
Short name T25
Test name
Test status
Simulation time 742324676 ps
CPU time 2.59 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:44 PM PDT 24
Peak memory 215652 kb
Host smart-efc710de-519d-433e-b59e-1086cf1a9f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411187636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.411187636
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2477942662
Short name T731
Test name
Test status
Simulation time 641575643 ps
CPU time 2.04 seconds
Started Mar 14 01:25:45 PM PDT 24
Finished Mar 14 01:25:48 PM PDT 24
Peak memory 215816 kb
Host smart-b0ec90b6-f190-4a0d-9e6a-315f6185733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477942662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2477942662
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.246490273
Short name T638
Test name
Test status
Simulation time 133193316 ps
CPU time 1.15 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:25:43 PM PDT 24
Peak memory 206296 kb
Host smart-fee31f9f-27b1-4c4f-bd6d-680553c2a3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246490273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.246490273
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4195287212
Short name T310
Test name
Test status
Simulation time 713920096 ps
CPU time 5.12 seconds
Started Mar 14 01:25:43 PM PDT 24
Finished Mar 14 01:25:49 PM PDT 24
Peak memory 219116 kb
Host smart-26741eea-3f3d-415c-ac44-205c8cb45ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195287212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4195287212
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.713118573
Short name T539
Test name
Test status
Simulation time 75172065 ps
CPU time 0.71 seconds
Started Mar 14 01:25:54 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 204396 kb
Host smart-7352d00e-abd2-4983-b5bf-1bc6bf40d50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713118573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.713118573
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1268620585
Short name T845
Test name
Test status
Simulation time 160374176 ps
CPU time 2.24 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:25:57 PM PDT 24
Peak memory 218040 kb
Host smart-2ba68937-1cb2-40f7-97af-d9d60a899fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268620585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1268620585
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1530761709
Short name T677
Test name
Test status
Simulation time 16199930 ps
CPU time 0.76 seconds
Started Mar 14 01:25:46 PM PDT 24
Finished Mar 14 01:25:47 PM PDT 24
Peak memory 206020 kb
Host smart-cfa77c09-4ba2-44cd-928d-ea1bba08d311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530761709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1530761709
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1892830129
Short name T116
Test name
Test status
Simulation time 28909139147 ps
CPU time 143.55 seconds
Started Mar 14 01:25:50 PM PDT 24
Finished Mar 14 01:28:14 PM PDT 24
Peak memory 268940 kb
Host smart-af3afa07-5c75-4279-a4dd-ae023921b2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892830129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1892830129
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1123241240
Short name T900
Test name
Test status
Simulation time 140062072973 ps
CPU time 300.51 seconds
Started Mar 14 01:25:50 PM PDT 24
Finished Mar 14 01:30:50 PM PDT 24
Peak memory 272136 kb
Host smart-9b48be02-ae58-47f7-9384-bb8267dfb76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123241240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1123241240
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3489298771
Short name T157
Test name
Test status
Simulation time 236483213737 ps
CPU time 302.8 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:30:56 PM PDT 24
Peak memory 256976 kb
Host smart-9a6b1764-6b0a-4f38-b909-952b93b13b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489298771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3489298771
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.357648465
Short name T884
Test name
Test status
Simulation time 48925115682 ps
CPU time 28.76 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 245600 kb
Host smart-d1a76989-eb21-4dd3-ae5a-87b6593785ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357648465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.357648465
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.792191596
Short name T131
Test name
Test status
Simulation time 177231291 ps
CPU time 3.78 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:25:57 PM PDT 24
Peak memory 233060 kb
Host smart-dc73b981-e24b-4104-b2d5-80c5a55656ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792191596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.792191596
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3832249871
Short name T207
Test name
Test status
Simulation time 1022869012 ps
CPU time 9.31 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:26:01 PM PDT 24
Peak memory 240416 kb
Host smart-3687da96-d50c-465f-965c-914fde31585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832249871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3832249871
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4245785866
Short name T41
Test name
Test status
Simulation time 32112112 ps
CPU time 1.15 seconds
Started Mar 14 01:25:47 PM PDT 24
Finished Mar 14 01:25:49 PM PDT 24
Peak memory 216436 kb
Host smart-ab1bab26-8ca9-4789-aaae-fa8c4ca08c8a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245785866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4245785866
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3862380216
Short name T21
Test name
Test status
Simulation time 478264945 ps
CPU time 5.15 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:46 PM PDT 24
Peak memory 234104 kb
Host smart-a1a9836a-3fdb-42ff-a1c9-187c284b55e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862380216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3862380216
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.207258935
Short name T348
Test name
Test status
Simulation time 320427451 ps
CPU time 4.38 seconds
Started Mar 14 01:25:40 PM PDT 24
Finished Mar 14 01:25:45 PM PDT 24
Peak memory 224000 kb
Host smart-36c0cee4-6985-47ab-8104-dc13c2c4826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207258935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.207258935
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.578152077
Short name T309
Test name
Test status
Simulation time 17674374 ps
CPU time 0.75 seconds
Started Mar 14 01:25:46 PM PDT 24
Finished Mar 14 01:25:47 PM PDT 24
Peak memory 215876 kb
Host smart-dbec16c6-ac1e-4fd3-abd5-c92a401b493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578152077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.578152077
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1821040448
Short name T268
Test name
Test status
Simulation time 85900642 ps
CPU time 3.53 seconds
Started Mar 14 01:25:51 PM PDT 24
Finished Mar 14 01:25:54 PM PDT 24
Peak memory 222296 kb
Host smart-cf6b4153-d4c1-44d2-9435-32ca091468c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1821040448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1821040448
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3975277825
Short name T288
Test name
Test status
Simulation time 41021170251 ps
CPU time 58.16 seconds
Started Mar 14 01:25:42 PM PDT 24
Finished Mar 14 01:26:41 PM PDT 24
Peak memory 215948 kb
Host smart-f36ebeaa-a35d-4c02-9957-15029fa8fe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975277825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3975277825
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2445835847
Short name T545
Test name
Test status
Simulation time 963459594 ps
CPU time 2.14 seconds
Started Mar 14 01:25:38 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 207384 kb
Host smart-4d7b1656-9206-4006-90eb-90b1256a182c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445835847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2445835847
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1070818641
Short name T272
Test name
Test status
Simulation time 68845976 ps
CPU time 3.72 seconds
Started Mar 14 01:25:39 PM PDT 24
Finished Mar 14 01:25:44 PM PDT 24
Peak memory 216072 kb
Host smart-db1fbae2-859b-4474-88ab-0785d2e7f329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070818641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1070818641
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2959700533
Short name T679
Test name
Test status
Simulation time 66629522 ps
CPU time 1.03 seconds
Started Mar 14 01:25:41 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 206140 kb
Host smart-2cead09a-3ce1-426b-8f68-656e846b32b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959700533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2959700533
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1213044817
Short name T421
Test name
Test status
Simulation time 302364392 ps
CPU time 3.96 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:25:56 PM PDT 24
Peak memory 232872 kb
Host smart-e2487c3a-8f14-458a-b1a2-33c542dbea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213044817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1213044817
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2232733463
Short name T372
Test name
Test status
Simulation time 12343560 ps
CPU time 0.73 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:25:54 PM PDT 24
Peak memory 204364 kb
Host smart-3c5d156c-20ab-4c8e-8808-f8bc27729bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232733463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2232733463
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.342050782
Short name T716
Test name
Test status
Simulation time 107814425 ps
CPU time 2.74 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 233560 kb
Host smart-9202917b-2e5f-4c76-acf4-42f958d9d764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342050782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.342050782
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1275917911
Short name T509
Test name
Test status
Simulation time 20469683 ps
CPU time 0.8 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:25:54 PM PDT 24
Peak memory 205324 kb
Host smart-4e51aa26-5fa9-4606-9de3-13c6eaaa26e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275917911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1275917911
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1461763728
Short name T172
Test name
Test status
Simulation time 876545927763 ps
CPU time 590.3 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:35:44 PM PDT 24
Peak memory 265168 kb
Host smart-d2c7ade7-77ac-483e-8d95-cd732f77c3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461763728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1461763728
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.908349233
Short name T138
Test name
Test status
Simulation time 906110280334 ps
CPU time 404.41 seconds
Started Mar 14 01:25:50 PM PDT 24
Finished Mar 14 01:32:35 PM PDT 24
Peak memory 263724 kb
Host smart-909f321b-87c5-4954-94ad-8d8a12c1aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908349233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.908349233
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4018226781
Short name T334
Test name
Test status
Simulation time 438194181 ps
CPU time 7.69 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:26:01 PM PDT 24
Peak memory 235096 kb
Host smart-4aee65ed-f700-40a4-a1c7-925fc531daea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018226781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4018226781
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2204214229
Short name T269
Test name
Test status
Simulation time 777129264 ps
CPU time 2.8 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 224072 kb
Host smart-d0dc18fe-65ba-4f6f-9548-04967d870c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204214229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2204214229
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2365263100
Short name T182
Test name
Test status
Simulation time 290875742 ps
CPU time 2.75 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:25:56 PM PDT 24
Peak memory 224048 kb
Host smart-40b9d29b-c3b4-4693-8d38-3dad31f7c591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365263100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2365263100
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.31638838
Short name T617
Test name
Test status
Simulation time 17131197 ps
CPU time 1.04 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:25:54 PM PDT 24
Peak memory 216444 kb
Host smart-3ab3ea47-ee0a-436f-9719-8ab63c9f2916
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31638838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.31638838
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3901535012
Short name T743
Test name
Test status
Simulation time 2747228364 ps
CPU time 7.13 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:26:02 PM PDT 24
Peak memory 234380 kb
Host smart-9a558806-e248-4aa1-b1e3-52f70a3842d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901535012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3901535012
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1552766192
Short name T15
Test name
Test status
Simulation time 3519054796 ps
CPU time 10.9 seconds
Started Mar 14 01:25:51 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 233532 kb
Host smart-b9d5d61f-b614-4da5-8e79-77d09cbabbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552766192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1552766192
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2503700363
Short name T780
Test name
Test status
Simulation time 18116395 ps
CPU time 0.76 seconds
Started Mar 14 01:25:54 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 215884 kb
Host smart-d801a1fa-9f7c-4af2-99fc-74a773e9f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503700363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2503700363
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3650356718
Short name T632
Test name
Test status
Simulation time 478731922 ps
CPU time 3.44 seconds
Started Mar 14 01:25:56 PM PDT 24
Finished Mar 14 01:25:59 PM PDT 24
Peak memory 222012 kb
Host smart-cd226754-aac1-4dbf-9122-1c5219494fde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3650356718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3650356718
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.604327406
Short name T403
Test name
Test status
Simulation time 2958404743 ps
CPU time 19.06 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:26:12 PM PDT 24
Peak memory 215988 kb
Host smart-3006a65b-280f-4ec6-a608-39438cd95967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604327406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.604327406
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1587087383
Short name T493
Test name
Test status
Simulation time 870475959 ps
CPU time 3.34 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:25:57 PM PDT 24
Peak memory 207580 kb
Host smart-7c59eb41-00eb-46d5-ac3c-e7e6259670ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587087383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1587087383
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1414286798
Short name T742
Test name
Test status
Simulation time 54822372 ps
CPU time 0.76 seconds
Started Mar 14 01:25:54 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 205320 kb
Host smart-6407180a-acbe-4dbb-9df8-d2dd4bac7945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414286798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1414286798
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2017631782
Short name T275
Test name
Test status
Simulation time 105199117 ps
CPU time 1.13 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 205280 kb
Host smart-de2fa98a-8a19-463c-9ad7-67910cee4f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017631782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2017631782
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.692799432
Short name T564
Test name
Test status
Simulation time 3025979454 ps
CPU time 13.51 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:26:07 PM PDT 24
Peak memory 239048 kb
Host smart-bb524971-118d-4bce-96c0-b10449591ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692799432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.692799432
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3673981108
Short name T734
Test name
Test status
Simulation time 65568271 ps
CPU time 0.75 seconds
Started Mar 14 01:26:03 PM PDT 24
Finished Mar 14 01:26:04 PM PDT 24
Peak memory 204932 kb
Host smart-285feadb-4419-47a7-8bfb-60321d16226f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673981108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3673981108
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.81367842
Short name T602
Test name
Test status
Simulation time 535905747 ps
CPU time 3.88 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 234116 kb
Host smart-6e5c137c-5ac5-4cb7-ac7c-57fa3609767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81367842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.81367842
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.122942088
Short name T259
Test name
Test status
Simulation time 43544273 ps
CPU time 0.77 seconds
Started Mar 14 01:25:51 PM PDT 24
Finished Mar 14 01:25:52 PM PDT 24
Peak memory 205076 kb
Host smart-5e15660e-9cf7-4a6b-908f-cfd61b721ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122942088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.122942088
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1230018457
Short name T301
Test name
Test status
Simulation time 3713670248 ps
CPU time 5.52 seconds
Started Mar 14 01:25:57 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 235992 kb
Host smart-cc3c7d95-83b8-43ed-9d8a-2a83867255d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230018457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1230018457
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1973911969
Short name T923
Test name
Test status
Simulation time 54396884980 ps
CPU time 268.46 seconds
Started Mar 14 01:25:51 PM PDT 24
Finished Mar 14 01:30:20 PM PDT 24
Peak memory 255832 kb
Host smart-29235868-0430-450d-9a75-00b65e79e8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973911969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1973911969
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.262318740
Short name T453
Test name
Test status
Simulation time 82204699198 ps
CPU time 233.07 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:29:48 PM PDT 24
Peak memory 263052 kb
Host smart-3dc9b7ea-aeb2-4b19-93e4-051295f31490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262318740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.262318740
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3156761552
Short name T563
Test name
Test status
Simulation time 6515403248 ps
CPU time 13.93 seconds
Started Mar 14 01:25:58 PM PDT 24
Finished Mar 14 01:26:13 PM PDT 24
Peak memory 232308 kb
Host smart-1e2df32d-dbcb-4891-b29d-7ab38b4dd12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156761552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3156761552
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4179484692
Short name T97
Test name
Test status
Simulation time 4497800932 ps
CPU time 14.25 seconds
Started Mar 14 01:25:58 PM PDT 24
Finished Mar 14 01:26:13 PM PDT 24
Peak memory 233992 kb
Host smart-7a241f4a-5348-4ec8-a11a-6de894fc0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179484692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4179484692
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.694477976
Short name T811
Test name
Test status
Simulation time 297786754 ps
CPU time 5.87 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:26:01 PM PDT 24
Peak memory 237368 kb
Host smart-fe231343-7071-4d33-8d19-da23057f8e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694477976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.694477976
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1459069186
Short name T579
Test name
Test status
Simulation time 25613313 ps
CPU time 1.07 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:25:54 PM PDT 24
Peak memory 216456 kb
Host smart-6d3a8cbf-22d4-475c-ab89-aebc75309f62
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459069186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1459069186
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1791078915
Short name T663
Test name
Test status
Simulation time 221576024 ps
CPU time 2.2 seconds
Started Mar 14 01:25:57 PM PDT 24
Finished Mar 14 01:26:00 PM PDT 24
Peak memory 223972 kb
Host smart-769f125d-340d-4a0b-8235-d24aa5b3673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791078915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1791078915
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1867639724
Short name T744
Test name
Test status
Simulation time 2164053230 ps
CPU time 8.44 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:26:01 PM PDT 24
Peak memory 232664 kb
Host smart-f7ab9fc4-a190-4306-8711-b4ebc0079411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867639724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1867639724
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.617281908
Short name T395
Test name
Test status
Simulation time 16535835 ps
CPU time 0.75 seconds
Started Mar 14 01:25:51 PM PDT 24
Finished Mar 14 01:25:53 PM PDT 24
Peak memory 215824 kb
Host smart-0182b338-7e50-4697-ad38-93b3c7c91cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617281908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.617281908
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4192104021
Short name T838
Test name
Test status
Simulation time 1059056016 ps
CPU time 5.58 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:05 PM PDT 24
Peak memory 222388 kb
Host smart-5319abac-fbba-425d-81cb-c00a65241d0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4192104021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4192104021
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1725535527
Short name T495
Test name
Test status
Simulation time 3409062466 ps
CPU time 29 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:26:22 PM PDT 24
Peak memory 216000 kb
Host smart-5998dbd0-4b26-4796-98bd-61638f57eefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725535527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1725535527
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1397111789
Short name T474
Test name
Test status
Simulation time 1358582465 ps
CPU time 9.43 seconds
Started Mar 14 01:25:48 PM PDT 24
Finished Mar 14 01:25:58 PM PDT 24
Peak memory 215876 kb
Host smart-1ba53662-9713-457b-a2fa-ef9c418bd140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397111789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1397111789
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1992464740
Short name T448
Test name
Test status
Simulation time 688690263 ps
CPU time 3.21 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:25:58 PM PDT 24
Peak memory 215792 kb
Host smart-4c8e4753-1e9e-4a4d-999d-96320737a8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992464740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1992464740
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2245142467
Short name T583
Test name
Test status
Simulation time 356960498 ps
CPU time 1.07 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:25:56 PM PDT 24
Peak memory 206320 kb
Host smart-f706b1ee-3cc4-4eb0-a386-b678dcd681e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245142467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2245142467
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4180747239
Short name T633
Test name
Test status
Simulation time 30031697257 ps
CPU time 19.87 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:19 PM PDT 24
Peak memory 219136 kb
Host smart-997c6fc8-a4e3-4055-9d83-1bf1520abec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180747239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4180747239
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1366936233
Short name T693
Test name
Test status
Simulation time 106137607 ps
CPU time 0.77 seconds
Started Mar 14 01:24:56 PM PDT 24
Finished Mar 14 01:24:56 PM PDT 24
Peak memory 204956 kb
Host smart-7190988d-40e0-47c6-9edc-65ac4c283849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366936233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
366936233
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.848502587
Short name T184
Test name
Test status
Simulation time 5971986996 ps
CPU time 10.84 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:25:00 PM PDT 24
Peak memory 235324 kb
Host smart-dc913134-84e9-47a9-9c7f-94f691358cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848502587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.848502587
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1044601590
Short name T408
Test name
Test status
Simulation time 16713534 ps
CPU time 0.76 seconds
Started Mar 14 01:24:46 PM PDT 24
Finished Mar 14 01:24:47 PM PDT 24
Peak memory 205076 kb
Host smart-18baae39-2241-48b0-a10e-e3fc063c4d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044601590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1044601590
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1866257828
Short name T891
Test name
Test status
Simulation time 3142954116 ps
CPU time 10.34 seconds
Started Mar 14 01:24:55 PM PDT 24
Finished Mar 14 01:25:06 PM PDT 24
Peak memory 218832 kb
Host smart-662b44fc-5f25-44c8-a8ea-b954ec396c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866257828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1866257828
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3021932693
Short name T628
Test name
Test status
Simulation time 14597338674 ps
CPU time 47.86 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:25:35 PM PDT 24
Peak memory 224144 kb
Host smart-7a0a3dc5-e9f0-469b-b5df-2f3a745868da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021932693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3021932693
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.411797846
Short name T847
Test name
Test status
Simulation time 1149489332 ps
CPU time 11.28 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:25:02 PM PDT 24
Peak memory 240060 kb
Host smart-d23777d5-ccb5-4b34-945a-e3e49dd989c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411797846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.411797846
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4283810650
Short name T816
Test name
Test status
Simulation time 430024630 ps
CPU time 2.98 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:53 PM PDT 24
Peak memory 223888 kb
Host smart-650f34a5-ab5d-48c9-ae01-dc96fa0000f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283810650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4283810650
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2126160953
Short name T176
Test name
Test status
Simulation time 8637741874 ps
CPU time 13.23 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:25:03 PM PDT 24
Peak memory 232956 kb
Host smart-d6aa2e02-7b99-4f09-8588-3f8e83cefd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126160953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2126160953
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2713396938
Short name T558
Test name
Test status
Simulation time 32845580 ps
CPU time 1.11 seconds
Started Mar 14 01:24:46 PM PDT 24
Finished Mar 14 01:24:48 PM PDT 24
Peak memory 216472 kb
Host smart-b6178da8-3f2a-43f9-b8bc-c857fa715db6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713396938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2713396938
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1282056364
Short name T369
Test name
Test status
Simulation time 97355059 ps
CPU time 2.64 seconds
Started Mar 14 01:24:48 PM PDT 24
Finished Mar 14 01:24:51 PM PDT 24
Peak memory 233100 kb
Host smart-863d8c1c-6bad-4835-bb66-3058676fc34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282056364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1282056364
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.897870771
Short name T825
Test name
Test status
Simulation time 28523622191 ps
CPU time 25.89 seconds
Started Mar 14 01:24:51 PM PDT 24
Finished Mar 14 01:25:16 PM PDT 24
Peak memory 248896 kb
Host smart-21b0f8ca-0072-4af2-9077-ef05aa79399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897870771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.897870771
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2020069802
Short name T327
Test name
Test status
Simulation time 17347991 ps
CPU time 0.73 seconds
Started Mar 14 01:24:52 PM PDT 24
Finished Mar 14 01:24:52 PM PDT 24
Peak memory 215912 kb
Host smart-be582f0d-f69b-4bf3-93d3-98053511b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020069802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2020069802
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2754603857
Short name T292
Test name
Test status
Simulation time 525455301 ps
CPU time 4.04 seconds
Started Mar 14 01:24:54 PM PDT 24
Finished Mar 14 01:24:58 PM PDT 24
Peak memory 221820 kb
Host smart-33302158-919e-4a53-9688-0e474b97d4cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2754603857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2754603857
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1053336103
Short name T63
Test name
Test status
Simulation time 185914080 ps
CPU time 1.02 seconds
Started Mar 14 01:24:49 PM PDT 24
Finished Mar 14 01:24:50 PM PDT 24
Peak memory 235200 kb
Host smart-41952ab7-d290-4a7b-876a-b444ded5ed44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053336103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1053336103
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2426380859
Short name T114
Test name
Test status
Simulation time 137573061 ps
CPU time 0.97 seconds
Started Mar 14 01:24:48 PM PDT 24
Finished Mar 14 01:24:49 PM PDT 24
Peak memory 206204 kb
Host smart-2c43b7b6-4dfd-4f05-8398-feccc50686a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426380859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2426380859
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3037155898
Short name T676
Test name
Test status
Simulation time 3023432610 ps
CPU time 9.03 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:59 PM PDT 24
Peak memory 215900 kb
Host smart-919d7bd0-3876-4d07-b5ba-e81e5f979702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037155898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3037155898
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.726445204
Short name T754
Test name
Test status
Simulation time 13518242056 ps
CPU time 34.69 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:25:22 PM PDT 24
Peak memory 216028 kb
Host smart-01095ad3-cef3-4086-964d-ec6de53d93fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726445204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.726445204
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1826518665
Short name T864
Test name
Test status
Simulation time 515967235 ps
CPU time 10.22 seconds
Started Mar 14 01:24:48 PM PDT 24
Finished Mar 14 01:24:58 PM PDT 24
Peak memory 215972 kb
Host smart-5b8ccbde-4177-43f0-9d0f-f9c2205afb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826518665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1826518665
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1489616816
Short name T690
Test name
Test status
Simulation time 29165808 ps
CPU time 0.78 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:51 PM PDT 24
Peak memory 205280 kb
Host smart-dd73b783-90ea-4ae5-8d86-8e87a57bfff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489616816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1489616816
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1391814982
Short name T492
Test name
Test status
Simulation time 7397423805 ps
CPU time 9.29 seconds
Started Mar 14 01:24:55 PM PDT 24
Finished Mar 14 01:25:04 PM PDT 24
Peak memory 219264 kb
Host smart-efd99c9e-47d1-4646-8bb3-395c410d7d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391814982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1391814982
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1421629392
Short name T388
Test name
Test status
Simulation time 36270110 ps
CPU time 0.74 seconds
Started Mar 14 01:26:02 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 204924 kb
Host smart-4c730908-6c2c-46f1-a2be-7071fa2efa37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421629392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1421629392
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.639892193
Short name T289
Test name
Test status
Simulation time 3429125580 ps
CPU time 6.81 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:06 PM PDT 24
Peak memory 218136 kb
Host smart-f354b15d-c1f3-40d0-a142-1da1d9d17081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639892193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.639892193
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4195728025
Short name T277
Test name
Test status
Simulation time 14790510 ps
CPU time 0.8 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:25:56 PM PDT 24
Peak memory 205044 kb
Host smart-6747cbcf-821e-4ffc-a061-d7ec06c7a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195728025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4195728025
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.240211550
Short name T718
Test name
Test status
Simulation time 2613177066 ps
CPU time 18.84 seconds
Started Mar 14 01:26:01 PM PDT 24
Finished Mar 14 01:26:19 PM PDT 24
Peak memory 231048 kb
Host smart-58456937-ed54-4480-bb88-eebccdb55f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240211550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.240211550
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.730586159
Short name T147
Test name
Test status
Simulation time 59033828757 ps
CPU time 126.45 seconds
Started Mar 14 01:26:03 PM PDT 24
Finished Mar 14 01:28:10 PM PDT 24
Peak memory 256956 kb
Host smart-d59205a1-5991-41ed-a576-a9c8df331932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730586159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.730586159
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3486228535
Short name T159
Test name
Test status
Simulation time 76698990129 ps
CPU time 434.3 seconds
Started Mar 14 01:26:03 PM PDT 24
Finished Mar 14 01:33:18 PM PDT 24
Peak memory 256648 kb
Host smart-8f994972-1e67-4406-8989-1684cc1ad66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486228535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3486228535
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.7993901
Short name T108
Test name
Test status
Simulation time 10186520167 ps
CPU time 14.76 seconds
Started Mar 14 01:25:49 PM PDT 24
Finished Mar 14 01:26:04 PM PDT 24
Peak memory 237360 kb
Host smart-7eca35d9-b4f1-4909-9b98-5578ba1e3231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7993901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.7993901
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2980200760
Short name T143
Test name
Test status
Simulation time 927181208 ps
CPU time 3.36 seconds
Started Mar 14 01:25:51 PM PDT 24
Finished Mar 14 01:25:54 PM PDT 24
Peak memory 233352 kb
Host smart-2189715f-757d-4756-8997-6ce718e34b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980200760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2980200760
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.545982837
Short name T548
Test name
Test status
Simulation time 8914834334 ps
CPU time 13.14 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:12 PM PDT 24
Peak memory 247356 kb
Host smart-96385ff2-4cca-4bdc-9135-9c3e160546af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545982837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.545982837
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3174037105
Short name T712
Test name
Test status
Simulation time 6751526052 ps
CPU time 9.4 seconds
Started Mar 14 01:25:53 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 224020 kb
Host smart-8a9168c0-01db-4df1-808b-2e0613c1938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174037105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3174037105
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3673962471
Short name T904
Test name
Test status
Simulation time 190009021 ps
CPU time 2.61 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:02 PM PDT 24
Peak memory 232320 kb
Host smart-b7c586a2-4f88-4332-a9c2-55d38cf2bd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673962471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3673962471
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3448904447
Short name T706
Test name
Test status
Simulation time 11377345143 ps
CPU time 5.9 seconds
Started Mar 14 01:25:56 PM PDT 24
Finished Mar 14 01:26:02 PM PDT 24
Peak memory 219684 kb
Host smart-1778a9fa-a28d-419d-b993-003acd271760
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3448904447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3448904447
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2798444699
Short name T65
Test name
Test status
Simulation time 48997677061 ps
CPU time 113.37 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:27:47 PM PDT 24
Peak memory 254060 kb
Host smart-851a6cbc-3a68-446d-8476-47862de06ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798444699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2798444699
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.624650451
Short name T642
Test name
Test status
Simulation time 1629913404 ps
CPU time 11.39 seconds
Started Mar 14 01:25:52 PM PDT 24
Finished Mar 14 01:26:05 PM PDT 24
Peak memory 215848 kb
Host smart-59fce7ee-10a1-46e6-a543-84ee0d6a2ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624650451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.624650451
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2098027724
Short name T418
Test name
Test status
Simulation time 7804560715 ps
CPU time 9.45 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:09 PM PDT 24
Peak memory 216012 kb
Host smart-38b547b2-b91c-4370-85d5-6587b14189f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098027724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2098027724
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2440705535
Short name T927
Test name
Test status
Simulation time 88852764 ps
CPU time 1.52 seconds
Started Mar 14 01:26:03 PM PDT 24
Finished Mar 14 01:26:05 PM PDT 24
Peak memory 215884 kb
Host smart-d67a5cfa-b19a-42ee-ac34-30c6a721af91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440705535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2440705535
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4277545759
Short name T419
Test name
Test status
Simulation time 186423842 ps
CPU time 0.94 seconds
Started Mar 14 01:25:58 PM PDT 24
Finished Mar 14 01:25:59 PM PDT 24
Peak memory 206324 kb
Host smart-7cd52694-377d-4d7e-bf0e-fd44b3098140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277545759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4277545759
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2197858056
Short name T865
Test name
Test status
Simulation time 785511360 ps
CPU time 4.93 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:04 PM PDT 24
Peak memory 228436 kb
Host smart-117a3427-fd1d-447e-9c9a-6f82469e02b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197858056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2197858056
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.125745269
Short name T502
Test name
Test status
Simulation time 69841412 ps
CPU time 0.77 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:26:06 PM PDT 24
Peak memory 204956 kb
Host smart-e453a1be-b3c7-4afe-b0d0-37b2579dfd32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125745269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.125745269
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1913841272
Short name T914
Test name
Test status
Simulation time 385017235 ps
CPU time 3.96 seconds
Started Mar 14 01:26:04 PM PDT 24
Finished Mar 14 01:26:09 PM PDT 24
Peak memory 234076 kb
Host smart-2729755b-fbfc-453e-afca-9863c8c1adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913841272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1913841272
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3870181074
Short name T705
Test name
Test status
Simulation time 25016188 ps
CPU time 0.81 seconds
Started Mar 14 01:25:51 PM PDT 24
Finished Mar 14 01:25:52 PM PDT 24
Peak memory 206020 kb
Host smart-b360cd8b-0921-475f-9132-056de60faefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870181074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3870181074
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3217835271
Short name T819
Test name
Test status
Simulation time 53793664836 ps
CPU time 90.24 seconds
Started Mar 14 01:26:04 PM PDT 24
Finished Mar 14 01:27:35 PM PDT 24
Peak memory 256712 kb
Host smart-95850cc7-0fda-4923-b096-6cdc75648392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217835271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3217835271
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.747986231
Short name T552
Test name
Test status
Simulation time 3763176899 ps
CPU time 63.48 seconds
Started Mar 14 01:26:03 PM PDT 24
Finished Mar 14 01:27:08 PM PDT 24
Peak memory 255280 kb
Host smart-d016e615-f0e9-4882-b4a0-966bccef719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747986231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.747986231
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1491761010
Short name T669
Test name
Test status
Simulation time 21468074098 ps
CPU time 22.2 seconds
Started Mar 14 01:25:55 PM PDT 24
Finished Mar 14 01:26:18 PM PDT 24
Peak memory 248424 kb
Host smart-b72bc95b-6258-4bb8-a0ad-c24b295573af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491761010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1491761010
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1417500872
Short name T423
Test name
Test status
Simulation time 563075762 ps
CPU time 5.55 seconds
Started Mar 14 01:25:57 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 218216 kb
Host smart-946399f1-343b-42e6-aa31-2fd23327b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417500872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1417500872
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3470258505
Short name T570
Test name
Test status
Simulation time 78799828 ps
CPU time 2.61 seconds
Started Mar 14 01:26:03 PM PDT 24
Finished Mar 14 01:26:06 PM PDT 24
Peak memory 232268 kb
Host smart-37be0885-c513-45d6-adcb-69eceb6ba6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470258505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3470258505
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2390772689
Short name T760
Test name
Test status
Simulation time 3169188570 ps
CPU time 6.58 seconds
Started Mar 14 01:25:57 PM PDT 24
Finished Mar 14 01:26:03 PM PDT 24
Peak memory 232396 kb
Host smart-d1606d31-faa4-4e83-9df5-cbf97d37553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390772689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2390772689
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3140747715
Short name T786
Test name
Test status
Simulation time 415245859 ps
CPU time 3.11 seconds
Started Mar 14 01:26:02 PM PDT 24
Finished Mar 14 01:26:05 PM PDT 24
Peak memory 233248 kb
Host smart-1bd88c49-46d9-419c-acfa-7be8ea8dc5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140747715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3140747715
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1841732597
Short name T882
Test name
Test status
Simulation time 1364318737 ps
CPU time 4.64 seconds
Started Mar 14 01:26:04 PM PDT 24
Finished Mar 14 01:26:09 PM PDT 24
Peak memory 218708 kb
Host smart-dd6f1d60-1f22-427f-8459-842a905c1609
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1841732597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1841732597
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4103813474
Short name T529
Test name
Test status
Simulation time 7243747462 ps
CPU time 21.6 seconds
Started Mar 14 01:26:04 PM PDT 24
Finished Mar 14 01:26:26 PM PDT 24
Peak memory 223516 kb
Host smart-06baa51e-d8f0-4e86-a8d3-cba88e77ecaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103813474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4103813474
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3235434210
Short name T720
Test name
Test status
Simulation time 11759423829 ps
CPU time 18.8 seconds
Started Mar 14 01:26:02 PM PDT 24
Finished Mar 14 01:26:21 PM PDT 24
Peak memory 215964 kb
Host smart-e649eb5c-dfde-48a3-9d80-1eb158c6dcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235434210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3235434210
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1443753899
Short name T82
Test name
Test status
Simulation time 619469669 ps
CPU time 4.83 seconds
Started Mar 14 01:25:59 PM PDT 24
Finished Mar 14 01:26:04 PM PDT 24
Peak memory 215832 kb
Host smart-d4942328-1592-4fd6-b5ac-73c8f562b7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443753899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1443753899
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3349586001
Short name T17
Test name
Test status
Simulation time 628035264 ps
CPU time 2.48 seconds
Started Mar 14 01:25:56 PM PDT 24
Finished Mar 14 01:25:58 PM PDT 24
Peak memory 215864 kb
Host smart-5bdcd468-aad8-42fe-ab8a-aa067d9aaf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349586001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3349586001
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2294689695
Short name T410
Test name
Test status
Simulation time 49659013 ps
CPU time 0.96 seconds
Started Mar 14 01:26:01 PM PDT 24
Finished Mar 14 01:26:02 PM PDT 24
Peak memory 206320 kb
Host smart-bc4d898d-c899-4547-ace4-e01375e83b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294689695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2294689695
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.977345848
Short name T799
Test name
Test status
Simulation time 23345410751 ps
CPU time 23.71 seconds
Started Mar 14 01:26:04 PM PDT 24
Finished Mar 14 01:26:28 PM PDT 24
Peak memory 222572 kb
Host smart-b8ea92aa-b7c9-4262-baa3-77fb069ff656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977345848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.977345848
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3581990325
Short name T752
Test name
Test status
Simulation time 14826062 ps
CPU time 0.73 seconds
Started Mar 14 01:26:09 PM PDT 24
Finished Mar 14 01:26:10 PM PDT 24
Peak memory 204944 kb
Host smart-5c6bf474-84fe-4e05-88ac-de87234d638d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581990325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3581990325
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.237235764
Short name T373
Test name
Test status
Simulation time 2528614204 ps
CPU time 4.92 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:26:10 PM PDT 24
Peak memory 218140 kb
Host smart-230e4fd4-a287-4d0d-ab3d-bad90f2d6c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237235764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.237235764
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4152035165
Short name T305
Test name
Test status
Simulation time 68863365 ps
CPU time 0.77 seconds
Started Mar 14 01:26:09 PM PDT 24
Finished Mar 14 01:26:10 PM PDT 24
Peak memory 205016 kb
Host smart-724510d1-5a9c-484d-99bb-c1d2e22f6c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152035165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4152035165
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.368250547
Short name T43
Test name
Test status
Simulation time 218769632027 ps
CPU time 274.67 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:30:40 PM PDT 24
Peak memory 264760 kb
Host smart-0f1c337f-84f7-4146-bd63-04d60f57a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368250547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.368250547
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3299594137
Short name T30
Test name
Test status
Simulation time 42396061175 ps
CPU time 302.98 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 267032 kb
Host smart-f80357f0-0f39-46ab-b4d0-6d6b4ad6a342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299594137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3299594137
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3264200813
Short name T468
Test name
Test status
Simulation time 7849267321 ps
CPU time 71.08 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:27:20 PM PDT 24
Peak memory 238780 kb
Host smart-8f3c57e2-a96d-4be1-99ab-d7b175bb5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264200813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3264200813
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.632284447
Short name T459
Test name
Test status
Simulation time 1765905895 ps
CPU time 16.01 seconds
Started Mar 14 01:26:03 PM PDT 24
Finished Mar 14 01:26:20 PM PDT 24
Peak memory 232216 kb
Host smart-369ecffd-b10a-429d-b1ef-6a32f10dc558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632284447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.632284447
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1197885701
Short name T427
Test name
Test status
Simulation time 3215915568 ps
CPU time 3.29 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:12 PM PDT 24
Peak memory 232384 kb
Host smart-96d69364-9454-4349-a511-466673d2cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197885701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1197885701
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.170862482
Short name T802
Test name
Test status
Simulation time 1050745044 ps
CPU time 6.47 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:13 PM PDT 24
Peak memory 233128 kb
Host smart-ca2ad067-dc8a-46f2-aeb0-b714365fb4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170862482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.170862482
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1525319790
Short name T49
Test name
Test status
Simulation time 1123417380 ps
CPU time 5.94 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 235960 kb
Host smart-a3c3347f-8dfb-4132-90d8-d6173dd31659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525319790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1525319790
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3163980528
Short name T360
Test name
Test status
Simulation time 16380733595 ps
CPU time 8.33 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 232848 kb
Host smart-65f105c9-9e98-48c9-a7fb-db44fdd886a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163980528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3163980528
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.958963683
Short name T283
Test name
Test status
Simulation time 773226240 ps
CPU time 3.62 seconds
Started Mar 14 01:26:09 PM PDT 24
Finished Mar 14 01:26:13 PM PDT 24
Peak memory 219864 kb
Host smart-c1bc58d8-af80-4aaf-bdcb-73ca2be2bfcd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=958963683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.958963683
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4089795388
Short name T895
Test name
Test status
Simulation time 315482224 ps
CPU time 1.19 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:10 PM PDT 24
Peak memory 206408 kb
Host smart-b5d57540-c400-47a9-8b47-73fdff3efdff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089795388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4089795388
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4132969947
Short name T417
Test name
Test status
Simulation time 9721881197 ps
CPU time 30.59 seconds
Started Mar 14 01:26:08 PM PDT 24
Finished Mar 14 01:26:40 PM PDT 24
Peak memory 215884 kb
Host smart-61283c66-e7b1-4267-8263-01b830b86742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132969947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4132969947
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4111184440
Short name T299
Test name
Test status
Simulation time 774430983 ps
CPU time 4.58 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:13 PM PDT 24
Peak memory 215912 kb
Host smart-704bec60-c2fb-463b-b539-360828253c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111184440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4111184440
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1240146613
Short name T892
Test name
Test status
Simulation time 830860927 ps
CPU time 3.33 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:12 PM PDT 24
Peak memory 216020 kb
Host smart-28b3b129-d592-4002-a5e0-c382e4c0adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240146613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1240146613
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.861684581
Short name T515
Test name
Test status
Simulation time 59620606 ps
CPU time 0.9 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:08 PM PDT 24
Peak memory 205316 kb
Host smart-62d8bb58-18f6-4d9f-bced-e7b9253c275a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861684581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.861684581
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2096061480
Short name T186
Test name
Test status
Simulation time 7353432591 ps
CPU time 7.63 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:14 PM PDT 24
Peak memory 218388 kb
Host smart-68999ca8-4484-45a4-b937-8b1ca17ef2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096061480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2096061480
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.48199459
Short name T767
Test name
Test status
Simulation time 15663184 ps
CPU time 0.74 seconds
Started Mar 14 01:26:14 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 204392 kb
Host smart-d2726640-6bfd-4f9f-bf90-657d1fd73283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48199459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.48199459
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2498114301
Short name T394
Test name
Test status
Simulation time 131646489 ps
CPU time 3.72 seconds
Started Mar 14 01:26:14 PM PDT 24
Finished Mar 14 01:26:18 PM PDT 24
Peak memory 237692 kb
Host smart-efbfa113-07ea-4a1d-a28d-12fb5904d939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498114301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2498114301
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.867609761
Short name T338
Test name
Test status
Simulation time 56403519 ps
CPU time 0.75 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:09 PM PDT 24
Peak memory 205032 kb
Host smart-4f911bf4-7bb5-4ad2-a631-a21e4df9a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867609761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.867609761
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2200997218
Short name T508
Test name
Test status
Simulation time 34548527987 ps
CPU time 163.51 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:28:50 PM PDT 24
Peak memory 256252 kb
Host smart-c0ad88c2-a43f-447f-b962-89056700f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200997218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2200997218
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2970758167
Short name T103
Test name
Test status
Simulation time 26712489049 ps
CPU time 210.37 seconds
Started Mar 14 01:26:08 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 265188 kb
Host smart-25d976d4-4bd7-49bc-b0bd-9ee755feea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970758167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2970758167
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1649972465
Short name T592
Test name
Test status
Simulation time 4227003701 ps
CPU time 16.16 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:23 PM PDT 24
Peak memory 232964 kb
Host smart-73447be8-ce45-4058-826f-94c9e983f7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649972465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1649972465
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2592571467
Short name T844
Test name
Test status
Simulation time 7621482405 ps
CPU time 11.48 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:26:17 PM PDT 24
Peak memory 224128 kb
Host smart-3002dc83-8a91-4374-971a-3be8704b01fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592571467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2592571467
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3365937275
Short name T188
Test name
Test status
Simulation time 50297878057 ps
CPU time 33.47 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 236972 kb
Host smart-58e8575f-f097-4622-bb52-c1e301b5ef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365937275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3365937275
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2685864331
Short name T200
Test name
Test status
Simulation time 22625451689 ps
CPU time 18.92 seconds
Started Mar 14 01:26:11 PM PDT 24
Finished Mar 14 01:26:30 PM PDT 24
Peak memory 233444 kb
Host smart-f5d2e2fc-4adc-45bb-8d27-4c48731ee9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685864331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2685864331
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.922593939
Short name T391
Test name
Test status
Simulation time 5074968009 ps
CPU time 8.27 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:26:14 PM PDT 24
Peak memory 232924 kb
Host smart-74bafa2b-171c-45f0-99ec-7953530e34bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922593939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.922593939
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1736312090
Short name T31
Test name
Test status
Simulation time 3613624942 ps
CPU time 5.79 seconds
Started Mar 14 01:26:08 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 218404 kb
Host smart-cff500f8-6ad2-4f3e-9f9c-ec3dafebc766
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1736312090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1736312090
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1912024934
Short name T922
Test name
Test status
Simulation time 132116254827 ps
CPU time 32.97 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:40 PM PDT 24
Peak memory 216004 kb
Host smart-0e878d41-4129-4b8e-8810-d02550cda62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912024934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1912024934
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3934252306
Short name T727
Test name
Test status
Simulation time 3325281221 ps
CPU time 6.83 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 215880 kb
Host smart-206ee45d-4397-4466-8b03-eb3eec95fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934252306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3934252306
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2543953785
Short name T814
Test name
Test status
Simulation time 609182547 ps
CPU time 11.26 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:20 PM PDT 24
Peak memory 215848 kb
Host smart-5d176ac2-5ace-4e2d-8cfc-d435d0ad39ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543953785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2543953785
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2655085880
Short name T631
Test name
Test status
Simulation time 210999251 ps
CPU time 0.81 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:08 PM PDT 24
Peak memory 205276 kb
Host smart-f411d56a-efe5-43c7-9b3e-fd363904fa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655085880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2655085880
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1065696057
Short name T22
Test name
Test status
Simulation time 4782159893 ps
CPU time 11.47 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:26:18 PM PDT 24
Peak memory 219408 kb
Host smart-680b46ad-fe35-4e83-be04-8373984cc6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065696057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1065696057
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.729886464
Short name T425
Test name
Test status
Simulation time 27642210 ps
CPU time 0.77 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:26:22 PM PDT 24
Peak memory 205304 kb
Host smart-ee1594d5-feff-4b8a-85ee-248fc3aa268d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729886464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.729886464
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1192734465
Short name T835
Test name
Test status
Simulation time 1878847955 ps
CPU time 5.14 seconds
Started Mar 14 01:26:09 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 232648 kb
Host smart-8570f48d-e7f2-4009-bc94-a51e72ff2e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192734465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1192734465
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1387218865
Short name T328
Test name
Test status
Simulation time 32824322 ps
CPU time 0.84 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:26:07 PM PDT 24
Peak memory 206060 kb
Host smart-f742c9a2-ec1a-440a-9a44-b495c86eecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387218865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1387218865
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2805002720
Short name T482
Test name
Test status
Simulation time 15431465224 ps
CPU time 43.16 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:27:04 PM PDT 24
Peak memory 240568 kb
Host smart-d6d6bdb2-7812-43ab-804a-4c04bb5d2164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805002720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2805002720
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3430248597
Short name T122
Test name
Test status
Simulation time 15794361846 ps
CPU time 78.81 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:27:38 PM PDT 24
Peak memory 257008 kb
Host smart-3d42b1ec-f1ab-4125-8ad9-e1f11f889f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430248597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3430248597
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3406995583
Short name T722
Test name
Test status
Simulation time 7474107112 ps
CPU time 54.94 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 222372 kb
Host smart-6a9865f0-2722-4b5f-a6cd-6c423ed12659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406995583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3406995583
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1767046326
Short name T113
Test name
Test status
Simulation time 1099434038 ps
CPU time 8.8 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:17 PM PDT 24
Peak memory 238132 kb
Host smart-28b0ea3d-dd25-4451-9c0c-771ef49a7d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767046326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1767046326
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.340442645
Short name T657
Test name
Test status
Simulation time 1501286577 ps
CPU time 3.17 seconds
Started Mar 14 01:26:11 PM PDT 24
Finished Mar 14 01:26:14 PM PDT 24
Peak memory 216316 kb
Host smart-7e48b958-3ccb-47f8-b152-13872908ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340442645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.340442645
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3747259993
Short name T566
Test name
Test status
Simulation time 1522045324 ps
CPU time 5.18 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:14 PM PDT 24
Peak memory 223972 kb
Host smart-9257b9f8-b66f-4eb1-88a1-4dcc4a076922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747259993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3747259993
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.115084665
Short name T365
Test name
Test status
Simulation time 604492972 ps
CPU time 3.52 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:12 PM PDT 24
Peak memory 220316 kb
Host smart-80a8c14e-9d53-45a9-9525-c1e36fd8acd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115084665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.115084665
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2194167639
Short name T441
Test name
Test status
Simulation time 4510489919 ps
CPU time 16.65 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:26 PM PDT 24
Peak memory 224132 kb
Host smart-5889455a-ed1f-4be1-96fe-3fb6d255da41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194167639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2194167639
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1822068881
Short name T624
Test name
Test status
Simulation time 85963007 ps
CPU time 3.46 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 222036 kb
Host smart-ed9b84a9-6b27-4ade-9bf0-d4414e85287f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1822068881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1822068881
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2040265636
Short name T573
Test name
Test status
Simulation time 4688271462 ps
CPU time 13.03 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:20 PM PDT 24
Peak memory 216000 kb
Host smart-20463be8-aa72-48d1-9316-23e1426581f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040265636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2040265636
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2396220495
Short name T542
Test name
Test status
Simulation time 6547947176 ps
CPU time 6.7 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 216008 kb
Host smart-b308c346-f946-4d1c-b7c6-db38a259745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396220495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2396220495
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3188845138
Short name T466
Test name
Test status
Simulation time 68762042 ps
CPU time 1.54 seconds
Started Mar 14 01:26:07 PM PDT 24
Finished Mar 14 01:26:10 PM PDT 24
Peak memory 215912 kb
Host smart-871698c1-a63f-4c2c-bb4e-51ffc297ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188845138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3188845138
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2620648554
Short name T276
Test name
Test status
Simulation time 97096036 ps
CPU time 1.08 seconds
Started Mar 14 01:26:06 PM PDT 24
Finished Mar 14 01:26:09 PM PDT 24
Peak memory 206292 kb
Host smart-92e51749-ff2f-4d21-b2b9-80575686fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620648554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2620648554
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1252293638
Short name T465
Test name
Test status
Simulation time 11729419104 ps
CPU time 31.86 seconds
Started Mar 14 01:26:05 PM PDT 24
Finished Mar 14 01:26:38 PM PDT 24
Peak memory 229964 kb
Host smart-60a4258b-d75f-43f3-8386-450f6f8fcaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252293638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1252293638
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3569827162
Short name T538
Test name
Test status
Simulation time 16809793 ps
CPU time 0.78 seconds
Started Mar 14 01:26:29 PM PDT 24
Finished Mar 14 01:26:29 PM PDT 24
Peak memory 204976 kb
Host smart-aa386c15-1e60-426d-adfc-3c5fb1630270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569827162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3569827162
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3649668156
Short name T181
Test name
Test status
Simulation time 61656680 ps
CPU time 2.46 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 232976 kb
Host smart-87fd8cdd-7388-4a4d-b664-48009093b530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649668156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3649668156
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3893054479
Short name T812
Test name
Test status
Simulation time 22644700 ps
CPU time 0.75 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:26:20 PM PDT 24
Peak memory 205060 kb
Host smart-1d159fca-8b3e-4742-a3c5-289415851bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893054479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3893054479
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2570051022
Short name T152
Test name
Test status
Simulation time 6050645791 ps
CPU time 65.78 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:27:28 PM PDT 24
Peak memory 256744 kb
Host smart-f1e15926-716c-4712-8fde-15ccc5d60140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570051022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2570051022
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3630274832
Short name T616
Test name
Test status
Simulation time 6475838869 ps
CPU time 64.54 seconds
Started Mar 14 01:26:23 PM PDT 24
Finished Mar 14 01:27:27 PM PDT 24
Peak memory 250268 kb
Host smart-5bf68282-608d-4a1c-9870-9b2ddbeab21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630274832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3630274832
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3080048285
Short name T296
Test name
Test status
Simulation time 654281191 ps
CPU time 8.77 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:33 PM PDT 24
Peak memory 235260 kb
Host smart-8b597303-334f-4b25-87c3-2a77af4536ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080048285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3080048285
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.10210234
Short name T210
Test name
Test status
Simulation time 2525322518 ps
CPU time 8.79 seconds
Started Mar 14 01:26:28 PM PDT 24
Finished Mar 14 01:26:37 PM PDT 24
Peak memory 224132 kb
Host smart-6ac97b31-c377-4c89-9be4-f5f68850040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10210234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.10210234
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2235495528
Short name T149
Test name
Test status
Simulation time 5816530892 ps
CPU time 20.46 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:45 PM PDT 24
Peak memory 235344 kb
Host smart-322bb3f6-f329-46bd-bb09-9de3186384dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235495528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2235495528
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.781663662
Short name T938
Test name
Test status
Simulation time 452605759 ps
CPU time 3.21 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:26:25 PM PDT 24
Peak memory 216248 kb
Host smart-332cc2ce-1c4a-47cd-81e0-0453fcf6fb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781663662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.781663662
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3346177069
Short name T807
Test name
Test status
Simulation time 5101529446 ps
CPU time 7.72 seconds
Started Mar 14 01:26:25 PM PDT 24
Finished Mar 14 01:26:33 PM PDT 24
Peak memory 224164 kb
Host smart-f2e09dc9-2b0e-43b6-a59b-bf00e3cb87f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346177069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3346177069
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4109978355
Short name T686
Test name
Test status
Simulation time 549992121 ps
CPU time 4.34 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 218616 kb
Host smart-2334432b-356b-452c-b4b9-245913286d1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4109978355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4109978355
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.183777622
Short name T881
Test name
Test status
Simulation time 66404877080 ps
CPU time 85.5 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:27:46 PM PDT 24
Peak memory 248748 kb
Host smart-90464be2-507a-40be-a5ba-fdb96a109b54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183777622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.183777622
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.950172906
Short name T416
Test name
Test status
Simulation time 1132813820 ps
CPU time 15.05 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:26:35 PM PDT 24
Peak memory 215888 kb
Host smart-0d52ed0c-5a8a-4385-a959-6357b99b6be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950172906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.950172906
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2705875766
Short name T520
Test name
Test status
Simulation time 6710289238 ps
CPU time 10.65 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:26:31 PM PDT 24
Peak memory 215916 kb
Host smart-15c1c6e5-df1c-4baa-917b-6adc908f42ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705875766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2705875766
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.581674165
Short name T553
Test name
Test status
Simulation time 22751224 ps
CPU time 1.18 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 207552 kb
Host smart-77cbdcf9-50bd-4283-bb40-b67391fce6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581674165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.581674165
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3660296528
Short name T95
Test name
Test status
Simulation time 21336195 ps
CPU time 0.78 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:26:21 PM PDT 24
Peak memory 205340 kb
Host smart-2bcf0b48-24e5-4972-9d1e-16411d17f671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660296528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3660296528
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3665902709
Short name T178
Test name
Test status
Simulation time 1060308419 ps
CPU time 5.38 seconds
Started Mar 14 01:26:17 PM PDT 24
Finished Mar 14 01:26:23 PM PDT 24
Peak memory 233068 kb
Host smart-34efb6ec-fa3b-469f-a6f1-9c01c01cc1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665902709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3665902709
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3981753037
Short name T523
Test name
Test status
Simulation time 23799827 ps
CPU time 0.69 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:26:22 PM PDT 24
Peak memory 204420 kb
Host smart-578fdc43-3f3c-4c82-9eaa-281d2b923142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981753037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3981753037
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2720847815
Short name T600
Test name
Test status
Simulation time 138043337 ps
CPU time 2.25 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:26:22 PM PDT 24
Peak memory 232752 kb
Host smart-7c091813-5b09-46f4-a8e8-95144fe3eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720847815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2720847815
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.990486710
Short name T375
Test name
Test status
Simulation time 51897479 ps
CPU time 0.75 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:26:22 PM PDT 24
Peak memory 205292 kb
Host smart-a788fa82-83ea-430a-b84e-9bd4982a5de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990486710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.990486710
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3747312697
Short name T199
Test name
Test status
Simulation time 182662347146 ps
CPU time 408.2 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:33:10 PM PDT 24
Peak memory 265148 kb
Host smart-b6b54ba2-be81-48d1-af88-ad4821208c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747312697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3747312697
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2253930453
Short name T447
Test name
Test status
Simulation time 10189875356 ps
CPU time 106.16 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 257020 kb
Host smart-0fe484d3-5d4b-4a24-a5fc-8489c2c5e837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253930453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2253930453
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3156947245
Short name T715
Test name
Test status
Simulation time 16192756945 ps
CPU time 37.61 seconds
Started Mar 14 01:26:27 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 248628 kb
Host smart-1d6bf564-7316-4da7-9c60-e3d35da56474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156947245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3156947245
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2502414250
Short name T759
Test name
Test status
Simulation time 2174031120 ps
CPU time 8.03 seconds
Started Mar 14 01:26:27 PM PDT 24
Finished Mar 14 01:26:35 PM PDT 24
Peak memory 219180 kb
Host smart-05200f70-bc1c-4c51-a00e-5809036b1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502414250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2502414250
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1416859959
Short name T918
Test name
Test status
Simulation time 43072273738 ps
CPU time 55.13 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:27:17 PM PDT 24
Peak memory 247432 kb
Host smart-f26dbf42-8911-48b9-b8a1-5ce738c3da17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416859959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1416859959
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.266469303
Short name T713
Test name
Test status
Simulation time 2828872948 ps
CPU time 5.98 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:26:26 PM PDT 24
Peak memory 217324 kb
Host smart-5e9ab3ca-7d29-4fcf-bacd-341378b4414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266469303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.266469303
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2195359841
Short name T729
Test name
Test status
Simulation time 460982216 ps
CPU time 6.44 seconds
Started Mar 14 01:26:23 PM PDT 24
Finished Mar 14 01:26:29 PM PDT 24
Peak memory 224104 kb
Host smart-30202d7c-7563-4431-812d-77eff076003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195359841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2195359841
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3360949456
Short name T457
Test name
Test status
Simulation time 7548329867 ps
CPU time 5.55 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:30 PM PDT 24
Peak memory 217968 kb
Host smart-06ff7ae0-1e37-42a2-b6c5-16ca004acd2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3360949456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3360949456
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2680918352
Short name T689
Test name
Test status
Simulation time 22501289958 ps
CPU time 70.68 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:27:31 PM PDT 24
Peak memory 234132 kb
Host smart-2dd15a59-7dd7-4ac8-b53e-f4d438243280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680918352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2680918352
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.511328804
Short name T532
Test name
Test status
Simulation time 2438535914 ps
CPU time 11.73 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:26:31 PM PDT 24
Peak memory 215920 kb
Host smart-f623e99f-91dc-4461-a8c2-d92b72ef4e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511328804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.511328804
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1869247440
Short name T291
Test name
Test status
Simulation time 3043825970 ps
CPU time 13.84 seconds
Started Mar 14 01:26:26 PM PDT 24
Finished Mar 14 01:26:40 PM PDT 24
Peak memory 215996 kb
Host smart-6d6e0442-2049-4d51-80f7-549271eed83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869247440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1869247440
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1186333448
Short name T244
Test name
Test status
Simulation time 57407481 ps
CPU time 0.84 seconds
Started Mar 14 01:26:28 PM PDT 24
Finished Mar 14 01:26:29 PM PDT 24
Peak memory 205324 kb
Host smart-d8b7e0ca-1059-4038-98d0-5f48079a63fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186333448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1186333448
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1529720284
Short name T933
Test name
Test status
Simulation time 246299385 ps
CPU time 0.83 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:26:23 PM PDT 24
Peak memory 205312 kb
Host smart-6315a2fc-7836-4803-8194-f564d59a4801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529720284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1529720284
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1909762360
Short name T808
Test name
Test status
Simulation time 24408236828 ps
CPU time 15.05 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:39 PM PDT 24
Peak memory 236068 kb
Host smart-df5b7fb8-37cd-4ef0-a74d-73781ef406b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909762360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1909762360
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.991618453
Short name T371
Test name
Test status
Simulation time 14904450 ps
CPU time 0.74 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 205172 kb
Host smart-b993e985-c222-48e3-9361-0bd3477b657d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991618453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.991618453
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.147242287
Short name T939
Test name
Test status
Simulation time 784267737 ps
CPU time 4.74 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:29 PM PDT 24
Peak memory 217488 kb
Host smart-0b46e7ac-7319-4bee-8a04-61891c36a60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147242287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.147242287
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2473796130
Short name T258
Test name
Test status
Simulation time 37403964 ps
CPU time 0.86 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 206392 kb
Host smart-53a0869f-5f11-4b09-97c2-e2126ae55f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473796130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2473796130
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.830624764
Short name T386
Test name
Test status
Simulation time 5006098585 ps
CPU time 13.25 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:37 PM PDT 24
Peak memory 233644 kb
Host smart-396f5574-dc73-46cc-a00c-c2930b6b9585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830624764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.830624764
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2777480589
Short name T154
Test name
Test status
Simulation time 9909082681 ps
CPU time 64.75 seconds
Started Mar 14 01:26:23 PM PDT 24
Finished Mar 14 01:27:28 PM PDT 24
Peak memory 233488 kb
Host smart-e770d71f-8a6d-4c27-8654-31a3da472c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777480589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2777480589
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3699710613
Short name T798
Test name
Test status
Simulation time 40117597953 ps
CPU time 241.41 seconds
Started Mar 14 01:26:29 PM PDT 24
Finished Mar 14 01:30:30 PM PDT 24
Peak memory 254800 kb
Host smart-80dedb5a-5a68-4ea1-ab27-a0ae0328db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699710613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3699710613
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.729006208
Short name T83
Test name
Test status
Simulation time 8969293889 ps
CPU time 21 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:43 PM PDT 24
Peak memory 240528 kb
Host smart-e98d3479-5c0d-4acf-ab62-6a3f43fe7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729006208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.729006208
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1877951650
Short name T609
Test name
Test status
Simulation time 443655658 ps
CPU time 3.32 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:26:23 PM PDT 24
Peak memory 219060 kb
Host smart-f424e2cf-d39f-4017-90f3-93be8db55c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877951650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1877951650
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.844747263
Short name T512
Test name
Test status
Simulation time 3130182588 ps
CPU time 11.4 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:36 PM PDT 24
Peak memory 219132 kb
Host smart-94fbcf8d-4930-4c92-a058-d41bd7446ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844747263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.844747263
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1452237219
Short name T234
Test name
Test status
Simulation time 23335362033 ps
CPU time 19.91 seconds
Started Mar 14 01:26:19 PM PDT 24
Finished Mar 14 01:26:39 PM PDT 24
Peak memory 232372 kb
Host smart-bfc5a12a-0f94-4a2c-8e0b-c596473b9397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452237219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1452237219
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.926879149
Short name T98
Test name
Test status
Simulation time 12140009479 ps
CPU time 36.72 seconds
Started Mar 14 01:26:25 PM PDT 24
Finished Mar 14 01:27:02 PM PDT 24
Peak memory 240568 kb
Host smart-915c592d-59eb-4de3-afb1-56007fc0819f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926879149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.926879149
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2535532606
Short name T711
Test name
Test status
Simulation time 170744088 ps
CPU time 3.02 seconds
Started Mar 14 01:26:29 PM PDT 24
Finished Mar 14 01:26:32 PM PDT 24
Peak memory 218396 kb
Host smart-7070482a-5d4b-415f-b693-a1ae5a932399
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2535532606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2535532606
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2315322611
Short name T749
Test name
Test status
Simulation time 172821437 ps
CPU time 1 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:26:22 PM PDT 24
Peak memory 206232 kb
Host smart-85370c90-535e-4b3e-985b-a3bde44f4af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315322611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2315322611
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3337416930
Short name T19
Test name
Test status
Simulation time 11674261102 ps
CPU time 18.75 seconds
Started Mar 14 01:26:25 PM PDT 24
Finished Mar 14 01:26:44 PM PDT 24
Peak memory 216032 kb
Host smart-f1be5759-358e-4b71-a720-ce7e1b7744d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337416930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3337416930
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2936057190
Short name T896
Test name
Test status
Simulation time 10911974513 ps
CPU time 8.11 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:26:28 PM PDT 24
Peak memory 215984 kb
Host smart-e9f6f4cf-0efa-4464-a89b-220b00620f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936057190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2936057190
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2615518885
Short name T586
Test name
Test status
Simulation time 4039202514 ps
CPU time 8.21 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:26:30 PM PDT 24
Peak memory 216032 kb
Host smart-33dd9c23-3a23-4428-9150-ad020e6a28d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615518885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2615518885
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1531634197
Short name T906
Test name
Test status
Simulation time 78186383 ps
CPU time 0.83 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:25 PM PDT 24
Peak memory 205316 kb
Host smart-81d8da19-3fa7-441a-8f88-928036cf07f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531634197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1531634197
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1871813807
Short name T195
Test name
Test status
Simulation time 2797567961 ps
CPU time 8.85 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:33 PM PDT 24
Peak memory 218776 kb
Host smart-d704fd92-966a-43c5-8ba1-9102161e57cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871813807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1871813807
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3040591595
Short name T321
Test name
Test status
Simulation time 20120254 ps
CPU time 0.71 seconds
Started Mar 14 01:26:24 PM PDT 24
Finished Mar 14 01:26:25 PM PDT 24
Peak memory 204960 kb
Host smart-eed4806c-fdd8-43f7-8a61-7ddd4bfe0878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040591595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3040591595
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2647446151
Short name T187
Test name
Test status
Simulation time 225072950 ps
CPU time 2.95 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:25 PM PDT 24
Peak memory 233284 kb
Host smart-4d2272af-9f2a-4b25-b07a-e5659762bb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647446151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2647446151
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.299732218
Short name T298
Test name
Test status
Simulation time 51613002 ps
CPU time 0.83 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:23 PM PDT 24
Peak memory 206108 kb
Host smart-623c2364-7b9c-4d99-a050-37e534fd79b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299732218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.299732218
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.192872167
Short name T115
Test name
Test status
Simulation time 1792977596 ps
CPU time 19.2 seconds
Started Mar 14 01:26:29 PM PDT 24
Finished Mar 14 01:26:48 PM PDT 24
Peak memory 248704 kb
Host smart-df4b212e-cbcb-4e9f-9715-9d2b196ce035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192872167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.192872167
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.467202229
Short name T40
Test name
Test status
Simulation time 14135270148 ps
CPU time 135.18 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:28:38 PM PDT 24
Peak memory 269900 kb
Host smart-cc9ea8e8-66f1-454b-86a1-bf2f7aae1896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467202229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.467202229
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.488260952
Short name T123
Test name
Test status
Simulation time 24733144315 ps
CPU time 27.59 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:49 PM PDT 24
Peak memory 236936 kb
Host smart-2ffcb5a3-00ea-430d-a42e-dcbe20de3666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488260952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.488260952
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3076609273
Short name T622
Test name
Test status
Simulation time 3415288136 ps
CPU time 16.2 seconds
Started Mar 14 01:26:18 PM PDT 24
Finished Mar 14 01:26:35 PM PDT 24
Peak memory 245488 kb
Host smart-715dc256-5c09-49b3-a2b8-761faca68190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076609273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3076609273
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1952198270
Short name T704
Test name
Test status
Simulation time 3825935541 ps
CPU time 12.48 seconds
Started Mar 14 01:26:23 PM PDT 24
Finished Mar 14 01:26:36 PM PDT 24
Peak memory 218344 kb
Host smart-5e832472-5ef9-4383-bed7-e88846b396af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952198270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1952198270
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2355417113
Short name T140
Test name
Test status
Simulation time 2751635269 ps
CPU time 9.27 seconds
Started Mar 14 01:26:29 PM PDT 24
Finished Mar 14 01:26:38 PM PDT 24
Peak memory 235284 kb
Host smart-cdac1490-f6a1-46a0-9382-dce987567ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355417113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2355417113
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3828579402
Short name T594
Test name
Test status
Simulation time 3894042563 ps
CPU time 12.28 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:35 PM PDT 24
Peak memory 218156 kb
Host smart-61c9892e-6081-4f22-a5bc-6a675b333df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828579402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3828579402
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3425438112
Short name T281
Test name
Test status
Simulation time 5464652468 ps
CPU time 5.17 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:28 PM PDT 24
Peak memory 236784 kb
Host smart-fd788f2a-0e39-49a3-af8b-d945ed065a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425438112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3425438112
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3240026389
Short name T498
Test name
Test status
Simulation time 69940568 ps
CPU time 3.24 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 222456 kb
Host smart-2dc47ba7-c9f7-44a7-aa9f-63ebb46fd5a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240026389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3240026389
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1310654472
Short name T912
Test name
Test status
Simulation time 16521049407 ps
CPU time 42.73 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:27:06 PM PDT 24
Peak memory 219420 kb
Host smart-29b66b5f-7771-48a5-a3d6-fcf94f5f1ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310654472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1310654472
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.124872608
Short name T685
Test name
Test status
Simulation time 4733935828 ps
CPU time 13.79 seconds
Started Mar 14 01:26:23 PM PDT 24
Finished Mar 14 01:26:37 PM PDT 24
Peak memory 216016 kb
Host smart-ce7522df-1b78-4fc7-9050-31606f5ff546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124872608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.124872608
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.666269784
Short name T297
Test name
Test status
Simulation time 126195219 ps
CPU time 2.62 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:25 PM PDT 24
Peak memory 215944 kb
Host smart-70f777ab-766e-4ff4-b8bd-45cf96923873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666269784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.666269784
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4002894189
Short name T88
Test name
Test status
Simulation time 36353598 ps
CPU time 0.89 seconds
Started Mar 14 01:26:27 PM PDT 24
Finished Mar 14 01:26:28 PM PDT 24
Peak memory 206316 kb
Host smart-86530883-8714-4aec-a7f1-6ad09f56a300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002894189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4002894189
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3257674575
Short name T591
Test name
Test status
Simulation time 338806009 ps
CPU time 4.41 seconds
Started Mar 14 01:26:21 PM PDT 24
Finished Mar 14 01:26:25 PM PDT 24
Peak memory 218456 kb
Host smart-74ab56de-423d-460f-96a5-37988fcfde8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257674575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3257674575
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2712379602
Short name T878
Test name
Test status
Simulation time 17458819 ps
CPU time 0.78 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:37 PM PDT 24
Peak memory 204952 kb
Host smart-19996e35-0041-42bb-a421-9d52a3ce90c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712379602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2712379602
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1342751922
Short name T590
Test name
Test status
Simulation time 699344872 ps
CPU time 4.69 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:41 PM PDT 24
Peak memory 220376 kb
Host smart-cf382d49-50fb-4e0e-82f1-6930824f2b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342751922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1342751922
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3686210287
Short name T477
Test name
Test status
Simulation time 38686162 ps
CPU time 0.78 seconds
Started Mar 14 01:26:20 PM PDT 24
Finished Mar 14 01:26:22 PM PDT 24
Peak memory 206060 kb
Host smart-77116e9f-f437-4535-8719-46797dda08ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686210287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3686210287
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4250980468
Short name T319
Test name
Test status
Simulation time 3628665892 ps
CPU time 75.01 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:27:51 PM PDT 24
Peak memory 251172 kb
Host smart-bb228e79-b923-408b-9f3d-37204d4ecd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250980468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4250980468
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3341811177
Short name T241
Test name
Test status
Simulation time 23960516603 ps
CPU time 199.74 seconds
Started Mar 14 01:26:32 PM PDT 24
Finished Mar 14 01:29:52 PM PDT 24
Peak memory 252968 kb
Host smart-3664c52e-bfca-4052-b029-81f9c25d93c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341811177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3341811177
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2327905375
Short name T238
Test name
Test status
Simulation time 14970026176 ps
CPU time 23.07 seconds
Started Mar 14 01:26:43 PM PDT 24
Finished Mar 14 01:27:07 PM PDT 24
Peak memory 236380 kb
Host smart-24b681c7-503e-443f-af15-a951cf0568a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327905375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2327905375
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.346331445
Short name T785
Test name
Test status
Simulation time 3975381982 ps
CPU time 11.45 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:26:49 PM PDT 24
Peak memory 219060 kb
Host smart-254d210a-4618-4ed4-91db-6eb0a32e4aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346331445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.346331445
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3763659226
Short name T913
Test name
Test status
Simulation time 696920191 ps
CPU time 12.16 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:26:47 PM PDT 24
Peak memory 253840 kb
Host smart-4141b784-362c-4c98-bac5-5d6febff3194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763659226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3763659226
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2687102135
Short name T16
Test name
Test status
Simulation time 295207346 ps
CPU time 5.52 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 235740 kb
Host smart-cdc73d41-9a1d-43f6-add9-152ac9fe035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687102135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2687102135
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3308873798
Short name T611
Test name
Test status
Simulation time 10566246332 ps
CPU time 29.8 seconds
Started Mar 14 01:26:34 PM PDT 24
Finished Mar 14 01:27:04 PM PDT 24
Peak memory 233988 kb
Host smart-17003f3f-53b5-4ff2-8e36-d8fe4181d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308873798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3308873798
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.192348905
Short name T500
Test name
Test status
Simulation time 142044654 ps
CPU time 3.67 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:39 PM PDT 24
Peak memory 222576 kb
Host smart-2e1b3b5a-eba3-4cb0-bf67-9c7083263abe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=192348905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.192348905
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2350797202
Short name T223
Test name
Test status
Simulation time 33131443600 ps
CPU time 255.37 seconds
Started Mar 14 01:26:31 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 264844 kb
Host smart-4ea5abf1-0fac-4840-8bd8-597671096aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350797202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2350797202
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3576314345
Short name T254
Test name
Test status
Simulation time 3165365908 ps
CPU time 8.52 seconds
Started Mar 14 01:26:27 PM PDT 24
Finished Mar 14 01:26:36 PM PDT 24
Peak memory 216000 kb
Host smart-3c608e00-1d29-47e8-ba53-fba33cf00917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576314345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3576314345
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3592176958
Short name T607
Test name
Test status
Simulation time 4523940112 ps
CPU time 13.8 seconds
Started Mar 14 01:26:22 PM PDT 24
Finished Mar 14 01:26:36 PM PDT 24
Peak memory 215864 kb
Host smart-a13dbaa4-3b0d-4705-8440-5696a82025cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592176958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3592176958
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.579503359
Short name T655
Test name
Test status
Simulation time 120217055 ps
CPU time 1.72 seconds
Started Mar 14 01:26:33 PM PDT 24
Finished Mar 14 01:26:35 PM PDT 24
Peak memory 215864 kb
Host smart-6363feca-23a3-4ff7-a6b7-481c466ba279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579503359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.579503359
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2692765224
Short name T335
Test name
Test status
Simulation time 78916662 ps
CPU time 0.75 seconds
Started Mar 14 01:26:39 PM PDT 24
Finished Mar 14 01:26:40 PM PDT 24
Peak memory 205204 kb
Host smart-8e4f125e-23a8-4bf4-a11f-8c8f2dddb04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692765224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2692765224
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4012221545
Short name T192
Test name
Test status
Simulation time 505572912 ps
CPU time 5.95 seconds
Started Mar 14 01:26:34 PM PDT 24
Finished Mar 14 01:26:40 PM PDT 24
Peak memory 237252 kb
Host smart-bdfea950-2f2a-4563-ad9b-9d3be681e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012221545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4012221545
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2671545789
Short name T672
Test name
Test status
Simulation time 18001985 ps
CPU time 0.7 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:06 PM PDT 24
Peak memory 205316 kb
Host smart-0db5ee95-d6f3-47d4-8b24-fddbca6a8cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671545789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
671545789
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3745027088
Short name T536
Test name
Test status
Simulation time 914866745 ps
CPU time 3.91 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:11 PM PDT 24
Peak memory 233808 kb
Host smart-679b0104-b79b-4911-afe7-2352811a7f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745027088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3745027088
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1267346690
Short name T14
Test name
Test status
Simulation time 57940985 ps
CPU time 0.78 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:48 PM PDT 24
Peak memory 205020 kb
Host smart-1a4f3de0-2c52-4810-b62d-9b259f904b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267346690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1267346690
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3631212027
Short name T218
Test name
Test status
Simulation time 9402780462 ps
CPU time 86.02 seconds
Started Mar 14 01:24:58 PM PDT 24
Finished Mar 14 01:26:24 PM PDT 24
Peak memory 252844 kb
Host smart-2fce7ed6-6022-43e0-9228-6b6a1993cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631212027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3631212027
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1918835700
Short name T887
Test name
Test status
Simulation time 24981700366 ps
CPU time 172.71 seconds
Started Mar 14 01:24:58 PM PDT 24
Finished Mar 14 01:27:50 PM PDT 24
Peak memory 248864 kb
Host smart-5d830919-b528-4090-a3d1-3d063e39da15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918835700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1918835700
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4190376701
Short name T139
Test name
Test status
Simulation time 169261038458 ps
CPU time 368.84 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:31:10 PM PDT 24
Peak memory 248768 kb
Host smart-a46f516f-7d6b-400b-9238-dea35828f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190376701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4190376701
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.895179907
Short name T513
Test name
Test status
Simulation time 867893334 ps
CPU time 15.52 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:16 PM PDT 24
Peak memory 244040 kb
Host smart-bbdb9392-7cf0-41b8-b956-01ceebd982f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895179907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.895179907
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4133580678
Short name T163
Test name
Test status
Simulation time 1438999081 ps
CPU time 6.37 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:06 PM PDT 24
Peak memory 224068 kb
Host smart-1ef6db0b-82f9-42cb-8bd6-467bb83540e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133580678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4133580678
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3274239271
Short name T665
Test name
Test status
Simulation time 42014515842 ps
CPU time 29.03 seconds
Started Mar 14 01:24:59 PM PDT 24
Finished Mar 14 01:25:28 PM PDT 24
Peak memory 243796 kb
Host smart-7f87e97d-5730-47bb-922e-1708c541debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274239271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3274239271
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3907272009
Short name T678
Test name
Test status
Simulation time 54620533 ps
CPU time 1.06 seconds
Started Mar 14 01:24:50 PM PDT 24
Finished Mar 14 01:24:51 PM PDT 24
Peak memory 216396 kb
Host smart-aaad89ea-73fc-43fd-821e-f8ebc012a1bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907272009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3907272009
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2760007575
Short name T921
Test name
Test status
Simulation time 3794427632 ps
CPU time 14.19 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:19 PM PDT 24
Peak memory 237540 kb
Host smart-ea07f46f-dc74-49b4-bfc2-47711232053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760007575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2760007575
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1443003161
Short name T185
Test name
Test status
Simulation time 749230293 ps
CPU time 5.23 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:07 PM PDT 24
Peak memory 224008 kb
Host smart-32db06b9-550d-4e7c-ac70-3d77ca1c53e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443003161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1443003161
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1167034873
Short name T449
Test name
Test status
Simulation time 17237440 ps
CPU time 0.76 seconds
Started Mar 14 01:24:54 PM PDT 24
Finished Mar 14 01:24:55 PM PDT 24
Peak memory 215812 kb
Host smart-3aed36ca-8c4b-4db0-af7c-1921e9d45e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167034873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1167034873
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.412478782
Short name T261
Test name
Test status
Simulation time 3833017792 ps
CPU time 4.85 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:07 PM PDT 24
Peak memory 220280 kb
Host smart-55ae68c0-6b8e-42c2-a90e-eb58e3e894ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=412478782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.412478782
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4220858917
Short name T62
Test name
Test status
Simulation time 88525388 ps
CPU time 1.2 seconds
Started Mar 14 01:24:59 PM PDT 24
Finished Mar 14 01:25:01 PM PDT 24
Peak memory 236728 kb
Host smart-19972fa0-71eb-4935-93f9-760a22bda9d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220858917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4220858917
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3774382113
Short name T73
Test name
Test status
Simulation time 113977737659 ps
CPU time 201.21 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:28:22 PM PDT 24
Peak memory 268180 kb
Host smart-0ed8bed4-fb83-4df2-86a8-c334cd569bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774382113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3774382113
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2847759837
Short name T589
Test name
Test status
Simulation time 8977597631 ps
CPU time 43.94 seconds
Started Mar 14 01:24:51 PM PDT 24
Finished Mar 14 01:25:35 PM PDT 24
Peak memory 215988 kb
Host smart-bd97a7c3-9c3d-46bf-8505-9cccec904a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847759837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2847759837
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2169566794
Short name T576
Test name
Test status
Simulation time 2815169218 ps
CPU time 7.8 seconds
Started Mar 14 01:24:54 PM PDT 24
Finished Mar 14 01:25:02 PM PDT 24
Peak memory 215832 kb
Host smart-827d3e95-cfc7-454a-8f98-bf1d08a4afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169566794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2169566794
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1977260934
Short name T414
Test name
Test status
Simulation time 133802831 ps
CPU time 1.44 seconds
Started Mar 14 01:24:47 PM PDT 24
Finished Mar 14 01:24:49 PM PDT 24
Peak memory 207700 kb
Host smart-aa58e846-0cdb-4134-8de2-c1647c60a021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977260934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1977260934
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3211126848
Short name T458
Test name
Test status
Simulation time 136702055 ps
CPU time 0.85 seconds
Started Mar 14 01:24:55 PM PDT 24
Finished Mar 14 01:24:56 PM PDT 24
Peak memory 205300 kb
Host smart-17e8ac8a-3970-413f-b583-de81c622c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211126848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3211126848
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3835502681
Short name T832
Test name
Test status
Simulation time 8334444408 ps
CPU time 21.31 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:29 PM PDT 24
Peak memory 220984 kb
Host smart-9349a70f-efe9-4eef-ae4b-3b6b0268454c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835502681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3835502681
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4170977127
Short name T806
Test name
Test status
Simulation time 34895002 ps
CPU time 0.73 seconds
Started Mar 14 01:26:34 PM PDT 24
Finished Mar 14 01:26:35 PM PDT 24
Peak memory 204404 kb
Host smart-5a53723b-0380-4242-a4b2-65cacbc718a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170977127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4170977127
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1550714819
Short name T662
Test name
Test status
Simulation time 124904137 ps
CPU time 2.53 seconds
Started Mar 14 01:26:39 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 216364 kb
Host smart-484d8e78-9103-4f85-8272-80a5081430b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550714819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1550714819
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3812864562
Short name T867
Test name
Test status
Simulation time 149313380 ps
CPU time 0.82 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:37 PM PDT 24
Peak memory 206360 kb
Host smart-176260a6-989a-4857-b61f-1e45661bd9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812864562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3812864562
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1758911016
Short name T871
Test name
Test status
Simulation time 1474882730 ps
CPU time 8.86 seconds
Started Mar 14 01:26:32 PM PDT 24
Finished Mar 14 01:26:41 PM PDT 24
Peak memory 248716 kb
Host smart-90d62e18-9d8d-4266-bc81-f782907381d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758911016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1758911016
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2549487548
Short name T201
Test name
Test status
Simulation time 41431889344 ps
CPU time 300.9 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 240116 kb
Host smart-f4299b69-1040-4c55-907a-52eb879e72f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549487548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2549487548
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2983873480
Short name T778
Test name
Test status
Simulation time 190990420077 ps
CPU time 270.71 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:31:09 PM PDT 24
Peak memory 272532 kb
Host smart-001303fe-f47b-4d89-818c-e6a54c328c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983873480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2983873480
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1627101888
Short name T546
Test name
Test status
Simulation time 1326850692 ps
CPU time 9.6 seconds
Started Mar 14 01:26:33 PM PDT 24
Finished Mar 14 01:26:43 PM PDT 24
Peak memory 240348 kb
Host smart-60d46451-af04-498d-8467-2bab1418a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627101888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1627101888
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4265647768
Short name T496
Test name
Test status
Simulation time 2161985349 ps
CPU time 9.7 seconds
Started Mar 14 01:26:33 PM PDT 24
Finished Mar 14 01:26:43 PM PDT 24
Peak memory 233252 kb
Host smart-3852d2df-0979-4662-a091-f7a2406fb556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265647768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4265647768
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2722998486
Short name T206
Test name
Test status
Simulation time 4172125024 ps
CPU time 10.12 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:26:47 PM PDT 24
Peak memory 237788 kb
Host smart-dac97ae1-b951-40e2-8d91-439e5de88a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722998486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2722998486
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1308154819
Short name T29
Test name
Test status
Simulation time 3990092929 ps
CPU time 5.01 seconds
Started Mar 14 01:26:33 PM PDT 24
Finished Mar 14 01:26:38 PM PDT 24
Peak memory 232352 kb
Host smart-5c5a734f-aa56-4fef-bdc2-d36d572922bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308154819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1308154819
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3176576632
Short name T409
Test name
Test status
Simulation time 629961430 ps
CPU time 5.76 seconds
Started Mar 14 01:26:32 PM PDT 24
Finished Mar 14 01:26:38 PM PDT 24
Peak memory 215980 kb
Host smart-ca90ba71-4da6-4f71-be4b-2148ff9c42ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176576632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3176576632
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.541575520
Short name T110
Test name
Test status
Simulation time 5289521523 ps
CPU time 4.11 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:26:41 PM PDT 24
Peak memory 218424 kb
Host smart-cb5a7701-b338-4140-a2bc-74f0f8835118
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=541575520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.541575520
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2161028887
Short name T675
Test name
Test status
Simulation time 2908516075 ps
CPU time 6.91 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:43 PM PDT 24
Peak memory 215988 kb
Host smart-b5c70815-2a6f-4b24-9b62-0ae7cb19a011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161028887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2161028887
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.63849972
Short name T848
Test name
Test status
Simulation time 75207436 ps
CPU time 1.38 seconds
Started Mar 14 01:26:43 PM PDT 24
Finished Mar 14 01:26:45 PM PDT 24
Peak memory 215900 kb
Host smart-527c8db7-5f06-44ae-8b51-3aa5e1c5ee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63849972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.63849972
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3482399938
Short name T287
Test name
Test status
Simulation time 79879941 ps
CPU time 0.91 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:26:36 PM PDT 24
Peak memory 205300 kb
Host smart-5555406d-30aa-49ed-bfae-455f15b38f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482399938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3482399938
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2393845567
Short name T861
Test name
Test status
Simulation time 381252473 ps
CPU time 6.95 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:43 PM PDT 24
Peak memory 229176 kb
Host smart-c2782a6c-8c4c-480d-8977-067846a41617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393845567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2393845567
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3376928088
Short name T337
Test name
Test status
Simulation time 64808871 ps
CPU time 0.72 seconds
Started Mar 14 01:26:32 PM PDT 24
Finished Mar 14 01:26:33 PM PDT 24
Peak memory 205316 kb
Host smart-811aeb26-080d-4d24-871b-b787929021a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376928088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3376928088
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.497069017
Short name T908
Test name
Test status
Simulation time 16233889560 ps
CPU time 6.5 seconds
Started Mar 14 01:26:39 PM PDT 24
Finished Mar 14 01:26:46 PM PDT 24
Peak memory 233156 kb
Host smart-19bae170-2a8a-47a1-a11a-a71c39e0ee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497069017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.497069017
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.236855591
Short name T252
Test name
Test status
Simulation time 274388781 ps
CPU time 0.8 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:37 PM PDT 24
Peak memory 206080 kb
Host smart-19a7dcc4-8549-4fe2-a9d8-74c2b7c8bb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236855591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.236855591
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2592534532
Short name T560
Test name
Test status
Simulation time 93048362989 ps
CPU time 138.06 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:28:55 PM PDT 24
Peak memory 255616 kb
Host smart-73a7e4ea-c8cb-440a-b4ef-da114dcfaaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592534532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2592534532
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.709387818
Short name T81
Test name
Test status
Simulation time 11787747516 ps
CPU time 79.18 seconds
Started Mar 14 01:26:30 PM PDT 24
Finished Mar 14 01:27:49 PM PDT 24
Peak memory 248612 kb
Host smart-44f20834-d517-4e52-9d02-8e5e27387f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709387818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.709387818
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2889559354
Short name T841
Test name
Test status
Simulation time 7505694319 ps
CPU time 131.25 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:28:49 PM PDT 24
Peak memory 264140 kb
Host smart-f5f253a4-0235-4a47-b5e6-7e7b7730305c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889559354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2889559354
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3138930030
Short name T66
Test name
Test status
Simulation time 777079760 ps
CPU time 9.47 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:45 PM PDT 24
Peak memory 239608 kb
Host smart-47b7a605-35d8-48dd-a7dd-14755648ce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138930030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3138930030
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2522724238
Short name T460
Test name
Test status
Simulation time 284365833 ps
CPU time 3.71 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 232936 kb
Host smart-2b00236c-bc8d-4b5b-b5b4-65e7e14a900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522724238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2522724238
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1895519451
Short name T191
Test name
Test status
Simulation time 3878558872 ps
CPU time 7.2 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:26:45 PM PDT 24
Peak memory 228072 kb
Host smart-05964281-1d90-4451-8be2-c65834855ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895519451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1895519451
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2853782290
Short name T643
Test name
Test status
Simulation time 1513090169 ps
CPU time 4.19 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:26:39 PM PDT 24
Peak memory 236040 kb
Host smart-29a3dcd8-f471-452a-aca3-ce0f0ff7667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853782290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2853782290
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1543464919
Short name T215
Test name
Test status
Simulation time 4295917099 ps
CPU time 10.44 seconds
Started Mar 14 01:26:43 PM PDT 24
Finished Mar 14 01:26:54 PM PDT 24
Peak memory 237192 kb
Host smart-8c04cceb-16be-49d2-b78f-b6cbc2807067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543464919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1543464919
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2752330284
Short name T581
Test name
Test status
Simulation time 1278034806 ps
CPU time 5.92 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:26:44 PM PDT 24
Peak memory 218688 kb
Host smart-b52a4fbf-e261-4522-acc9-d3f2f0d5524b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2752330284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2752330284
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.952755519
Short name T850
Test name
Test status
Simulation time 102647160678 ps
CPU time 231.78 seconds
Started Mar 14 01:26:28 PM PDT 24
Finished Mar 14 01:30:20 PM PDT 24
Peak memory 253124 kb
Host smart-861d54fa-dc0e-41c5-b54b-571ec3710808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952755519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.952755519
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1800082635
Short name T243
Test name
Test status
Simulation time 4791307294 ps
CPU time 41.35 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:27:19 PM PDT 24
Peak memory 215852 kb
Host smart-2830ca41-c897-4425-afe5-b822ea1f2ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800082635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1800082635
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4031570918
Short name T775
Test name
Test status
Simulation time 772990845 ps
CPU time 2.56 seconds
Started Mar 14 01:26:39 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 215608 kb
Host smart-eb441886-154a-4f08-8336-87f8dd98b0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031570918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4031570918
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.905271036
Short name T446
Test name
Test status
Simulation time 415774324 ps
CPU time 2.97 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:26:40 PM PDT 24
Peak memory 215856 kb
Host smart-2efa7e5e-9db7-4bfc-b917-e3a551480ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905271036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.905271036
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.565901625
Short name T929
Test name
Test status
Simulation time 71989341 ps
CPU time 0.83 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:26:39 PM PDT 24
Peak memory 205264 kb
Host smart-41ee2475-05e3-4082-ba08-60dea78438fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565901625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.565901625
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.46500955
Short name T137
Test name
Test status
Simulation time 2092392442 ps
CPU time 4.23 seconds
Started Mar 14 01:26:34 PM PDT 24
Finished Mar 14 01:26:38 PM PDT 24
Peak memory 216300 kb
Host smart-e30872ec-adc0-4125-a21b-a5b5bbf5df27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46500955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.46500955
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2714282513
Short name T813
Test name
Test status
Simulation time 23281011 ps
CPU time 0.71 seconds
Started Mar 14 01:26:43 PM PDT 24
Finished Mar 14 01:26:44 PM PDT 24
Peak memory 204920 kb
Host smart-d8618717-c9b4-4c7b-bf6f-8ab013c3a768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714282513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2714282513
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3432583180
Short name T177
Test name
Test status
Simulation time 2334340998 ps
CPU time 6.65 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 237864 kb
Host smart-3a001082-acf9-464d-b852-2300417c9bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432583180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3432583180
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.454258212
Short name T383
Test name
Test status
Simulation time 43862639 ps
CPU time 0.8 seconds
Started Mar 14 01:26:34 PM PDT 24
Finished Mar 14 01:26:35 PM PDT 24
Peak memory 206384 kb
Host smart-56ed8da4-70bb-41ad-934c-a619e6938af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454258212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.454258212
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.661774803
Short name T127
Test name
Test status
Simulation time 9419015407 ps
CPU time 64.36 seconds
Started Mar 14 01:26:39 PM PDT 24
Finished Mar 14 01:27:44 PM PDT 24
Peak memory 256472 kb
Host smart-383e0c79-c399-4b48-883a-cad0ea2016a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661774803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.661774803
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1782250886
Short name T584
Test name
Test status
Simulation time 3671413152 ps
CPU time 55.54 seconds
Started Mar 14 01:26:43 PM PDT 24
Finished Mar 14 01:27:39 PM PDT 24
Peak memory 249576 kb
Host smart-d0759f3d-e86f-4d23-b695-741562b0c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782250886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1782250886
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1249554983
Short name T429
Test name
Test status
Simulation time 28013054745 ps
CPU time 69.4 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:27:47 PM PDT 24
Peak memory 250384 kb
Host smart-0efab226-c0ea-4eee-ba3f-9ad362a0e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249554983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1249554983
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1419681327
Short name T100
Test name
Test status
Simulation time 11292107293 ps
CPU time 30.26 seconds
Started Mar 14 01:26:33 PM PDT 24
Finished Mar 14 01:27:04 PM PDT 24
Peak memory 248328 kb
Host smart-18e0f67d-acea-4233-9750-c8b4e4a482a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419681327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1419681327
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1504291888
Short name T578
Test name
Test status
Simulation time 2864371817 ps
CPU time 7.11 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 219596 kb
Host smart-1f9eecac-a8e4-4980-9f6f-d5831cc825c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504291888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1504291888
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.414958408
Short name T339
Test name
Test status
Simulation time 32983778131 ps
CPU time 24.75 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:26:59 PM PDT 24
Peak memory 234016 kb
Host smart-f2e3add7-2021-4038-85eb-b9095ce91e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414958408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.414958408
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2667592865
Short name T128
Test name
Test status
Simulation time 5287311259 ps
CPU time 8.73 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:26:47 PM PDT 24
Peak memory 233268 kb
Host smart-496efc57-f9bc-4b4b-a388-9053e8fc992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667592865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2667592865
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.183342601
Short name T595
Test name
Test status
Simulation time 1936051399 ps
CPU time 6.53 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 228104 kb
Host smart-4811845a-555c-4a14-9797-cc66484170ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183342601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.183342601
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1904954453
Short name T286
Test name
Test status
Simulation time 1489663131 ps
CPU time 4.98 seconds
Started Mar 14 01:26:43 PM PDT 24
Finished Mar 14 01:26:49 PM PDT 24
Peak memory 219556 kb
Host smart-8720469b-ade1-4059-aef0-c22366af9c6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1904954453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1904954453
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4053118667
Short name T226
Test name
Test status
Simulation time 393073192497 ps
CPU time 658.18 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:37:36 PM PDT 24
Peak memory 285268 kb
Host smart-975b60b9-2fdb-49e6-b422-be797d182aa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053118667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4053118667
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2872115814
Short name T67
Test name
Test status
Simulation time 12014158891 ps
CPU time 16.32 seconds
Started Mar 14 01:26:33 PM PDT 24
Finished Mar 14 01:26:50 PM PDT 24
Peak memory 215896 kb
Host smart-712a38d5-fa59-4b68-8487-5c1bdd40c3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872115814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2872115814
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.839156501
Short name T674
Test name
Test status
Simulation time 31642686599 ps
CPU time 11.4 seconds
Started Mar 14 01:26:36 PM PDT 24
Finished Mar 14 01:26:48 PM PDT 24
Peak memory 215888 kb
Host smart-ce32a87b-e31d-42d2-8efa-c43778e9201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839156501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.839156501
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3755291771
Short name T364
Test name
Test status
Simulation time 1162953793 ps
CPU time 6.49 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:26:42 PM PDT 24
Peak memory 216040 kb
Host smart-1076ada3-b897-42a5-8da2-20c1c524d924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755291771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3755291771
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1214540629
Short name T94
Test name
Test status
Simulation time 149246425 ps
CPU time 1.26 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:26:38 PM PDT 24
Peak memory 206356 kb
Host smart-8c83f6ee-d784-4368-930b-0df4a6f1485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214540629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1214540629
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1245188618
Short name T27
Test name
Test status
Simulation time 1231181569 ps
CPU time 4.72 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:26:41 PM PDT 24
Peak memory 233444 kb
Host smart-4d254bab-f08e-4422-9501-19cfdf2470a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245188618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1245188618
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3048355172
Short name T253
Test name
Test status
Simulation time 61375623 ps
CPU time 0.72 seconds
Started Mar 14 01:26:50 PM PDT 24
Finished Mar 14 01:26:51 PM PDT 24
Peak memory 204996 kb
Host smart-6ddbb096-53a1-4677-bd87-3965ebb198c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048355172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3048355172
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3278593071
Short name T897
Test name
Test status
Simulation time 315512847 ps
CPU time 3.88 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:26:52 PM PDT 24
Peak memory 224064 kb
Host smart-afc22f45-9ac5-4f87-af54-e5f3c8fc34f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278593071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3278593071
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.182173733
Short name T869
Test name
Test status
Simulation time 16056052 ps
CPU time 0.75 seconds
Started Mar 14 01:26:33 PM PDT 24
Finished Mar 14 01:26:34 PM PDT 24
Peak memory 205272 kb
Host smart-ecf9d9e6-bf3c-4646-9e70-61b45f97902e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182173733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.182173733
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1425966107
Short name T726
Test name
Test status
Simulation time 494725529 ps
CPU time 6.6 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:26:56 PM PDT 24
Peak memory 235432 kb
Host smart-47d18da8-de56-47e0-a769-83c3786b64ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425966107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1425966107
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1386291474
Short name T205
Test name
Test status
Simulation time 8521793377 ps
CPU time 111.54 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:28:43 PM PDT 24
Peak memory 250448 kb
Host smart-50622b63-73c1-4854-b6f4-153522439954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386291474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1386291474
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3379668698
Short name T820
Test name
Test status
Simulation time 4428475672 ps
CPU time 61.57 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:27:50 PM PDT 24
Peak memory 240628 kb
Host smart-e12e50c8-ab17-420d-9774-da4a188c879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379668698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3379668698
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3433402488
Short name T770
Test name
Test status
Simulation time 5314681300 ps
CPU time 27.52 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 240096 kb
Host smart-bfb5728e-6493-4698-ab46-a6cb5346b06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433402488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3433402488
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.246339800
Short name T455
Test name
Test status
Simulation time 688235122 ps
CPU time 4.47 seconds
Started Mar 14 01:26:50 PM PDT 24
Finished Mar 14 01:26:55 PM PDT 24
Peak memory 233848 kb
Host smart-1ba54756-dd59-414b-91a7-87d766cbb498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246339800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.246339800
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3299221172
Short name T134
Test name
Test status
Simulation time 825724398 ps
CPU time 10.37 seconds
Started Mar 14 01:26:53 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 240328 kb
Host smart-22f9cef9-f498-41e3-9f87-4552ac827a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299221172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3299221172
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1299109080
Short name T344
Test name
Test status
Simulation time 843588222 ps
CPU time 3.34 seconds
Started Mar 14 01:26:47 PM PDT 24
Finished Mar 14 01:26:51 PM PDT 24
Peak memory 224056 kb
Host smart-8be2debe-4475-4bb5-8fff-65b71293f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299109080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1299109080
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2981210932
Short name T168
Test name
Test status
Simulation time 472500486 ps
CPU time 7.96 seconds
Started Mar 14 01:26:38 PM PDT 24
Finished Mar 14 01:26:46 PM PDT 24
Peak memory 233820 kb
Host smart-969f54a0-b567-4a7b-b665-82ab3db6fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981210932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2981210932
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2358331858
Short name T279
Test name
Test status
Simulation time 376516743 ps
CPU time 3.47 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:26:52 PM PDT 24
Peak memory 218504 kb
Host smart-00dcd804-f2aa-4aff-8b67-c5b6ba72d782
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358331858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2358331858
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3202377074
Short name T518
Test name
Test status
Simulation time 301746028 ps
CPU time 0.98 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:26:49 PM PDT 24
Peak memory 206388 kb
Host smart-94a84fbf-20cc-4518-adbd-b9297f6cf585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202377074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3202377074
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3757694807
Short name T37
Test name
Test status
Simulation time 50299162168 ps
CPU time 75.56 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 215944 kb
Host smart-a6c0e7ba-92e6-400e-bd58-166b0787d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757694807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3757694807
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3970075073
Short name T585
Test name
Test status
Simulation time 11037257205 ps
CPU time 8.46 seconds
Started Mar 14 01:26:34 PM PDT 24
Finished Mar 14 01:26:43 PM PDT 24
Peak memory 216020 kb
Host smart-b41024c3-4208-4b68-9462-a3e8448b27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970075073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3970075073
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1163294930
Short name T562
Test name
Test status
Simulation time 12813841 ps
CPU time 0.76 seconds
Started Mar 14 01:26:37 PM PDT 24
Finished Mar 14 01:26:37 PM PDT 24
Peak memory 205252 kb
Host smart-03dea5f4-f7e3-4b6c-8147-555d4ad311b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163294930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1163294930
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1609179211
Short name T550
Test name
Test status
Simulation time 92153992 ps
CPU time 0.93 seconds
Started Mar 14 01:26:35 PM PDT 24
Finished Mar 14 01:26:36 PM PDT 24
Peak memory 206360 kb
Host smart-98a753ac-f95c-4afe-afd7-faa73536802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609179211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1609179211
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4017342620
Short name T196
Test name
Test status
Simulation time 353016968 ps
CPU time 7.35 seconds
Started Mar 14 01:26:54 PM PDT 24
Finished Mar 14 01:27:02 PM PDT 24
Peak memory 236580 kb
Host smart-2df48983-7862-4d47-a494-54fe5d386b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017342620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4017342620
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4077118686
Short name T926
Test name
Test status
Simulation time 43976440 ps
CPU time 0.78 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:26:50 PM PDT 24
Peak memory 204824 kb
Host smart-1805a2ef-cc97-4a78-ad6e-20221002d418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077118686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4077118686
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3738614391
Short name T295
Test name
Test status
Simulation time 629439979 ps
CPU time 3.11 seconds
Started Mar 14 01:26:51 PM PDT 24
Finished Mar 14 01:26:54 PM PDT 24
Peak memory 217300 kb
Host smart-4b61f509-c989-496c-a38d-61827200cba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738614391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3738614391
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1440774703
Short name T247
Test name
Test status
Simulation time 50255171 ps
CPU time 0.78 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:26:49 PM PDT 24
Peak memory 205348 kb
Host smart-6796f376-5f25-4ad6-9cd4-1d9c59f98c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440774703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1440774703
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.802223137
Short name T130
Test name
Test status
Simulation time 214727256865 ps
CPU time 295.35 seconds
Started Mar 14 01:26:51 PM PDT 24
Finished Mar 14 01:31:47 PM PDT 24
Peak memory 265120 kb
Host smart-f8fec7c4-77b9-4b45-a6c5-126ce1d31d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802223137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.802223137
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.474653229
Short name T225
Test name
Test status
Simulation time 4832848270 ps
CPU time 69.23 seconds
Started Mar 14 01:26:51 PM PDT 24
Finished Mar 14 01:28:01 PM PDT 24
Peak memory 248420 kb
Host smart-b7d96640-bebd-447b-96b4-fe6d630e10d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474653229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.474653229
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3685058712
Short name T155
Test name
Test status
Simulation time 15760213679 ps
CPU time 130.23 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:29:00 PM PDT 24
Peak memory 253192 kb
Host smart-66ec324f-a217-4cd3-aa6f-884d9e7bf9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685058712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3685058712
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2795754918
Short name T359
Test name
Test status
Simulation time 6393294670 ps
CPU time 31.79 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:27:24 PM PDT 24
Peak memory 247720 kb
Host smart-55ea33e3-97ef-4118-9652-36f77f8bc3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795754918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2795754918
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2939552751
Short name T165
Test name
Test status
Simulation time 38613580038 ps
CPU time 9.39 seconds
Started Mar 14 01:26:56 PM PDT 24
Finished Mar 14 01:27:06 PM PDT 24
Peak memory 235076 kb
Host smart-66c0bd53-22db-4f29-b601-af29d4df2718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939552751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2939552751
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.67308610
Short name T730
Test name
Test status
Simulation time 3540255575 ps
CPU time 10.48 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:26:58 PM PDT 24
Peak memory 233436 kb
Host smart-0aeed642-b708-4a89-874a-50cbc6ef01e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67308610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.67308610
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4041176090
Short name T738
Test name
Test status
Simulation time 6969957433 ps
CPU time 22.46 seconds
Started Mar 14 01:26:50 PM PDT 24
Finished Mar 14 01:27:13 PM PDT 24
Peak memory 238352 kb
Host smart-f5ebf6b8-ce7b-4a53-86b7-023fb6092d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041176090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4041176090
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.545627669
Short name T524
Test name
Test status
Simulation time 5563580262 ps
CPU time 13.12 seconds
Started Mar 14 01:26:51 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 233204 kb
Host smart-e71b07f4-5b94-46ff-94bd-154bee8802b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545627669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.545627669
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1590324530
Short name T329
Test name
Test status
Simulation time 176032015 ps
CPU time 3.59 seconds
Started Mar 14 01:26:51 PM PDT 24
Finished Mar 14 01:26:55 PM PDT 24
Peak memory 218344 kb
Host smart-ef90ee44-9a22-43ca-8104-dd26e76898fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1590324530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1590324530
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.849302863
Short name T873
Test name
Test status
Simulation time 17571735598 ps
CPU time 17.56 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:27:07 PM PDT 24
Peak memory 215944 kb
Host smart-c18bb93c-0a78-4eff-9e4a-6f4452b1e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849302863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.849302863
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1048639564
Short name T475
Test name
Test status
Simulation time 6845765948 ps
CPU time 10.2 seconds
Started Mar 14 01:26:54 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 215848 kb
Host smart-53f16c16-1e0d-4116-8e38-0ff905f62330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048639564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1048639564
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4223000968
Short name T688
Test name
Test status
Simulation time 262845665 ps
CPU time 5.07 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:26:54 PM PDT 24
Peak memory 215924 kb
Host smart-ef8a9605-e148-44da-9ac8-d16a5402861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223000968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4223000968
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2689360933
Short name T783
Test name
Test status
Simulation time 163557253 ps
CPU time 0.92 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:26:50 PM PDT 24
Peak memory 206276 kb
Host smart-ba2ce87f-57c6-498a-aece-528e43f23402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689360933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2689360933
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.337905441
Short name T894
Test name
Test status
Simulation time 45905799 ps
CPU time 2.32 seconds
Started Mar 14 01:26:51 PM PDT 24
Finished Mar 14 01:26:54 PM PDT 24
Peak memory 215900 kb
Host smart-6d506980-6c4b-45c0-888c-6d0bf28c179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337905441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.337905441
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1812645910
Short name T565
Test name
Test status
Simulation time 95674266 ps
CPU time 0.77 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:26:53 PM PDT 24
Peak memory 204424 kb
Host smart-641cea82-68ea-49bb-84f1-ba7b01a8116d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812645910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1812645910
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2279230204
Short name T527
Test name
Test status
Simulation time 162597096 ps
CPU time 2.96 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:26:55 PM PDT 24
Peak memory 234424 kb
Host smart-6eef702a-5050-4574-a873-0889d9c86fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279230204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2279230204
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.395293459
Short name T614
Test name
Test status
Simulation time 25973518 ps
CPU time 0.8 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:26:53 PM PDT 24
Peak memory 206060 kb
Host smart-2e1427c4-80b8-4e8d-b37d-022f5ee87885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395293459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.395293459
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3758614450
Short name T694
Test name
Test status
Simulation time 17853073923 ps
CPU time 66.05 seconds
Started Mar 14 01:26:48 PM PDT 24
Finished Mar 14 01:27:54 PM PDT 24
Peak memory 248780 kb
Host smart-52c12510-cab2-4ee9-b9e0-f633e2917c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758614450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3758614450
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1010603687
Short name T193
Test name
Test status
Simulation time 4922406077 ps
CPU time 99.73 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:28:29 PM PDT 24
Peak memory 253264 kb
Host smart-99f27284-f8b5-4777-b9cf-32a49136d0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010603687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1010603687
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.43200731
Short name T343
Test name
Test status
Simulation time 1381425706 ps
CPU time 16.99 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:27:06 PM PDT 24
Peak memory 239904 kb
Host smart-8d148883-299e-4ce0-aaee-9fbc74ae11c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43200731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.43200731
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3546718738
Short name T444
Test name
Test status
Simulation time 57125650 ps
CPU time 2.4 seconds
Started Mar 14 01:26:54 PM PDT 24
Finished Mar 14 01:26:57 PM PDT 24
Peak memory 232336 kb
Host smart-8d498e88-9e25-4fa7-9cce-1158ea37e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546718738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3546718738
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1786150047
Short name T393
Test name
Test status
Simulation time 9510247797 ps
CPU time 28.11 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:27:17 PM PDT 24
Peak memory 227272 kb
Host smart-5afea476-e281-489f-8d3c-8de36475b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786150047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1786150047
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3401184550
Short name T198
Test name
Test status
Simulation time 35170138 ps
CPU time 2.29 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:26:51 PM PDT 24
Peak memory 232316 kb
Host smart-a8f20a72-07eb-42ee-ac14-e9db4f45fe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401184550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3401184550
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2488681839
Short name T324
Test name
Test status
Simulation time 4743656204 ps
CPU time 15.82 seconds
Started Mar 14 01:26:47 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 239188 kb
Host smart-b0b4b832-6023-4470-b3f4-c687a9ba0a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488681839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2488681839
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.694991174
Short name T541
Test name
Test status
Simulation time 67189823 ps
CPU time 3.48 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:26:56 PM PDT 24
Peak memory 222372 kb
Host smart-51863158-12dc-498f-8a59-21d9682c94f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=694991174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.694991174
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.508112754
Short name T652
Test name
Test status
Simulation time 189103787052 ps
CPU time 327.54 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 254396 kb
Host smart-bb1f8c45-d013-45e9-bbe2-feffbbd24bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508112754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.508112754
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.403301280
Short name T380
Test name
Test status
Simulation time 2299493240 ps
CPU time 37.83 seconds
Started Mar 14 01:26:54 PM PDT 24
Finished Mar 14 01:27:33 PM PDT 24
Peak memory 215948 kb
Host smart-b6eff8a5-04b6-46b4-afb0-2c0c41d3e21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403301280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.403301280
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2405983908
Short name T768
Test name
Test status
Simulation time 976395307 ps
CPU time 7.52 seconds
Started Mar 14 01:26:51 PM PDT 24
Finished Mar 14 01:26:59 PM PDT 24
Peak memory 215844 kb
Host smart-8a603492-0970-49ee-9463-3bbd364517f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405983908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2405983908
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.679901678
Short name T543
Test name
Test status
Simulation time 157495769 ps
CPU time 2.07 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:26:51 PM PDT 24
Peak memory 215880 kb
Host smart-cc6c16ca-ea8a-4b7d-a277-8d25146f3c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679901678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.679901678
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1352122684
Short name T315
Test name
Test status
Simulation time 44858009 ps
CPU time 0.72 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:26:53 PM PDT 24
Peak memory 205332 kb
Host smart-7c50d43c-6062-407a-b2f8-2d6463f5decb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352122684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1352122684
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4030582066
Short name T412
Test name
Test status
Simulation time 2118256376 ps
CPU time 6.74 seconds
Started Mar 14 01:26:54 PM PDT 24
Finished Mar 14 01:27:01 PM PDT 24
Peak memory 233264 kb
Host smart-4d7b241b-7042-41da-aa44-1119bb81b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030582066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4030582066
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1051181972
Short name T804
Test name
Test status
Simulation time 24433442 ps
CPU time 0.8 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:26:53 PM PDT 24
Peak memory 204404 kb
Host smart-5ebbf93a-5570-48e9-bce0-ef5db9c834f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051181972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1051181972
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3977592116
Short name T490
Test name
Test status
Simulation time 1029957673 ps
CPU time 6.97 seconds
Started Mar 14 01:26:50 PM PDT 24
Finished Mar 14 01:26:57 PM PDT 24
Peak memory 219424 kb
Host smart-bffbb484-cb5e-48f8-bf4a-e1121e8dab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977592116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3977592116
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4160845597
Short name T849
Test name
Test status
Simulation time 42008345 ps
CPU time 0.78 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:26:50 PM PDT 24
Peak memory 205016 kb
Host smart-b440cd31-8481-4ae1-a833-46cf6a18c257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160845597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4160845597
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4254606982
Short name T124
Test name
Test status
Simulation time 24958858185 ps
CPU time 131.94 seconds
Started Mar 14 01:26:55 PM PDT 24
Finished Mar 14 01:29:08 PM PDT 24
Peak memory 253628 kb
Host smart-411f4047-55db-4d3a-8ac5-f6a7cf5e73bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254606982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4254606982
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3706496872
Short name T547
Test name
Test status
Simulation time 26049790842 ps
CPU time 45.42 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:27:38 PM PDT 24
Peak memory 248912 kb
Host smart-e1fc5c4c-093f-4d3f-b045-0626769c78d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706496872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3706496872
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2558227926
Short name T639
Test name
Test status
Simulation time 56655053609 ps
CPU time 44.63 seconds
Started Mar 14 01:26:56 PM PDT 24
Finished Mar 14 01:27:41 PM PDT 24
Peak memory 238240 kb
Host smart-0ee6345c-5d76-4283-8d63-eb2a7a039c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558227926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2558227926
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2397726262
Short name T605
Test name
Test status
Simulation time 765944339 ps
CPU time 10.74 seconds
Started Mar 14 01:26:54 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 229276 kb
Host smart-b8384ad3-a4c7-48e2-91b6-6af8f5754bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397726262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2397726262
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.160343734
Short name T450
Test name
Test status
Simulation time 54133564975 ps
CPU time 11.2 seconds
Started Mar 14 01:26:54 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 233924 kb
Host smart-ed828960-134c-4147-87d7-00a77174f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160343734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.160343734
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3162558963
Short name T571
Test name
Test status
Simulation time 1366035159 ps
CPU time 17.47 seconds
Started Mar 14 01:26:50 PM PDT 24
Finished Mar 14 01:27:08 PM PDT 24
Peak memory 248792 kb
Host smart-98f54536-a4a4-4044-9aa4-fd7448254e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162558963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3162558963
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2631818444
Short name T888
Test name
Test status
Simulation time 1248889033 ps
CPU time 6.61 seconds
Started Mar 14 01:26:50 PM PDT 24
Finished Mar 14 01:26:57 PM PDT 24
Peak memory 216248 kb
Host smart-2bde61d3-38cb-47e4-8c17-77a6e522135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631818444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2631818444
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.24856034
Short name T209
Test name
Test status
Simulation time 440765820 ps
CPU time 2.81 seconds
Started Mar 14 01:26:53 PM PDT 24
Finished Mar 14 01:26:56 PM PDT 24
Peak memory 232252 kb
Host smart-7e7b5d6c-797a-47f0-89cc-fd64c86c711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24856034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.24856034
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4207649242
Short name T670
Test name
Test status
Simulation time 273933347 ps
CPU time 3.41 seconds
Started Mar 14 01:26:55 PM PDT 24
Finished Mar 14 01:26:59 PM PDT 24
Peak memory 222372 kb
Host smart-320141f7-d737-4bfd-9420-09d7c1286877
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4207649242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4207649242
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2176032963
Short name T559
Test name
Test status
Simulation time 5611752636 ps
CPU time 10.35 seconds
Started Mar 14 01:26:52 PM PDT 24
Finished Mar 14 01:27:02 PM PDT 24
Peak memory 215932 kb
Host smart-75f82aef-0392-4b87-80e6-cf0460487799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176032963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2176032963
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.710319858
Short name T367
Test name
Test status
Simulation time 2651816322 ps
CPU time 2.21 seconds
Started Mar 14 01:26:47 PM PDT 24
Finished Mar 14 01:26:50 PM PDT 24
Peak memory 215852 kb
Host smart-a0b9e8c0-487e-41e8-a0c6-64238e760838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710319858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.710319858
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1670164695
Short name T817
Test name
Test status
Simulation time 84695869 ps
CPU time 1.98 seconds
Started Mar 14 01:26:54 PM PDT 24
Finished Mar 14 01:26:57 PM PDT 24
Peak memory 215800 kb
Host smart-19ac393c-3979-433f-ac1b-734a3a096006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670164695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1670164695
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3069210803
Short name T300
Test name
Test status
Simulation time 37869883 ps
CPU time 0.85 seconds
Started Mar 14 01:26:50 PM PDT 24
Finished Mar 14 01:26:51 PM PDT 24
Peak memory 205304 kb
Host smart-0505cfa7-efd5-4dd3-8160-9fc17bc6e80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069210803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3069210803
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.29593931
Short name T306
Test name
Test status
Simulation time 8929383420 ps
CPU time 21.83 seconds
Started Mar 14 01:26:49 PM PDT 24
Finished Mar 14 01:27:11 PM PDT 24
Peak memory 246208 kb
Host smart-95f0fecf-71c1-4fcb-b6ad-5f8e2a68d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29593931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.29593931
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3372892010
Short name T54
Test name
Test status
Simulation time 19762989 ps
CPU time 0.84 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 204956 kb
Host smart-d7870bc3-eb8a-4594-8c4f-0222a9c1552c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372892010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3372892010
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2348887686
Short name T612
Test name
Test status
Simulation time 100910733 ps
CPU time 2.27 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 216200 kb
Host smart-4882001e-7e18-4cc1-9094-fe0e01c6e974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348887686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2348887686
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.873840462
Short name T469
Test name
Test status
Simulation time 16093253 ps
CPU time 0.79 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 205012 kb
Host smart-207034d7-4ab5-4ee8-a030-89e670887182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873840462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.873840462
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2326870966
Short name T667
Test name
Test status
Simulation time 11904146782 ps
CPU time 33.57 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:36 PM PDT 24
Peak memory 240520 kb
Host smart-0bbebcfa-d37b-46a5-8b4a-6d7aec335d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326870966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2326870966
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1576009144
Short name T204
Test name
Test status
Simulation time 57148549950 ps
CPU time 143.67 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:29:27 PM PDT 24
Peak memory 256872 kb
Host smart-af99eb71-70b9-4db6-8d3a-350ed3a2b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576009144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1576009144
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1564361503
Short name T516
Test name
Test status
Simulation time 24171153074 ps
CPU time 177.49 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:30:00 PM PDT 24
Peak memory 249888 kb
Host smart-f3f28c55-c827-42ee-9d0b-763dff9c0386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564361503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1564361503
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.594479309
Short name T112
Test name
Test status
Simulation time 21487722466 ps
CPU time 50.58 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 240444 kb
Host smart-44fde872-9692-40f7-be50-44cdc0fe8a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594479309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.594479309
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.327750515
Short name T721
Test name
Test status
Simulation time 20276558286 ps
CPU time 6.12 seconds
Started Mar 14 01:27:06 PM PDT 24
Finished Mar 14 01:27:13 PM PDT 24
Peak memory 233760 kb
Host smart-a03f2d02-4d57-403d-b689-896689148036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327750515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.327750515
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.720220805
Short name T169
Test name
Test status
Simulation time 3876095632 ps
CPU time 11.67 seconds
Started Mar 14 01:26:59 PM PDT 24
Finished Mar 14 01:27:11 PM PDT 24
Peak memory 218060 kb
Host smart-98321dde-51c2-4318-85b8-f76d2df231f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720220805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.720220805
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2902813230
Short name T781
Test name
Test status
Simulation time 36526494894 ps
CPU time 22.69 seconds
Started Mar 14 01:27:00 PM PDT 24
Finished Mar 14 01:27:23 PM PDT 24
Peak memory 218336 kb
Host smart-efd9151b-024e-4d8f-ba78-0467e7447cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902813230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2902813230
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.93206335
Short name T504
Test name
Test status
Simulation time 2092309902 ps
CPU time 6.9 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:08 PM PDT 24
Peak memory 232336 kb
Host smart-b9c0e524-a18a-402d-8671-d308b0059062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93206335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.93206335
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3515297040
Short name T707
Test name
Test status
Simulation time 133673476 ps
CPU time 3.23 seconds
Started Mar 14 01:26:59 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 218280 kb
Host smart-d3994bd1-cbf5-45b0-885a-a9851ed601d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3515297040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3515297040
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2657427373
Short name T636
Test name
Test status
Simulation time 5790083035 ps
CPU time 26.74 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:29 PM PDT 24
Peak memory 216024 kb
Host smart-ae627b53-cf1f-477b-bcb9-0f8028226e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657427373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2657427373
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2579915032
Short name T630
Test name
Test status
Simulation time 1226260968 ps
CPU time 6.39 seconds
Started Mar 14 01:27:00 PM PDT 24
Finished Mar 14 01:27:07 PM PDT 24
Peak memory 215920 kb
Host smart-23e7768e-dcd2-4d02-8c27-66689b805e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579915032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2579915032
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.526351194
Short name T920
Test name
Test status
Simulation time 206460610 ps
CPU time 3.49 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:06 PM PDT 24
Peak memory 215916 kb
Host smart-da1e939c-1954-41b2-bfc8-add9680f639e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526351194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.526351194
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3505966635
Short name T647
Test name
Test status
Simulation time 209043910 ps
CPU time 0.82 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:02 PM PDT 24
Peak memory 205248 kb
Host smart-a70642fc-5aef-4b9e-9bdb-4881d2533e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505966635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3505966635
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1625354292
Short name T856
Test name
Test status
Simulation time 3421493173 ps
CPU time 14.44 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 234220 kb
Host smart-f60eec7d-0e4d-490b-8877-a7aa4207ac48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625354292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1625354292
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.599450785
Short name T69
Test name
Test status
Simulation time 20959014 ps
CPU time 0.72 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:04 PM PDT 24
Peak memory 204980 kb
Host smart-971de957-2df9-4087-aace-04809a53e9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599450785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.599450785
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.207420287
Short name T208
Test name
Test status
Simulation time 6162353669 ps
CPU time 11.97 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 237788 kb
Host smart-6ba9a48c-d66f-48b8-8364-81a08fac5ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207420287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.207420287
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.634103001
Short name T499
Test name
Test status
Simulation time 32120653 ps
CPU time 0.78 seconds
Started Mar 14 01:26:58 PM PDT 24
Finished Mar 14 01:26:59 PM PDT 24
Peak memory 205048 kb
Host smart-f72c260c-cbf4-42b1-b10f-05d3d5ecaf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634103001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.634103001
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.673756961
Short name T222
Test name
Test status
Simulation time 58296648640 ps
CPU time 89.48 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:28:33 PM PDT 24
Peak memory 240528 kb
Host smart-688c9695-72f6-45cc-91b7-5927de83ffbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673756961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.673756961
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2483346585
Short name T839
Test name
Test status
Simulation time 23960063992 ps
CPU time 53.83 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:56 PM PDT 24
Peak memory 250192 kb
Host smart-63f68bb6-2afb-4d5a-b41a-97ab6d330556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483346585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2483346585
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3859540365
Short name T822
Test name
Test status
Simulation time 5240721370 ps
CPU time 95.38 seconds
Started Mar 14 01:27:00 PM PDT 24
Finished Mar 14 01:28:36 PM PDT 24
Peak memory 265192 kb
Host smart-2b70010c-3d25-4f88-8450-e7a6dcc9fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859540365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3859540365
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1723251648
Short name T773
Test name
Test status
Simulation time 1551107635 ps
CPU time 14.23 seconds
Started Mar 14 01:27:08 PM PDT 24
Finished Mar 14 01:27:23 PM PDT 24
Peak memory 235328 kb
Host smart-ce13a905-bbd3-4f9b-a5ec-5c87d1bde039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723251648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1723251648
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4004700564
Short name T141
Test name
Test status
Simulation time 47458174 ps
CPU time 2.62 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:04 PM PDT 24
Peak memory 232816 kb
Host smart-d3ce1a49-2db0-4d54-bd56-6fb0db110c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004700564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4004700564
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2649805463
Short name T766
Test name
Test status
Simulation time 2788921256 ps
CPU time 11.65 seconds
Started Mar 14 01:27:08 PM PDT 24
Finished Mar 14 01:27:20 PM PDT 24
Peak memory 239944 kb
Host smart-aad98be8-7019-40e3-a481-0da7e9af728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649805463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2649805463
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.9314720
Short name T230
Test name
Test status
Simulation time 1627589524 ps
CPU time 8.06 seconds
Started Mar 14 01:27:00 PM PDT 24
Finished Mar 14 01:27:09 PM PDT 24
Peak memory 237140 kb
Host smart-25de22e1-7534-4264-bd62-7c59474f3645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9314720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.9314720
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.105007301
Short name T174
Test name
Test status
Simulation time 10696792700 ps
CPU time 18.51 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:21 PM PDT 24
Peak memory 236248 kb
Host smart-a8146978-7929-419b-b17e-37f131356bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105007301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.105007301
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1294229454
Short name T641
Test name
Test status
Simulation time 1387507804 ps
CPU time 3.98 seconds
Started Mar 14 01:27:06 PM PDT 24
Finished Mar 14 01:27:10 PM PDT 24
Peak memory 219544 kb
Host smart-ff15b81d-4808-4916-942d-6adeba484269
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1294229454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1294229454
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2274576676
Short name T4
Test name
Test status
Simulation time 15614779608 ps
CPU time 32.56 seconds
Started Mar 14 01:27:00 PM PDT 24
Finished Mar 14 01:27:34 PM PDT 24
Peak memory 249916 kb
Host smart-598d616b-1bfc-485f-81b9-d9209ff56446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274576676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2274576676
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.832211544
Short name T36
Test name
Test status
Simulation time 51663792555 ps
CPU time 58.07 seconds
Started Mar 14 01:26:59 PM PDT 24
Finished Mar 14 01:27:57 PM PDT 24
Peak memory 215952 kb
Host smart-275f95c7-25d8-490d-95d6-910065c0055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832211544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.832211544
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4044422181
Short name T290
Test name
Test status
Simulation time 597860455 ps
CPU time 4.34 seconds
Started Mar 14 01:27:00 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 215856 kb
Host smart-7dec949c-1321-49e5-a0bb-79ba37421d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044422181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4044422181
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1272052888
Short name T575
Test name
Test status
Simulation time 1842603137 ps
CPU time 5.05 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:07 PM PDT 24
Peak memory 216064 kb
Host smart-6ed0c359-b37c-43d5-b93d-b9cbe05d5f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272052888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1272052888
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.787178355
Short name T440
Test name
Test status
Simulation time 288352094 ps
CPU time 0.79 seconds
Started Mar 14 01:26:59 PM PDT 24
Finished Mar 14 01:27:01 PM PDT 24
Peak memory 205308 kb
Host smart-a9a1df85-8a66-4373-9c3c-ebeba653ab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787178355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.787178355
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3166786731
Short name T333
Test name
Test status
Simulation time 35671046797 ps
CPU time 55.94 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:59 PM PDT 24
Peak memory 246728 kb
Host smart-ad86c648-2d22-404c-a87f-5c419cb3ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166786731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3166786731
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3645545291
Short name T55
Test name
Test status
Simulation time 10809295 ps
CPU time 0.75 seconds
Started Mar 14 01:27:04 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 204996 kb
Host smart-149663a7-5a60-41ee-bc90-cac97e6c4c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645545291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3645545291
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.467515473
Short name T549
Test name
Test status
Simulation time 5355054026 ps
CPU time 4.75 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:06 PM PDT 24
Peak memory 224156 kb
Host smart-64e18350-4e75-4dab-9918-7576821ec950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467515473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.467515473
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1673247520
Short name T400
Test name
Test status
Simulation time 37234091 ps
CPU time 0.78 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:04 PM PDT 24
Peak memory 206052 kb
Host smart-bc9812ce-0af7-4b8c-bb56-68e788cc487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673247520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1673247520
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1974452095
Short name T497
Test name
Test status
Simulation time 2961371073 ps
CPU time 31.06 seconds
Started Mar 14 01:27:04 PM PDT 24
Finished Mar 14 01:27:35 PM PDT 24
Peak memory 242696 kb
Host smart-7425fb4a-060c-487a-b74e-e26cb682e0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974452095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1974452095
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2738735717
Short name T905
Test name
Test status
Simulation time 28603530495 ps
CPU time 35.67 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:39 PM PDT 24
Peak memory 234548 kb
Host smart-f3b2252d-ce6e-4540-8935-afcac8bc2bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738735717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2738735717
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3165125553
Short name T772
Test name
Test status
Simulation time 18108898690 ps
CPU time 32.02 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:35 PM PDT 24
Peak memory 234072 kb
Host smart-14a5a218-f268-4287-94d2-d11858239918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165125553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3165125553
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2252210190
Short name T554
Test name
Test status
Simulation time 1630444338 ps
CPU time 15.03 seconds
Started Mar 14 01:27:05 PM PDT 24
Finished Mar 14 01:27:20 PM PDT 24
Peak memory 239980 kb
Host smart-7996ee5b-0b22-4e80-8d36-2f8f872512b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252210190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2252210190
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1115982255
Short name T71
Test name
Test status
Simulation time 2780591814 ps
CPU time 6.69 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:22 PM PDT 24
Peak memory 233068 kb
Host smart-e5c1d2d1-c4a2-4aac-a5fc-0d52fb5c1df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115982255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1115982255
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1912789477
Short name T86
Test name
Test status
Simulation time 573463842 ps
CPU time 6.51 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:10 PM PDT 24
Peak memory 238572 kb
Host smart-2c5de83f-fe05-41e8-b4b4-f7945205501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912789477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1912789477
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4145804563
Short name T126
Test name
Test status
Simulation time 18894387113 ps
CPU time 18.84 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:34 PM PDT 24
Peak memory 232384 kb
Host smart-a0848efb-59e1-44c2-a674-b15876698920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145804563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4145804563
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2475484375
Short name T836
Test name
Test status
Simulation time 6565350332 ps
CPU time 23.1 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:27 PM PDT 24
Peak memory 224092 kb
Host smart-3e0751a0-2ad4-46ba-b74e-09de60a2475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475484375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2475484375
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1058321232
Short name T476
Test name
Test status
Simulation time 242566015 ps
CPU time 3.97 seconds
Started Mar 14 01:27:05 PM PDT 24
Finished Mar 14 01:27:09 PM PDT 24
Peak memory 221888 kb
Host smart-f5778471-b5f4-4ced-998c-f2994b3e6d87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1058321232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1058321232
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.876381324
Short name T805
Test name
Test status
Simulation time 355833581640 ps
CPU time 678.71 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:38:20 PM PDT 24
Peak memory 289780 kb
Host smart-d5a32790-42d7-45e6-8ce9-14599477b123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876381324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.876381324
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.84379714
Short name T92
Test name
Test status
Simulation time 7379419765 ps
CPU time 13.48 seconds
Started Mar 14 01:27:10 PM PDT 24
Finished Mar 14 01:27:24 PM PDT 24
Peak memory 215964 kb
Host smart-2898d04b-01f3-4efe-80e3-1ea598ea1d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84379714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.84379714
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2222320547
Short name T404
Test name
Test status
Simulation time 10219444432 ps
CPU time 9.54 seconds
Started Mar 14 01:27:10 PM PDT 24
Finished Mar 14 01:27:20 PM PDT 24
Peak memory 215956 kb
Host smart-34f8a4d9-2f8d-4af9-b221-845a8aa7dace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222320547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2222320547
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3639556177
Short name T572
Test name
Test status
Simulation time 14515096 ps
CPU time 0.98 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:17 PM PDT 24
Peak memory 206532 kb
Host smart-2a91f8d0-b4e2-4183-8770-e1080261f854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639556177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3639556177
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1342141414
Short name T771
Test name
Test status
Simulation time 38947167 ps
CPU time 0.83 seconds
Started Mar 14 01:27:10 PM PDT 24
Finished Mar 14 01:27:11 PM PDT 24
Peak memory 205264 kb
Host smart-f45ca344-02f0-4434-aa7d-aba57187590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342141414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1342141414
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4204792807
Short name T681
Test name
Test status
Simulation time 7525702986 ps
CPU time 7.81 seconds
Started Mar 14 01:27:04 PM PDT 24
Finished Mar 14 01:27:12 PM PDT 24
Peak memory 218552 kb
Host smart-6ade5ec1-36f5-49a6-99eb-e0877d8f2588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204792807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4204792807
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.650072760
Short name T931
Test name
Test status
Simulation time 14084945 ps
CPU time 0.76 seconds
Started Mar 14 01:25:03 PM PDT 24
Finished Mar 14 01:25:04 PM PDT 24
Peak memory 204984 kb
Host smart-e6e107b7-9582-46eb-8e59-225bf99d2ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650072760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.650072760
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1608802473
Short name T211
Test name
Test status
Simulation time 35387707 ps
CPU time 2.35 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:07 PM PDT 24
Peak memory 233832 kb
Host smart-b85050f0-bf97-47de-a879-3f0dea65536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608802473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1608802473
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.453390371
Short name T262
Test name
Test status
Simulation time 19935240 ps
CPU time 0.8 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:08 PM PDT 24
Peak memory 206076 kb
Host smart-9717390b-5bdc-40cf-abab-4aa05c1d4195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453390371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.453390371
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3182908605
Short name T898
Test name
Test status
Simulation time 355362820901 ps
CPU time 160.03 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:27:47 PM PDT 24
Peak memory 253120 kb
Host smart-43708c50-6768-4e87-817f-71c89315851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182908605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3182908605
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2098782930
Short name T668
Test name
Test status
Simulation time 16440627311 ps
CPU time 57.03 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:58 PM PDT 24
Peak memory 248836 kb
Host smart-43957d2a-d05d-4094-9d4c-ee75acdeb5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098782930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2098782930
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2964380321
Short name T156
Test name
Test status
Simulation time 5369624561 ps
CPU time 30.7 seconds
Started Mar 14 01:24:58 PM PDT 24
Finished Mar 14 01:25:29 PM PDT 24
Peak memory 221780 kb
Host smart-2cbaf6f1-e54e-4f72-8b94-2a78e5710aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964380321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2964380321
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1822357879
Short name T606
Test name
Test status
Simulation time 2696422255 ps
CPU time 19.05 seconds
Started Mar 14 01:24:59 PM PDT 24
Finished Mar 14 01:25:18 PM PDT 24
Peak memory 236440 kb
Host smart-9a7bb7a8-79a5-4cdc-a2fb-e49a91abbdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822357879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1822357879
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1370079481
Short name T285
Test name
Test status
Simulation time 122609938 ps
CPU time 2.56 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:04 PM PDT 24
Peak memory 232348 kb
Host smart-49339f1c-be1a-4301-8d62-bf841a40c42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370079481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1370079481
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2478608554
Short name T173
Test name
Test status
Simulation time 1679399176 ps
CPU time 7.68 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:10 PM PDT 24
Peak memory 233492 kb
Host smart-92e0477e-366b-4cb7-8706-3d3f261be2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478608554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2478608554
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4236446535
Short name T917
Test name
Test status
Simulation time 94260587 ps
CPU time 1.12 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:03 PM PDT 24
Peak memory 216416 kb
Host smart-2e82efc2-cba0-4ab7-8fdd-12205d26d049
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236446535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4236446535
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.459072366
Short name T216
Test name
Test status
Simulation time 1333222986 ps
CPU time 10.5 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:18 PM PDT 24
Peak memory 246552 kb
Host smart-80d48d26-5782-428e-967e-bf9784eb8559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459072366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
459072366
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3221730350
Short name T555
Test name
Test status
Simulation time 1630974813 ps
CPU time 6.87 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:08 PM PDT 24
Peak memory 216120 kb
Host smart-478a7ad2-a739-4262-b3bf-bb56da6b312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221730350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3221730350
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2332872673
Short name T401
Test name
Test status
Simulation time 17321745 ps
CPU time 0.74 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:06 PM PDT 24
Peak memory 215912 kb
Host smart-f3489344-8ad5-4939-a9fc-bdfb65957ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332872673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2332872673
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1137256090
Short name T709
Test name
Test status
Simulation time 1183035593 ps
CPU time 4.3 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:09 PM PDT 24
Peak memory 221628 kb
Host smart-aca01ee8-50d2-402a-9cb6-ea1c9b8dd5ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1137256090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1137256090
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.130185352
Short name T64
Test name
Test status
Simulation time 252173593 ps
CPU time 1.13 seconds
Started Mar 14 01:24:59 PM PDT 24
Finished Mar 14 01:25:00 PM PDT 24
Peak memory 235216 kb
Host smart-4951ade7-b58d-4c77-8d78-87cda1b193c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130185352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.130185352
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2989946809
Short name T6
Test name
Test status
Simulation time 29719108221 ps
CPU time 180.13 seconds
Started Mar 14 01:24:57 PM PDT 24
Finished Mar 14 01:27:58 PM PDT 24
Peak memory 251384 kb
Host smart-4ea00ef0-4347-4d68-88c6-0b4860425c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989946809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2989946809
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1481906413
Short name T779
Test name
Test status
Simulation time 17073718357 ps
CPU time 26.91 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:28 PM PDT 24
Peak memory 215912 kb
Host smart-35bec1ff-a6ff-4ba8-b271-0d4ca27f34a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481906413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1481906413
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2528219186
Short name T443
Test name
Test status
Simulation time 42900765576 ps
CPU time 23.98 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:25 PM PDT 24
Peak memory 216028 kb
Host smart-ce38b713-23fb-462c-b10d-00f8ee1ec5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528219186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2528219186
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1594070644
Short name T618
Test name
Test status
Simulation time 170261052 ps
CPU time 3.55 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:11 PM PDT 24
Peak memory 216036 kb
Host smart-dcb7bcd1-1957-4e64-8b23-005de4b9dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594070644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1594070644
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1766123032
Short name T658
Test name
Test status
Simulation time 118058518 ps
CPU time 0.84 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:06 PM PDT 24
Peak memory 205392 kb
Host smart-e29b4323-1fe4-4535-aebb-3c9ff230b8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766123032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1766123032
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1632296017
Short name T132
Test name
Test status
Simulation time 82839680 ps
CPU time 2.61 seconds
Started Mar 14 01:25:08 PM PDT 24
Finished Mar 14 01:25:11 PM PDT 24
Peak memory 224104 kb
Host smart-0452bd38-4f8c-4d45-b8e8-9763049e956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632296017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1632296017
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1528169077
Short name T765
Test name
Test status
Simulation time 58207875 ps
CPU time 0.73 seconds
Started Mar 14 01:27:04 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 205208 kb
Host smart-aba2b465-9953-4ade-b1ac-db6aef5d3ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528169077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1528169077
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1195088936
Short name T885
Test name
Test status
Simulation time 1932090984 ps
CPU time 6.18 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:10 PM PDT 24
Peak memory 219280 kb
Host smart-dfe3d417-0bf5-4a23-8eaa-826b411332ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195088936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1195088936
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4026839776
Short name T916
Test name
Test status
Simulation time 31943441 ps
CPU time 0.79 seconds
Started Mar 14 01:26:58 PM PDT 24
Finished Mar 14 01:26:59 PM PDT 24
Peak memory 205076 kb
Host smart-20ca1eb2-0516-49e9-9f93-53608a4320dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026839776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4026839776
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2746937756
Short name T761
Test name
Test status
Simulation time 213090626358 ps
CPU time 259.34 seconds
Started Mar 14 01:27:05 PM PDT 24
Finished Mar 14 01:31:24 PM PDT 24
Peak memory 248756 kb
Host smart-cc20a438-2d63-48f6-8147-d46b8668cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746937756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2746937756
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2200303011
Short name T87
Test name
Test status
Simulation time 96717663035 ps
CPU time 171.98 seconds
Started Mar 14 01:27:10 PM PDT 24
Finished Mar 14 01:30:02 PM PDT 24
Peak memory 232416 kb
Host smart-38175701-8f7a-486c-b199-6160c747ed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200303011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2200303011
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.271599547
Short name T76
Test name
Test status
Simulation time 27139495264 ps
CPU time 185.54 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:30:21 PM PDT 24
Peak memory 248844 kb
Host smart-c7724cf0-4203-4a8c-a906-4ebc7a5fba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271599547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.271599547
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.465779775
Short name T109
Test name
Test status
Simulation time 5543292911 ps
CPU time 31.29 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:34 PM PDT 24
Peak memory 246952 kb
Host smart-33e4fdf1-4fa4-44b2-b30b-64e04ba53767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465779775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.465779775
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2533058628
Short name T597
Test name
Test status
Simulation time 4022541257 ps
CPU time 10.71 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:14 PM PDT 24
Peak memory 224056 kb
Host smart-34a12622-e873-4640-b9ed-5f9781804c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533058628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2533058628
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4094960500
Short name T250
Test name
Test status
Simulation time 1894827266 ps
CPU time 5.27 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:21 PM PDT 24
Peak memory 224120 kb
Host smart-f94bfa6c-7da2-4007-8454-4e844f368395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094960500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4094960500
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1259865285
Short name T533
Test name
Test status
Simulation time 1076652760 ps
CPU time 7.98 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:11 PM PDT 24
Peak memory 218044 kb
Host smart-7ac996ed-27ee-4446-b194-577dddd4bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259865285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1259865285
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2239128718
Short name T868
Test name
Test status
Simulation time 8316696675 ps
CPU time 14.37 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 232792 kb
Host smart-26b6c315-e5ef-4999-b65c-1d98db7b898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239128718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2239128718
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.355710382
Short name T535
Test name
Test status
Simulation time 1307652279 ps
CPU time 4.3 seconds
Started Mar 14 01:27:10 PM PDT 24
Finished Mar 14 01:27:14 PM PDT 24
Peak memory 219528 kb
Host smart-5113e886-66a6-44a0-8a82-0fcbf6a66ca1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355710382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.355710382
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2460109152
Short name T1
Test name
Test status
Simulation time 186523602 ps
CPU time 1.27 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 206392 kb
Host smart-34e06bc7-3267-4bc0-92aa-49141368d47b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460109152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2460109152
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.753060739
Short name T588
Test name
Test status
Simulation time 3187756701 ps
CPU time 11.72 seconds
Started Mar 14 01:27:04 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 216008 kb
Host smart-051e4586-227c-48e4-88db-14bf1967a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753060739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.753060739
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2110909014
Short name T377
Test name
Test status
Simulation time 2756654103 ps
CPU time 12.06 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 215892 kb
Host smart-fa5ea83c-1f65-434f-a88b-8f309b48a396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110909014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2110909014
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3270259565
Short name T284
Test name
Test status
Simulation time 86703437 ps
CPU time 0.92 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:04 PM PDT 24
Peak memory 205976 kb
Host smart-13bf4f4c-edf6-409e-af21-eec98b1c7749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270259565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3270259565
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1967352122
Short name T577
Test name
Test status
Simulation time 61897015 ps
CPU time 0.92 seconds
Started Mar 14 01:27:02 PM PDT 24
Finished Mar 14 01:27:03 PM PDT 24
Peak memory 205268 kb
Host smart-20e49a1e-1256-42bc-af94-e3d1bd60c41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967352122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1967352122
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1687125097
Short name T118
Test name
Test status
Simulation time 9077150591 ps
CPU time 11.7 seconds
Started Mar 14 01:27:10 PM PDT 24
Finished Mar 14 01:27:22 PM PDT 24
Peak memory 232948 kb
Host smart-09d78a14-4c9c-4bde-90b6-980c91a8df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687125097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1687125097
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3906468158
Short name T336
Test name
Test status
Simulation time 18062805 ps
CPU time 0.77 seconds
Started Mar 14 01:27:14 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 205388 kb
Host smart-a74611c0-3b8c-4bf8-a26e-16af500d8c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906468158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3906468158
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1154858414
Short name T491
Test name
Test status
Simulation time 5277548950 ps
CPU time 6.73 seconds
Started Mar 14 01:27:08 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 219412 kb
Host smart-957e5ac7-c88e-4065-af2d-b4a6bd754633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154858414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1154858414
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1926775644
Short name T656
Test name
Test status
Simulation time 136316359 ps
CPU time 0.78 seconds
Started Mar 14 01:27:04 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 206380 kb
Host smart-710368d9-e1b2-459d-a141-e9ccd9989d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926775644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1926775644
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4044382663
Short name T740
Test name
Test status
Simulation time 22007233303 ps
CPU time 60.38 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:28:04 PM PDT 24
Peak memory 248760 kb
Host smart-5ad9b0ae-4240-417c-8daa-314b396a2fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044382663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4044382663
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2794223811
Short name T361
Test name
Test status
Simulation time 36693857012 ps
CPU time 118.82 seconds
Started Mar 14 01:27:22 PM PDT 24
Finished Mar 14 01:29:21 PM PDT 24
Peak memory 254828 kb
Host smart-5eb02e78-4667-4adc-9584-d78e72d39b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794223811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2794223811
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3040254309
Short name T227
Test name
Test status
Simulation time 111788610082 ps
CPU time 227.95 seconds
Started Mar 14 01:27:19 PM PDT 24
Finished Mar 14 01:31:08 PM PDT 24
Peak memory 262680 kb
Host smart-64dcc5b6-0133-4888-a638-5b036c2f1e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040254309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3040254309
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3200934971
Short name T420
Test name
Test status
Simulation time 31534327920 ps
CPU time 44.51 seconds
Started Mar 14 01:27:03 PM PDT 24
Finished Mar 14 01:27:48 PM PDT 24
Peak memory 246968 kb
Host smart-38406fc6-9d3e-4596-90ec-154efa2700e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200934971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3200934971
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2993035079
Short name T874
Test name
Test status
Simulation time 1403524890 ps
CPU time 6.26 seconds
Started Mar 14 01:27:08 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 233300 kb
Host smart-4d6372c5-576e-4c4f-b002-1ae8fc88d171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993035079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2993035079
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1098687451
Short name T379
Test name
Test status
Simulation time 12485718568 ps
CPU time 21.82 seconds
Started Mar 14 01:27:05 PM PDT 24
Finished Mar 14 01:27:27 PM PDT 24
Peak memory 224108 kb
Host smart-251c0b92-7e58-47b0-9e7d-a3d8589baf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098687451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1098687451
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3719129343
Short name T48
Test name
Test status
Simulation time 75203264321 ps
CPU time 45.4 seconds
Started Mar 14 01:27:07 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 239456 kb
Host smart-9a7c7e8a-f407-4fca-a73e-24ec2ad9efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719129343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3719129343
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2680826672
Short name T673
Test name
Test status
Simulation time 17952669253 ps
CPU time 14.17 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:30 PM PDT 24
Peak memory 239028 kb
Host smart-18c6d1e0-b65f-4933-9004-5cc868ce9934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680826672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2680826672
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4278357230
Short name T52
Test name
Test status
Simulation time 3899171856 ps
CPU time 5.64 seconds
Started Mar 14 01:27:01 PM PDT 24
Finished Mar 14 01:27:07 PM PDT 24
Peak memory 222000 kb
Host smart-c9cc60a0-31ed-40a6-bb0d-65cd20489f66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4278357230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4278357230
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3170708112
Short name T528
Test name
Test status
Simulation time 195178805 ps
CPU time 1.13 seconds
Started Mar 14 01:27:13 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 206604 kb
Host smart-c62651e3-1954-4fff-836c-7ddb04956504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170708112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3170708112
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.4045485062
Short name T308
Test name
Test status
Simulation time 8458271828 ps
CPU time 53.37 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 216024 kb
Host smart-f9c45a3d-7db7-463f-92b8-4050160e9b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045485062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4045485062
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1372932550
Short name T251
Test name
Test status
Simulation time 2303213638 ps
CPU time 11.51 seconds
Started Mar 14 01:27:05 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 215956 kb
Host smart-1dd252f4-906e-49e7-a3d9-b7024f7b1630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372932550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1372932550
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.9188162
Short name T280
Test name
Test status
Simulation time 61005086 ps
CPU time 0.93 seconds
Started Mar 14 01:27:05 PM PDT 24
Finished Mar 14 01:27:06 PM PDT 24
Peak memory 206520 kb
Host smart-6e5bdaeb-ac1c-4294-a089-28023a277f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9188162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.9188162
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.610576737
Short name T569
Test name
Test status
Simulation time 122376138 ps
CPU time 0.93 seconds
Started Mar 14 01:27:04 PM PDT 24
Finished Mar 14 01:27:05 PM PDT 24
Peak memory 205844 kb
Host smart-847df984-2ce2-48a8-b253-0df31e467337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610576737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.610576737
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1593163365
Short name T434
Test name
Test status
Simulation time 8157676795 ps
CPU time 7.83 seconds
Started Mar 14 01:27:08 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 218420 kb
Host smart-b14159ce-01d6-47b7-ae19-462586ffceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593163365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1593163365
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1904617810
Short name T521
Test name
Test status
Simulation time 31045289 ps
CPU time 0.73 seconds
Started Mar 14 01:27:20 PM PDT 24
Finished Mar 14 01:27:21 PM PDT 24
Peak memory 204364 kb
Host smart-9f056515-1c04-476d-abd0-edbb12ef7ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904617810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1904617810
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3479172727
Short name T567
Test name
Test status
Simulation time 211720138 ps
CPU time 3.5 seconds
Started Mar 14 01:27:22 PM PDT 24
Finished Mar 14 01:27:26 PM PDT 24
Peak memory 233108 kb
Host smart-c6072a2c-b0f6-49a4-917c-fca9aa74e9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479172727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3479172727
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1789179084
Short name T620
Test name
Test status
Simulation time 20514153 ps
CPU time 0.75 seconds
Started Mar 14 01:27:11 PM PDT 24
Finished Mar 14 01:27:12 PM PDT 24
Peak memory 206392 kb
Host smart-3e3d0fe8-2717-4cce-b854-b61232fb3d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789179084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1789179084
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1616390690
Short name T644
Test name
Test status
Simulation time 9220738283 ps
CPU time 46.73 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:28:02 PM PDT 24
Peak memory 251344 kb
Host smart-5b4ab47d-6aae-48a4-961e-5ae82f47e666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616390690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1616390690
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1667230902
Short name T146
Test name
Test status
Simulation time 13714685568 ps
CPU time 95.4 seconds
Started Mar 14 01:27:18 PM PDT 24
Finished Mar 14 01:28:54 PM PDT 24
Peak memory 250632 kb
Host smart-f4015665-83ba-43e0-821a-4c59e8ae54f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667230902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1667230902
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3600676843
Short name T769
Test name
Test status
Simulation time 2408423427 ps
CPU time 20.59 seconds
Started Mar 14 01:27:14 PM PDT 24
Finished Mar 14 01:27:35 PM PDT 24
Peak memory 232300 kb
Host smart-a92aa0f0-b26b-4f04-a00d-c51075e71588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600676843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3600676843
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3122533574
Short name T213
Test name
Test status
Simulation time 1030154961 ps
CPU time 3.53 seconds
Started Mar 14 01:27:10 PM PDT 24
Finished Mar 14 01:27:14 PM PDT 24
Peak memory 233896 kb
Host smart-19165ae4-567c-4179-822f-b5695d0e35d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122533574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3122533574
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.789126104
Short name T837
Test name
Test status
Simulation time 5360270338 ps
CPU time 11.07 seconds
Started Mar 14 01:27:14 PM PDT 24
Finished Mar 14 01:27:26 PM PDT 24
Peak memory 231492 kb
Host smart-0fd779db-0318-43e6-935a-06b145d609b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789126104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.789126104
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3308013788
Short name T220
Test name
Test status
Simulation time 1303707600 ps
CPU time 4 seconds
Started Mar 14 01:27:19 PM PDT 24
Finished Mar 14 01:27:23 PM PDT 24
Peak memory 224080 kb
Host smart-a6b04e8a-c64c-4834-8888-376cade4ccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308013788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3308013788
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2678331779
Short name T326
Test name
Test status
Simulation time 585127317 ps
CPU time 6.52 seconds
Started Mar 14 01:27:22 PM PDT 24
Finished Mar 14 01:27:29 PM PDT 24
Peak memory 219132 kb
Host smart-4d62e19f-4e45-4690-a3e8-5be4b7e1bdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678331779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2678331779
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2583783019
Short name T788
Test name
Test status
Simulation time 714896406 ps
CPU time 5.25 seconds
Started Mar 14 01:27:19 PM PDT 24
Finished Mar 14 01:27:24 PM PDT 24
Peak memory 221852 kb
Host smart-c80e9a8c-a398-4d4d-bbe4-ac8ea1dec973
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2583783019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2583783019
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3841138040
Short name T197
Test name
Test status
Simulation time 90392902455 ps
CPU time 273.75 seconds
Started Mar 14 01:27:19 PM PDT 24
Finished Mar 14 01:31:54 PM PDT 24
Peak memory 285148 kb
Host smart-6a8a2d02-387d-4502-bdd4-4cd83ae67e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841138040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3841138040
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3594357780
Short name T374
Test name
Test status
Simulation time 439127453 ps
CPU time 4.08 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:19 PM PDT 24
Peak memory 215964 kb
Host smart-d4b822ba-447c-421f-a1ba-3831ca57a552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594357780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3594357780
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2733469464
Short name T747
Test name
Test status
Simulation time 4895352808 ps
CPU time 6.05 seconds
Started Mar 14 01:27:16 PM PDT 24
Finished Mar 14 01:27:22 PM PDT 24
Peak memory 215904 kb
Host smart-a2aaa7ad-7d39-4bb7-aa7c-20df7b8d4802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733469464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2733469464
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1173760300
Short name T664
Test name
Test status
Simulation time 202446744 ps
CPU time 1.73 seconds
Started Mar 14 01:27:13 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 215872 kb
Host smart-9fa1b19c-83c8-4bf5-8560-89d7248b3c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173760300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1173760300
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.38528583
Short name T687
Test name
Test status
Simulation time 46160169 ps
CPU time 0.77 seconds
Started Mar 14 01:27:13 PM PDT 24
Finished Mar 14 01:27:14 PM PDT 24
Peak memory 205240 kb
Host smart-d4b713a3-fe70-49c6-b44d-023d6ebf5e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38528583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.38528583
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1736367941
Short name T879
Test name
Test status
Simulation time 8790712628 ps
CPU time 32.96 seconds
Started Mar 14 01:27:13 PM PDT 24
Finished Mar 14 01:27:46 PM PDT 24
Peak memory 218764 kb
Host smart-cfc5c894-1140-46e6-b228-90a324109298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736367941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1736367941
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1242161131
Short name T800
Test name
Test status
Simulation time 13775096 ps
CPU time 0.74 seconds
Started Mar 14 01:27:18 PM PDT 24
Finished Mar 14 01:27:20 PM PDT 24
Peak memory 204960 kb
Host smart-e5d52602-0d7f-43ea-a1ff-bb4e06d78540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242161131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1242161131
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4201852666
Short name T212
Test name
Test status
Simulation time 547933299 ps
CPU time 3.5 seconds
Started Mar 14 01:27:13 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 236328 kb
Host smart-adb9a0bd-c8be-4474-9b61-de0ec761f242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201852666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4201852666
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2291242205
Short name T390
Test name
Test status
Simulation time 138687797 ps
CPU time 0.76 seconds
Started Mar 14 01:27:18 PM PDT 24
Finished Mar 14 01:27:19 PM PDT 24
Peak memory 205340 kb
Host smart-62f8d813-8eee-4061-825a-2cb955380b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291242205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2291242205
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3673648890
Short name T304
Test name
Test status
Simulation time 97289641813 ps
CPU time 184.92 seconds
Started Mar 14 01:27:20 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 256592 kb
Host smart-757b9924-c856-4db1-ba7a-fa69858186c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673648890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3673648890
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2658489685
Short name T462
Test name
Test status
Simulation time 6597731804 ps
CPU time 48.82 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:28:04 PM PDT 24
Peak memory 248868 kb
Host smart-10d54c15-a248-4649-ae2b-8bb0ddc97afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658489685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2658489685
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3535008244
Short name T235
Test name
Test status
Simulation time 161041050256 ps
CPU time 484.75 seconds
Started Mar 14 01:27:18 PM PDT 24
Finished Mar 14 01:35:23 PM PDT 24
Peak memory 265016 kb
Host smart-9cc7bc2f-4843-4865-a0d0-de9b1869b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535008244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3535008244
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2925001608
Short name T824
Test name
Test status
Simulation time 401552218 ps
CPU time 4.02 seconds
Started Mar 14 01:27:14 PM PDT 24
Finished Mar 14 01:27:18 PM PDT 24
Peak memory 233348 kb
Host smart-7a399ce6-53cd-4078-82e4-4acf90d47487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925001608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2925001608
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.193444779
Short name T829
Test name
Test status
Simulation time 24501020050 ps
CPU time 19.87 seconds
Started Mar 14 01:27:12 PM PDT 24
Finished Mar 14 01:27:32 PM PDT 24
Peak memory 224048 kb
Host smart-7bb31679-d7e3-41c3-8d00-36067c3c8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193444779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.193444779
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3012265115
Short name T626
Test name
Test status
Simulation time 13132606597 ps
CPU time 8.21 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:23 PM PDT 24
Peak memory 233152 kb
Host smart-7531f021-91ea-4170-80b5-174c29177eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012265115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3012265115
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1822151730
Short name T385
Test name
Test status
Simulation time 17890949706 ps
CPU time 24.99 seconds
Started Mar 14 01:27:16 PM PDT 24
Finished Mar 14 01:27:41 PM PDT 24
Peak memory 232740 kb
Host smart-849ffd70-161c-419f-bc48-4072818bda7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822151730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1822151730
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2860449587
Short name T350
Test name
Test status
Simulation time 5806317726 ps
CPU time 5.84 seconds
Started Mar 14 01:27:12 PM PDT 24
Finished Mar 14 01:27:18 PM PDT 24
Peak memory 222520 kb
Host smart-18af3140-41f7-4864-8ec7-59ebffeecc04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2860449587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2860449587
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1921981706
Short name T231
Test name
Test status
Simulation time 7675161076 ps
CPU time 94.5 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:28:50 PM PDT 24
Peak memory 250824 kb
Host smart-c733b9a8-be80-47c5-a880-6d801627f5ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921981706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1921981706
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1401664736
Short name T471
Test name
Test status
Simulation time 643770634 ps
CPU time 7.59 seconds
Started Mar 14 01:27:20 PM PDT 24
Finished Mar 14 01:27:27 PM PDT 24
Peak memory 215948 kb
Host smart-81f8b81b-cd4c-44ef-9c07-ef1fc791d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401664736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1401664736
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.166392378
Short name T282
Test name
Test status
Simulation time 1175368696 ps
CPU time 3.74 seconds
Started Mar 14 01:27:12 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 215912 kb
Host smart-95bfcb1a-34fd-4ce8-b4cd-7799c8eaf004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166392378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.166392378
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1185538812
Short name T596
Test name
Test status
Simulation time 67354062 ps
CPU time 1.45 seconds
Started Mar 14 01:27:19 PM PDT 24
Finished Mar 14 01:27:21 PM PDT 24
Peak memory 215860 kb
Host smart-055b1497-a0c6-4956-93f0-1860b0ac488d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185538812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1185538812
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4000949690
Short name T85
Test name
Test status
Simulation time 46060016 ps
CPU time 0.91 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 205588 kb
Host smart-16a8611a-2a36-47b7-8e5d-2e74c647163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000949690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4000949690
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1839644136
Short name T859
Test name
Test status
Simulation time 29336114656 ps
CPU time 17.8 seconds
Started Mar 14 01:27:22 PM PDT 24
Finished Mar 14 01:27:40 PM PDT 24
Peak memory 233196 kb
Host smart-cbb95d2a-04e5-4895-bda1-0c713469bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839644136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1839644136
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3182808361
Short name T13
Test name
Test status
Simulation time 13178158 ps
CPU time 0.75 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:27:34 PM PDT 24
Peak memory 205388 kb
Host smart-c99728f8-a3d0-4066-8e34-a7722e156826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182808361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3182808361
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1081277727
Short name T794
Test name
Test status
Simulation time 586468977 ps
CPU time 3.28 seconds
Started Mar 14 01:27:14 PM PDT 24
Finished Mar 14 01:27:18 PM PDT 24
Peak memory 235508 kb
Host smart-971ed921-b08c-4ac2-9236-615bd4a6b0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081277727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1081277727
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.140198712
Short name T886
Test name
Test status
Simulation time 18736945 ps
CPU time 0.77 seconds
Started Mar 14 01:27:18 PM PDT 24
Finished Mar 14 01:27:19 PM PDT 24
Peak memory 206384 kb
Host smart-f9499163-77b2-4e7b-9b12-9363633ee1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140198712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.140198712
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4266018958
Short name T153
Test name
Test status
Simulation time 2811735640 ps
CPU time 44.27 seconds
Started Mar 14 01:27:19 PM PDT 24
Finished Mar 14 01:28:03 PM PDT 24
Peak memory 238844 kb
Host smart-382108bb-62a8-462b-92fb-2aa0dc84f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266018958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4266018958
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2978974902
Short name T928
Test name
Test status
Simulation time 30531088532 ps
CPU time 267.38 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:31:43 PM PDT 24
Peak memory 271636 kb
Host smart-e54c6d8e-57ba-439f-b03d-a80b1bf03932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978974902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2978974902
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4138625647
Short name T358
Test name
Test status
Simulation time 126472671349 ps
CPU time 240.99 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:31:17 PM PDT 24
Peak memory 259048 kb
Host smart-6369a7e2-fa32-4317-bd89-eeee76943b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138625647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4138625647
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3978094592
Short name T236
Test name
Test status
Simulation time 1667902729 ps
CPU time 15.52 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:31 PM PDT 24
Peak memory 246464 kb
Host smart-ca2c2a8c-36ca-422a-b597-25abb7dbbf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978094592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3978094592
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3377756245
Short name T695
Test name
Test status
Simulation time 207692919 ps
CPU time 3.3 seconds
Started Mar 14 01:27:14 PM PDT 24
Finished Mar 14 01:27:17 PM PDT 24
Peak memory 224140 kb
Host smart-40716ecf-77bf-4e33-b2be-4d31a99978d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377756245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3377756245
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3364003552
Short name T171
Test name
Test status
Simulation time 1725234940 ps
CPU time 8.42 seconds
Started Mar 14 01:27:12 PM PDT 24
Finished Mar 14 01:27:20 PM PDT 24
Peak memory 243052 kb
Host smart-0ae0851c-479a-4f36-8eb3-bb5c06d4c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364003552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3364003552
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2273025839
Short name T121
Test name
Test status
Simulation time 3191485309 ps
CPU time 4.09 seconds
Started Mar 14 01:27:22 PM PDT 24
Finished Mar 14 01:27:26 PM PDT 24
Peak memory 218212 kb
Host smart-0d4883c4-68cb-47b5-a58a-95b804585a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273025839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2273025839
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2372107412
Short name T833
Test name
Test status
Simulation time 327804474 ps
CPU time 3.76 seconds
Started Mar 14 01:27:16 PM PDT 24
Finished Mar 14 01:27:21 PM PDT 24
Peak memory 218660 kb
Host smart-f1090148-afcf-488e-8329-f9a933922ff5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372107412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2372107412
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1303009095
Short name T105
Test name
Test status
Simulation time 12960793088 ps
CPU time 65.68 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:28:20 PM PDT 24
Peak memory 248776 kb
Host smart-bab1e70f-80ee-43bd-a478-76cc78b335c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303009095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1303009095
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4092423300
Short name T368
Test name
Test status
Simulation time 7052047720 ps
CPU time 35.45 seconds
Started Mar 14 01:27:22 PM PDT 24
Finished Mar 14 01:27:58 PM PDT 24
Peak memory 215956 kb
Host smart-65a1a15f-36dc-4bb5-8f1d-0fc2c2e88395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092423300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4092423300
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1919693425
Short name T580
Test name
Test status
Simulation time 8350920913 ps
CPU time 19.87 seconds
Started Mar 14 01:27:20 PM PDT 24
Finished Mar 14 01:27:40 PM PDT 24
Peak memory 215860 kb
Host smart-7b409410-fb30-48aa-a87f-7b6a029bc1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919693425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1919693425
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1521020261
Short name T680
Test name
Test status
Simulation time 257938919 ps
CPU time 1.18 seconds
Started Mar 14 01:27:13 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 215944 kb
Host smart-31a8316e-0875-4d93-8fb1-c41525c6b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521020261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1521020261
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1035037681
Short name T263
Test name
Test status
Simulation time 278940652 ps
CPU time 1.06 seconds
Started Mar 14 01:27:10 PM PDT 24
Finished Mar 14 01:27:11 PM PDT 24
Peak memory 206304 kb
Host smart-a4d4c46e-8fc2-4c5b-b4e9-ee0e585180ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035037681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1035037681
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1657799493
Short name T413
Test name
Test status
Simulation time 993885442 ps
CPU time 5.58 seconds
Started Mar 14 01:27:15 PM PDT 24
Finished Mar 14 01:27:20 PM PDT 24
Peak memory 218060 kb
Host smart-34aeaf95-27ad-48a2-a258-adcb2b6ea3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657799493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1657799493
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.836046816
Short name T821
Test name
Test status
Simulation time 27576678 ps
CPU time 0.71 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:27:33 PM PDT 24
Peak memory 205328 kb
Host smart-10cfde72-f569-44e6-81bf-d1e20b930373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836046816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.836046816
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3319982262
Short name T692
Test name
Test status
Simulation time 446448866 ps
CPU time 3.46 seconds
Started Mar 14 01:27:31 PM PDT 24
Finished Mar 14 01:27:36 PM PDT 24
Peak memory 219064 kb
Host smart-9eb194e8-4353-4787-916f-7be026e02129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319982262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3319982262
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2287405926
Short name T389
Test name
Test status
Simulation time 15657519 ps
CPU time 0.78 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:35 PM PDT 24
Peak memory 206392 kb
Host smart-c7a9725a-00f5-4164-9f43-b9a32bca3c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287405926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2287405926
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4186654997
Short name T89
Test name
Test status
Simulation time 98207288228 ps
CPU time 213.05 seconds
Started Mar 14 01:27:35 PM PDT 24
Finished Mar 14 01:31:08 PM PDT 24
Peak memory 240428 kb
Host smart-c4c69046-2e30-4b71-a5a3-b94e425476bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186654997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4186654997
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4115776540
Short name T166
Test name
Test status
Simulation time 34211309273 ps
CPU time 56.41 seconds
Started Mar 14 01:27:38 PM PDT 24
Finished Mar 14 01:28:34 PM PDT 24
Peak memory 224192 kb
Host smart-9cb7dddc-bde9-421a-a548-aaeeae972725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115776540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4115776540
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1562317825
Short name T75
Test name
Test status
Simulation time 965099881 ps
CPU time 14.89 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:27:48 PM PDT 24
Peak memory 221584 kb
Host smart-985ca660-d1ad-42a1-b1a6-8408c9624e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562317825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1562317825
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2306620307
Short name T320
Test name
Test status
Simulation time 3768215416 ps
CPU time 26.32 seconds
Started Mar 14 01:27:38 PM PDT 24
Finished Mar 14 01:28:05 PM PDT 24
Peak memory 240596 kb
Host smart-8cec71f6-4f2f-4cc3-90ee-d7003fb80cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306620307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2306620307
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.999678440
Short name T96
Test name
Test status
Simulation time 538546810 ps
CPU time 3.05 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:37 PM PDT 24
Peak memory 218040 kb
Host smart-494fbedd-6009-4d02-81bc-727b4ecdc176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999678440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.999678440
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.622434248
Short name T763
Test name
Test status
Simulation time 57449117946 ps
CPU time 39.84 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:28:13 PM PDT 24
Peak memory 248796 kb
Host smart-b6b70f0a-fe58-49af-b9f1-c936a0144432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622434248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.622434248
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1130997959
Short name T144
Test name
Test status
Simulation time 4524760021 ps
CPU time 5.08 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:27:38 PM PDT 24
Peak memory 233452 kb
Host smart-2aa65375-dc46-4ade-bdf7-de93bdce7401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130997959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1130997959
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2304696080
Short name T751
Test name
Test status
Simulation time 571524947 ps
CPU time 4.24 seconds
Started Mar 14 01:27:31 PM PDT 24
Finished Mar 14 01:27:37 PM PDT 24
Peak memory 233088 kb
Host smart-ca1643bf-d3eb-4c24-aeeb-8f61a8ddfce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304696080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2304696080
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1732379507
Short name T714
Test name
Test status
Simulation time 272858604 ps
CPU time 3.37 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:27:37 PM PDT 24
Peak memory 222496 kb
Host smart-01e7ecdd-de76-4527-9564-05033f7101da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1732379507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1732379507
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2819959760
Short name T556
Test name
Test status
Simulation time 17089914183 ps
CPU time 73.32 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:28:47 PM PDT 24
Peak memory 249236 kb
Host smart-070633f4-ff6e-4b80-9740-add9001213ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819959760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2819959760
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3744990044
Short name T790
Test name
Test status
Simulation time 500132678 ps
CPU time 6.88 seconds
Started Mar 14 01:27:31 PM PDT 24
Finished Mar 14 01:27:39 PM PDT 24
Peak memory 215964 kb
Host smart-59b4f7c6-5469-4862-ab73-d34495794cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744990044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3744990044
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.821473597
Short name T311
Test name
Test status
Simulation time 21355584625 ps
CPU time 19.03 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 215884 kb
Host smart-ce6cd1e1-5917-48fc-afdb-c5a044baf667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821473597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.821473597
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2933993256
Short name T853
Test name
Test status
Simulation time 306030806 ps
CPU time 2.57 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:27:35 PM PDT 24
Peak memory 216240 kb
Host smart-c7243d6e-9607-45d2-b44b-dc4af3ba1357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933993256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2933993256
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.414418609
Short name T737
Test name
Test status
Simulation time 31557723 ps
CPU time 0.74 seconds
Started Mar 14 01:27:34 PM PDT 24
Finished Mar 14 01:27:35 PM PDT 24
Peak memory 205340 kb
Host smart-4877a756-241d-4d7f-a8ce-5c4b8de99d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414418609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.414418609
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2003328345
Short name T935
Test name
Test status
Simulation time 1513130405 ps
CPU time 7.35 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:27:40 PM PDT 24
Peak memory 234988 kb
Host smart-c3402098-2151-4e32-ae3d-27fed2d2b49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003328345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2003328345
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3645891944
Short name T278
Test name
Test status
Simulation time 57599959 ps
CPU time 0.71 seconds
Started Mar 14 01:27:34 PM PDT 24
Finished Mar 14 01:27:35 PM PDT 24
Peak memory 204416 kb
Host smart-972f92a2-a820-4e50-8122-0b1fc9625791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645891944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3645891944
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.897459865
Short name T840
Test name
Test status
Simulation time 8541582455 ps
CPU time 5.33 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:39 PM PDT 24
Peak memory 233440 kb
Host smart-67bea09c-3a5f-4a2f-a6c9-a98886da414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897459865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.897459865
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.836151690
Short name T702
Test name
Test status
Simulation time 17128284 ps
CPU time 0.83 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:34 PM PDT 24
Peak memory 206056 kb
Host smart-bf3909c6-a0f2-4965-9451-c01bdaf46137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836151690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.836151690
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3800409872
Short name T511
Test name
Test status
Simulation time 3867717042 ps
CPU time 56.48 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:28:30 PM PDT 24
Peak memory 255892 kb
Host smart-cc44ed70-44d0-4fd3-a380-b1dcbb34537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800409872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3800409872
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.357204007
Short name T834
Test name
Test status
Simulation time 31839502645 ps
CPU time 46.39 seconds
Started Mar 14 01:27:40 PM PDT 24
Finished Mar 14 01:28:26 PM PDT 24
Peak memory 236532 kb
Host smart-a3281568-fa19-4386-9679-2c926e2e632f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357204007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.357204007
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1744605395
Short name T39
Test name
Test status
Simulation time 4030272797 ps
CPU time 38.9 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 236128 kb
Host smart-f87022bb-eb07-4ad3-9c6a-1618b8bfbb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744605395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1744605395
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_intercept.83227845
Short name T256
Test name
Test status
Simulation time 186405004 ps
CPU time 2.94 seconds
Started Mar 14 01:27:42 PM PDT 24
Finished Mar 14 01:27:45 PM PDT 24
Peak memory 233292 kb
Host smart-d574bbfe-70aa-402b-a633-8ce1c462caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83227845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.83227845
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.293497252
Short name T629
Test name
Test status
Simulation time 1667528359 ps
CPU time 3.2 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:36 PM PDT 24
Peak memory 232312 kb
Host smart-dadcb422-0e5b-4691-80e6-72657f1d6347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293497252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.293497252
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2246015780
Short name T24
Test name
Test status
Simulation time 1231539762 ps
CPU time 10.08 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:44 PM PDT 24
Peak memory 236604 kb
Host smart-f8df55a8-97eb-4257-8287-95cdee40f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246015780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2246015780
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2908384066
Short name T637
Test name
Test status
Simulation time 625230892 ps
CPU time 8.2 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:41 PM PDT 24
Peak memory 229124 kb
Host smart-6be2b949-817c-4d95-be93-9649f3ccda9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908384066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2908384066
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3234967902
Short name T346
Test name
Test status
Simulation time 245895473 ps
CPU time 3.21 seconds
Started Mar 14 01:27:32 PM PDT 24
Finished Mar 14 01:27:36 PM PDT 24
Peak memory 218796 kb
Host smart-192d2176-fec3-4155-ae56-c8aed6508a11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3234967902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3234967902
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3316729396
Short name T28
Test name
Test status
Simulation time 99253939 ps
CPU time 1.16 seconds
Started Mar 14 01:27:44 PM PDT 24
Finished Mar 14 01:27:45 PM PDT 24
Peak memory 206544 kb
Host smart-5b852481-ef6d-4af5-a5f4-90ec933a85d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316729396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3316729396
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.683899941
Short name T619
Test name
Test status
Simulation time 6922480498 ps
CPU time 17.96 seconds
Started Mar 14 01:27:42 PM PDT 24
Finished Mar 14 01:28:00 PM PDT 24
Peak memory 215928 kb
Host smart-631faef4-93ca-4175-a2a8-ece6473c498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683899941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.683899941
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2956946786
Short name T582
Test name
Test status
Simulation time 1233650906 ps
CPU time 2.59 seconds
Started Mar 14 01:27:39 PM PDT 24
Finished Mar 14 01:27:42 PM PDT 24
Peak memory 215592 kb
Host smart-e7c78328-ffdc-40ce-8417-dd0ec10553ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956946786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2956946786
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2476843662
Short name T803
Test name
Test status
Simulation time 328400688 ps
CPU time 1.52 seconds
Started Mar 14 01:27:39 PM PDT 24
Finished Mar 14 01:27:41 PM PDT 24
Peak memory 215780 kb
Host smart-4fbbd81f-3737-4fd4-880e-c022f532646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476843662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2476843662
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1699588614
Short name T872
Test name
Test status
Simulation time 153658863 ps
CPU time 0.89 seconds
Started Mar 14 01:27:35 PM PDT 24
Finished Mar 14 01:27:36 PM PDT 24
Peak memory 205168 kb
Host smart-bd3296cc-b843-46f1-a173-1d458cb3325f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699588614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1699588614
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2940107385
Short name T698
Test name
Test status
Simulation time 390751592 ps
CPU time 7.94 seconds
Started Mar 14 01:27:33 PM PDT 24
Finished Mar 14 01:27:41 PM PDT 24
Peak memory 240456 kb
Host smart-5f7a31c2-fac5-41a3-a3e9-609fb447bca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940107385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2940107385
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.105701298
Short name T332
Test name
Test status
Simulation time 14293075 ps
CPU time 0.73 seconds
Started Mar 14 01:27:41 PM PDT 24
Finished Mar 14 01:27:42 PM PDT 24
Peak memory 204948 kb
Host smart-963eeb54-6d8c-479a-bf5f-fb1053d00492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105701298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.105701298
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2316942181
Short name T445
Test name
Test status
Simulation time 1745508503 ps
CPU time 7.39 seconds
Started Mar 14 01:27:41 PM PDT 24
Finished Mar 14 01:27:48 PM PDT 24
Peak memory 232920 kb
Host smart-611bbede-4b0b-4641-83c6-2c8290d6bdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316942181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2316942181
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1944618065
Short name T354
Test name
Test status
Simulation time 66272540 ps
CPU time 0.81 seconds
Started Mar 14 01:27:40 PM PDT 24
Finished Mar 14 01:27:41 PM PDT 24
Peak memory 206372 kb
Host smart-2b34d1ed-176d-4d8f-ac66-8f82f3458492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944618065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1944618065
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2318418043
Short name T70
Test name
Test status
Simulation time 4711051755 ps
CPU time 20.9 seconds
Started Mar 14 01:27:44 PM PDT 24
Finished Mar 14 01:28:05 PM PDT 24
Peak memory 218708 kb
Host smart-da943aa4-70c6-4ece-9666-401956751d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318418043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2318418043
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1664976966
Short name T470
Test name
Test status
Simulation time 2625124386 ps
CPU time 48.83 seconds
Started Mar 14 01:27:42 PM PDT 24
Finished Mar 14 01:28:31 PM PDT 24
Peak memory 248780 kb
Host smart-77a00fdd-7330-4bd4-a567-e3833f030753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664976966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1664976966
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3262290131
Short name T51
Test name
Test status
Simulation time 14092080890 ps
CPU time 37.65 seconds
Started Mar 14 01:27:43 PM PDT 24
Finished Mar 14 01:28:21 PM PDT 24
Peak memory 234992 kb
Host smart-2faff2c0-eaad-457b-abc9-8b401dd80ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262290131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3262290131
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3123808545
Short name T530
Test name
Test status
Simulation time 1069770026 ps
CPU time 14.27 seconds
Started Mar 14 01:27:42 PM PDT 24
Finished Mar 14 01:27:56 PM PDT 24
Peak memory 240468 kb
Host smart-d33882b1-72e3-4203-bece-308527e9e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123808545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3123808545
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3815926408
Short name T561
Test name
Test status
Simulation time 11444195928 ps
CPU time 10.88 seconds
Started Mar 14 01:27:41 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 217916 kb
Host smart-52a4d397-ea97-4f30-878e-a0d55a9ddd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815926408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3815926408
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2981060952
Short name T161
Test name
Test status
Simulation time 759558766 ps
CPU time 9.31 seconds
Started Mar 14 01:27:42 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 228888 kb
Host smart-667d2a7a-8529-4825-af20-345a261e3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981060952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2981060952
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1320823502
Short name T899
Test name
Test status
Simulation time 124390956 ps
CPU time 2.5 seconds
Started Mar 14 01:27:41 PM PDT 24
Finished Mar 14 01:27:43 PM PDT 24
Peak memory 218136 kb
Host smart-586fd1e6-46ba-49be-a892-38b8057182a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320823502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1320823502
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1587461524
Short name T748
Test name
Test status
Simulation time 3764752623 ps
CPU time 11.62 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:57 PM PDT 24
Peak memory 232700 kb
Host smart-0529647e-8949-4954-ad78-122b8fd2ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587461524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1587461524
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3830964403
Short name T356
Test name
Test status
Simulation time 1829387015 ps
CPU time 6.6 seconds
Started Mar 14 01:27:39 PM PDT 24
Finished Mar 14 01:27:46 PM PDT 24
Peak memory 219308 kb
Host smart-3520527c-cb27-41c8-a807-675601e38bf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3830964403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3830964403
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3432953250
Short name T242
Test name
Test status
Simulation time 3948545027 ps
CPU time 28.08 seconds
Started Mar 14 01:27:36 PM PDT 24
Finished Mar 14 01:28:04 PM PDT 24
Peak memory 215960 kb
Host smart-9d9f4bc5-06b0-49a1-adff-0313d0029387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432953250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3432953250
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4225944225
Short name T852
Test name
Test status
Simulation time 1833142594 ps
CPU time 4.14 seconds
Started Mar 14 01:27:39 PM PDT 24
Finished Mar 14 01:27:44 PM PDT 24
Peak memory 215836 kb
Host smart-2f00b0d7-aef5-43ad-b8f2-caecdbac6997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225944225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4225944225
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3345000617
Short name T901
Test name
Test status
Simulation time 75653622 ps
CPU time 0.91 seconds
Started Mar 14 01:27:36 PM PDT 24
Finished Mar 14 01:27:37 PM PDT 24
Peak memory 205516 kb
Host smart-61c0bbb0-5f58-4dfc-98ee-8b7bd0464a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345000617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3345000617
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1030126799
Short name T671
Test name
Test status
Simulation time 315570240 ps
CPU time 0.96 seconds
Started Mar 14 01:27:42 PM PDT 24
Finished Mar 14 01:27:43 PM PDT 24
Peak memory 206316 kb
Host smart-336d950b-a79d-49c6-8e3b-201a653016e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030126799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1030126799
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.462479121
Short name T125
Test name
Test status
Simulation time 4317055700 ps
CPU time 16.27 seconds
Started Mar 14 01:27:39 PM PDT 24
Finished Mar 14 01:27:55 PM PDT 24
Peak memory 233788 kb
Host smart-1b55d759-83f3-4865-9859-dfadf0751ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462479121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.462479121
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.595329379
Short name T349
Test name
Test status
Simulation time 37345793 ps
CPU time 0.74 seconds
Started Mar 14 01:27:39 PM PDT 24
Finished Mar 14 01:27:40 PM PDT 24
Peak memory 204920 kb
Host smart-35abc032-d535-43b3-b1f2-0188273213ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595329379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.595329379
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2507284244
Short name T830
Test name
Test status
Simulation time 3313636436 ps
CPU time 4.27 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:51 PM PDT 24
Peak memory 219896 kb
Host smart-6b63c550-1a0f-42c2-b64d-9e9a3b4c66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507284244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2507284244
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4126466455
Short name T810
Test name
Test status
Simulation time 54252225 ps
CPU time 0.79 seconds
Started Mar 14 01:27:44 PM PDT 24
Finished Mar 14 01:27:45 PM PDT 24
Peak memory 205320 kb
Host smart-b99dd298-454f-412c-9ba1-e31cf7c24249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126466455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4126466455
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2047029485
Short name T357
Test name
Test status
Simulation time 24150545669 ps
CPU time 33.27 seconds
Started Mar 14 01:27:40 PM PDT 24
Finished Mar 14 01:28:14 PM PDT 24
Peak memory 236660 kb
Host smart-11f0c189-2ca3-4273-8efe-8e605a3a8450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047029485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2047029485
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2207523003
Short name T479
Test name
Test status
Simulation time 88849646986 ps
CPU time 269.27 seconds
Started Mar 14 01:27:43 PM PDT 24
Finished Mar 14 01:32:13 PM PDT 24
Peak memory 256012 kb
Host smart-7e90fea8-771d-422e-8da9-5166ac8ba697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207523003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2207523003
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3936176202
Short name T791
Test name
Test status
Simulation time 2919847675 ps
CPU time 47.17 seconds
Started Mar 14 01:27:42 PM PDT 24
Finished Mar 14 01:28:30 PM PDT 24
Peak memory 238968 kb
Host smart-55767bac-33d0-49ea-b889-f17e4cbdafd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936176202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3936176202
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2915118589
Short name T237
Test name
Test status
Simulation time 20681479419 ps
CPU time 25.33 seconds
Started Mar 14 01:27:41 PM PDT 24
Finished Mar 14 01:28:07 PM PDT 24
Peak memory 232312 kb
Host smart-54cbb92a-2c59-40b4-903c-004c0a306a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915118589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2915118589
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1013546821
Short name T180
Test name
Test status
Simulation time 430211643 ps
CPU time 2.47 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:49 PM PDT 24
Peak memory 217372 kb
Host smart-4e4301e1-7797-4962-b2ff-2be7ceba6cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013546821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1013546821
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3794121901
Short name T924
Test name
Test status
Simulation time 4825799796 ps
CPU time 8.34 seconds
Started Mar 14 01:27:43 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 240532 kb
Host smart-818e1e95-e14f-41e1-81e3-bf4e432e6e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794121901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3794121901
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2962622151
Short name T353
Test name
Test status
Simulation time 252248196 ps
CPU time 5.28 seconds
Started Mar 14 01:27:39 PM PDT 24
Finished Mar 14 01:27:44 PM PDT 24
Peak memory 240272 kb
Host smart-7edec144-fde7-47cc-905a-a8b1919ec7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962622151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2962622151
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2970210174
Short name T175
Test name
Test status
Simulation time 1411969465 ps
CPU time 5.81 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 240152 kb
Host smart-2c5962cd-3c3b-498f-b779-f19ce9f74e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970210174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2970210174
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.717653946
Short name T325
Test name
Test status
Simulation time 2888154570 ps
CPU time 4.95 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:51 PM PDT 24
Peak memory 218836 kb
Host smart-55a7af59-c3bb-4b4e-abca-0f87f0955b0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=717653946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.717653946
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.945630754
Short name T384
Test name
Test status
Simulation time 44741186604 ps
CPU time 47.12 seconds
Started Mar 14 01:27:39 PM PDT 24
Finished Mar 14 01:28:26 PM PDT 24
Peak memory 215924 kb
Host smart-3b6fc650-61de-44a4-a09f-944411588940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945630754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.945630754
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1910744190
Short name T732
Test name
Test status
Simulation time 3087778727 ps
CPU time 7.53 seconds
Started Mar 14 01:27:42 PM PDT 24
Finished Mar 14 01:27:50 PM PDT 24
Peak memory 215908 kb
Host smart-4cd2a873-d673-4522-9f07-538672b785a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910744190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1910744190
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1049815177
Short name T557
Test name
Test status
Simulation time 323563022 ps
CPU time 2.76 seconds
Started Mar 14 01:27:44 PM PDT 24
Finished Mar 14 01:27:47 PM PDT 24
Peak memory 215912 kb
Host smart-540d5c72-67f5-46c6-b5bf-090d3b3d9294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049815177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1049815177
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.513792810
Short name T809
Test name
Test status
Simulation time 87330544 ps
CPU time 0.99 seconds
Started Mar 14 01:27:43 PM PDT 24
Finished Mar 14 01:27:44 PM PDT 24
Peak memory 206296 kb
Host smart-e0399be6-100e-4608-b4a6-2b1cc1ce4871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513792810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.513792810
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3763324736
Short name T787
Test name
Test status
Simulation time 2299759323 ps
CPU time 6.55 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 249588 kb
Host smart-8cce0b12-57c2-4184-8f72-2bdbebde0807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763324736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3763324736
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.730769253
Short name T758
Test name
Test status
Simulation time 18503591 ps
CPU time 0.73 seconds
Started Mar 14 01:27:50 PM PDT 24
Finished Mar 14 01:27:50 PM PDT 24
Peak memory 205288 kb
Host smart-b7c72af1-1850-4933-aadd-fada61774bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730769253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.730769253
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2020703994
Short name T603
Test name
Test status
Simulation time 1157958153 ps
CPU time 5.36 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:28:00 PM PDT 24
Peak memory 217096 kb
Host smart-96834d8a-9985-4137-9e2b-10574c5f7541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020703994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2020703994
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1935334236
Short name T489
Test name
Test status
Simulation time 65608283 ps
CPU time 0.82 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:47 PM PDT 24
Peak memory 205040 kb
Host smart-6e23a633-4baf-46b4-9532-8609334b0687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935334236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1935334236
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3808975738
Short name T74
Test name
Test status
Simulation time 1124188572 ps
CPU time 20.23 seconds
Started Mar 14 01:27:49 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 234884 kb
Host smart-4f9025c6-a210-4c8d-8c7c-dc0420df7caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808975738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3808975738
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3234959452
Short name T876
Test name
Test status
Simulation time 15462546425 ps
CPU time 142.58 seconds
Started Mar 14 01:27:49 PM PDT 24
Finished Mar 14 01:30:12 PM PDT 24
Peak memory 248896 kb
Host smart-5510d20c-7ca9-4b47-8b5e-af6c2f31ea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234959452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3234959452
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2477027426
Short name T507
Test name
Test status
Simulation time 35546860442 ps
CPU time 105.87 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:29:32 PM PDT 24
Peak memory 248848 kb
Host smart-103e7250-4b64-4832-9fe2-1b79382dc20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477027426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2477027426
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3032079363
Short name T774
Test name
Test status
Simulation time 2331829986 ps
CPU time 13.87 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:28:00 PM PDT 24
Peak memory 234368 kb
Host smart-e0d69b77-9f5e-4d35-a528-f6757f47be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032079363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3032079363
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3098073663
Short name T430
Test name
Test status
Simulation time 402907874 ps
CPU time 3.63 seconds
Started Mar 14 01:27:49 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 224068 kb
Host smart-7fbfa4bd-8492-4e0a-a3a8-ebe23d177dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098073663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3098073663
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3048069818
Short name T823
Test name
Test status
Simulation time 996275690 ps
CPU time 6.9 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:27:59 PM PDT 24
Peak memory 234012 kb
Host smart-dd0819cd-c2f0-4432-861c-d064f2eb48b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048069818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3048069818
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3827276324
Short name T903
Test name
Test status
Simulation time 1583815472 ps
CPU time 5.18 seconds
Started Mar 14 01:27:49 PM PDT 24
Finished Mar 14 01:27:55 PM PDT 24
Peak memory 232612 kb
Host smart-57e1504f-b1c2-4fa1-b3a1-810a2969ef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827276324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3827276324
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2756723119
Short name T189
Test name
Test status
Simulation time 300601236 ps
CPU time 5.22 seconds
Started Mar 14 01:27:47 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 232860 kb
Host smart-b24150f6-4bb0-462f-aee7-59c38cbf44b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756723119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2756723119
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1942750278
Short name T352
Test name
Test status
Simulation time 2631667281 ps
CPU time 4.85 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:27:59 PM PDT 24
Peak memory 222092 kb
Host smart-79e72282-e5d0-452f-b9cb-af251069a00f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1942750278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1942750278
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1026601751
Short name T478
Test name
Test status
Simulation time 981872463 ps
CPU time 8.52 seconds
Started Mar 14 01:27:45 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 217552 kb
Host smart-2b759c35-8163-4002-92b4-1b0678d41a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026601751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1026601751
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.200066098
Short name T35
Test name
Test status
Simulation time 665514733 ps
CPU time 5.4 seconds
Started Mar 14 01:27:49 PM PDT 24
Finished Mar 14 01:27:54 PM PDT 24
Peak memory 215844 kb
Host smart-ea947a67-1abb-48e3-9785-ab88d80ef428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200066098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.200066098
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3393673432
Short name T11
Test name
Test status
Simulation time 28332048 ps
CPU time 1.25 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:27:54 PM PDT 24
Peak memory 207588 kb
Host smart-8cde1b93-ec16-4e57-9418-1cfb50f5b4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393673432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3393673432
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1668578950
Short name T485
Test name
Test status
Simulation time 77634348 ps
CPU time 0.77 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:46 PM PDT 24
Peak memory 205272 kb
Host smart-d88fa436-2c67-4f82-b2a2-093a625f6a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668578950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1668578950
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1745201020
Short name T99
Test name
Test status
Simulation time 19082251625 ps
CPU time 29.53 seconds
Started Mar 14 01:27:47 PM PDT 24
Finished Mar 14 01:28:16 PM PDT 24
Peak memory 217260 kb
Host smart-4d9c2902-6863-4c74-9f85-1c8b5343c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745201020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1745201020
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2922631415
Short name T487
Test name
Test status
Simulation time 110087388 ps
CPU time 0.72 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:01 PM PDT 24
Peak memory 204920 kb
Host smart-e886000d-383b-454c-b64c-47ad70158573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922631415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
922631415
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2401305850
Short name T863
Test name
Test status
Simulation time 5229947595 ps
CPU time 7.18 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:12 PM PDT 24
Peak memory 234100 kb
Host smart-34aa6d65-fa5e-404c-b8fd-f4df28c5b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401305850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2401305850
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.675843498
Short name T355
Test name
Test status
Simulation time 39143877 ps
CPU time 0.83 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:01 PM PDT 24
Peak memory 206444 kb
Host smart-8bf78c6d-cd56-44de-a4da-3888316fdd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675843498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.675843498
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.593660689
Short name T224
Test name
Test status
Simulation time 40753984537 ps
CPU time 210.79 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:28:31 PM PDT 24
Peak memory 254252 kb
Host smart-fa0531aa-e1f8-4146-9a2a-c0eec9efc8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593660689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.593660689
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3840410850
Short name T437
Test name
Test status
Simulation time 548523920317 ps
CPU time 188.69 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:28:15 PM PDT 24
Peak memory 241028 kb
Host smart-2ad357c2-1e94-4180-8af1-85db00783b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840410850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3840410850
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1186837122
Short name T79
Test name
Test status
Simulation time 52489680695 ps
CPU time 193.12 seconds
Started Mar 14 01:25:03 PM PDT 24
Finished Mar 14 01:28:16 PM PDT 24
Peak memory 250668 kb
Host smart-6235683d-4e62-4543-ad65-ef81f30c2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186837122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1186837122
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2313324655
Short name T239
Test name
Test status
Simulation time 20709584844 ps
CPU time 28.15 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:29 PM PDT 24
Peak memory 233328 kb
Host smart-d64bcf2e-73c1-43ca-9ee7-87b36162684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313324655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2313324655
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2320826759
Short name T795
Test name
Test status
Simulation time 6917835577 ps
CPU time 6.69 seconds
Started Mar 14 01:24:59 PM PDT 24
Finished Mar 14 01:25:06 PM PDT 24
Peak memory 218112 kb
Host smart-89e2a978-151b-401c-9f69-1a202f8276cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320826759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2320826759
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2036327106
Short name T907
Test name
Test status
Simulation time 5539170282 ps
CPU time 12.14 seconds
Started Mar 14 01:24:58 PM PDT 24
Finished Mar 14 01:25:11 PM PDT 24
Peak memory 238208 kb
Host smart-4a0a70d7-aac8-441c-9ada-aa5b4f5e357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036327106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2036327106
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2315361787
Short name T42
Test name
Test status
Simulation time 33622955 ps
CPU time 1.11 seconds
Started Mar 14 01:24:58 PM PDT 24
Finished Mar 14 01:24:59 PM PDT 24
Peak memory 216512 kb
Host smart-5dcfe6d1-b015-47be-8aae-d0b18f2b8ccd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315361787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2315361787
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2371715202
Short name T484
Test name
Test status
Simulation time 5198163607 ps
CPU time 16.32 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:18 PM PDT 24
Peak memory 223472 kb
Host smart-64c20ccc-2c7a-4dc9-9c42-5dbf5ba56006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371715202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2371715202
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1773347509
Short name T436
Test name
Test status
Simulation time 431630259 ps
CPU time 3.27 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:08 PM PDT 24
Peak memory 222936 kb
Host smart-0ec7a998-a80e-4fc5-8ab0-1b6432c49c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773347509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1773347509
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1417571332
Short name T57
Test name
Test status
Simulation time 18758283 ps
CPU time 0.8 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:02 PM PDT 24
Peak memory 215908 kb
Host smart-5c734439-f663-4317-b329-62e55687519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417571332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1417571332
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2587303488
Short name T341
Test name
Test status
Simulation time 856979617 ps
CPU time 4.42 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:05 PM PDT 24
Peak memory 221892 kb
Host smart-7978c5b8-8e50-44f4-9955-61f8fc2f6ba2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2587303488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2587303488
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4166883931
Short name T858
Test name
Test status
Simulation time 13829547028 ps
CPU time 145.95 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:27:33 PM PDT 24
Peak memory 248816 kb
Host smart-ceca8491-6348-4c93-b4ca-1309926b7416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166883931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4166883931
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2339258090
Short name T84
Test name
Test status
Simulation time 10831917314 ps
CPU time 29.81 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:32 PM PDT 24
Peak memory 215968 kb
Host smart-f0f90dd9-fff0-4ee4-adad-98688a7134a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339258090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2339258090
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3595247292
Short name T621
Test name
Test status
Simulation time 19022906650 ps
CPU time 18.29 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:19 PM PDT 24
Peak memory 215976 kb
Host smart-fc0083fa-077b-4301-85db-1bcd55545aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595247292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3595247292
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.807475872
Short name T405
Test name
Test status
Simulation time 160020237 ps
CPU time 2.99 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:04 PM PDT 24
Peak memory 215852 kb
Host smart-809b1450-8780-443e-80e5-9b8e2e440f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807475872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.807475872
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1462424942
Short name T93
Test name
Test status
Simulation time 69041463 ps
CPU time 0.96 seconds
Started Mar 14 01:25:08 PM PDT 24
Finished Mar 14 01:25:09 PM PDT 24
Peak memory 205296 kb
Host smart-b4f359aa-423b-4812-9909-14275be263cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462424942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1462424942
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.959447249
Short name T456
Test name
Test status
Simulation time 294091717 ps
CPU time 6.83 seconds
Started Mar 14 01:25:08 PM PDT 24
Finished Mar 14 01:25:15 PM PDT 24
Peak memory 240448 kb
Host smart-8712f76d-5903-43d6-a6c0-09b8bef9030f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959447249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.959447249
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3382643420
Short name T411
Test name
Test status
Simulation time 16132808 ps
CPU time 0.7 seconds
Started Mar 14 01:25:08 PM PDT 24
Finished Mar 14 01:25:09 PM PDT 24
Peak memory 204380 kb
Host smart-e91f7a10-ecac-4c1d-bf65-81b2ff83e509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382643420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
382643420
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.253546090
Short name T431
Test name
Test status
Simulation time 4690130088 ps
CPU time 5.51 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:13 PM PDT 24
Peak memory 219456 kb
Host smart-f6382201-b327-4b8d-8124-53cd4395d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253546090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.253546090
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.277763967
Short name T875
Test name
Test status
Simulation time 29244927 ps
CPU time 0.77 seconds
Started Mar 14 01:25:04 PM PDT 24
Finished Mar 14 01:25:05 PM PDT 24
Peak memory 206316 kb
Host smart-876f364c-df45-4f31-959a-25594e704f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277763967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.277763967
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3482384631
Short name T151
Test name
Test status
Simulation time 10640463570 ps
CPU time 42.26 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:49 PM PDT 24
Peak memory 248756 kb
Host smart-928bb2f1-5c2f-4c07-9024-86e526995a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482384631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3482384631
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2438414687
Short name T117
Test name
Test status
Simulation time 6677336541 ps
CPU time 53.2 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:55 PM PDT 24
Peak memory 253668 kb
Host smart-f297daa9-6740-4ded-ad19-e155b307257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438414687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2438414687
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.642195287
Short name T150
Test name
Test status
Simulation time 13449291585 ps
CPU time 80.44 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:26:25 PM PDT 24
Peak memory 253524 kb
Host smart-61b12f2f-74f8-422d-bfe7-52f2e230a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642195287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
642195287
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1294027937
Short name T506
Test name
Test status
Simulation time 571460628 ps
CPU time 18.81 seconds
Started Mar 14 01:25:06 PM PDT 24
Finished Mar 14 01:25:25 PM PDT 24
Peak memory 239612 kb
Host smart-d534b896-f0d9-426b-af29-c1936b071955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294027937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1294027937
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3353281244
Short name T463
Test name
Test status
Simulation time 1433183938 ps
CPU time 2.89 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:03 PM PDT 24
Peak memory 216052 kb
Host smart-881aa7ab-38dc-4b61-a0c6-76a643c16f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353281244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3353281244
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2479414172
Short name T307
Test name
Test status
Simulation time 980665580 ps
CPU time 7.41 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:15 PM PDT 24
Peak memory 231528 kb
Host smart-d39eb711-0e11-45cb-9b2f-619905980c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479414172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2479414172
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3285655982
Short name T264
Test name
Test status
Simulation time 32264125 ps
CPU time 1.11 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:01 PM PDT 24
Peak memory 216436 kb
Host smart-b661f917-d46a-4898-8e44-8280fdc63799
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285655982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3285655982
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.692894907
Short name T815
Test name
Test status
Simulation time 14773218958 ps
CPU time 12.48 seconds
Started Mar 14 01:25:07 PM PDT 24
Finished Mar 14 01:25:20 PM PDT 24
Peak memory 232816 kb
Host smart-5f3fe891-0bf2-4da0-a005-12dbf3621f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692894907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
692894907
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2313701709
Short name T129
Test name
Test status
Simulation time 8599191145 ps
CPU time 24.56 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:25 PM PDT 24
Peak memory 224120 kb
Host smart-d75b4637-a6a1-4d69-b524-9b38ccade038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313701709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2313701709
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2497542605
Short name T59
Test name
Test status
Simulation time 20303221 ps
CPU time 0.73 seconds
Started Mar 14 01:25:04 PM PDT 24
Finished Mar 14 01:25:05 PM PDT 24
Peak memory 215888 kb
Host smart-09fff64d-6c64-4cf0-90d4-a27825c394b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497542605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2497542605
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.577070600
Short name T649
Test name
Test status
Simulation time 269864540 ps
CPU time 3.84 seconds
Started Mar 14 01:25:01 PM PDT 24
Finished Mar 14 01:25:05 PM PDT 24
Peak memory 221976 kb
Host smart-b4e0c88b-399a-4ff2-8def-3258bbe87a51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=577070600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.577070600
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3173090160
Short name T91
Test name
Test status
Simulation time 59831407893 ps
CPU time 200.46 seconds
Started Mar 14 01:25:03 PM PDT 24
Finished Mar 14 01:28:24 PM PDT 24
Peak memory 269660 kb
Host smart-a985ed6f-df1e-4da0-a252-396fc4319f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173090160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3173090160
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3152522264
Short name T860
Test name
Test status
Simulation time 9267772922 ps
CPU time 37.87 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:43 PM PDT 24
Peak memory 216056 kb
Host smart-db9bdfd7-6300-4df5-a4ec-76feb49485fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152522264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3152522264
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1890861319
Short name T266
Test name
Test status
Simulation time 18226444862 ps
CPU time 12.94 seconds
Started Mar 14 01:25:03 PM PDT 24
Finished Mar 14 01:25:16 PM PDT 24
Peak memory 215920 kb
Host smart-4c13045d-714c-4249-a830-e8db00d85480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890861319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1890861319
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3935578040
Short name T930
Test name
Test status
Simulation time 48022800 ps
CPU time 0.96 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:04 PM PDT 24
Peak memory 206416 kb
Host smart-262dbe67-0e54-4f4c-baa6-96de55fbe880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935578040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3935578040
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2555628308
Short name T267
Test name
Test status
Simulation time 91211423 ps
CPU time 0.81 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:01 PM PDT 24
Peak memory 205212 kb
Host smart-b61b4250-7622-411f-8e65-c20daf61f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555628308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2555628308
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3750372025
Short name T399
Test name
Test status
Simulation time 6627971284 ps
CPU time 23.6 seconds
Started Mar 14 01:25:02 PM PDT 24
Finished Mar 14 01:25:26 PM PDT 24
Peak memory 237588 kb
Host smart-ce4c7c93-c269-46d3-8506-dbc460f666a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750372025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3750372025
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2655936264
Short name T461
Test name
Test status
Simulation time 15295676 ps
CPU time 0.71 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:24 PM PDT 24
Peak memory 205280 kb
Host smart-fa81242e-b838-4f07-b4eb-bf2af88edaf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655936264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
655936264
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3135552989
Short name T381
Test name
Test status
Simulation time 1721686163 ps
CPU time 4.69 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:25:24 PM PDT 24
Peak memory 219268 kb
Host smart-4ead9cac-73d5-4a3e-ba77-f5aae8e432c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135552989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3135552989
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3039736486
Short name T376
Test name
Test status
Simulation time 49505472 ps
CPU time 0.79 seconds
Started Mar 14 01:25:05 PM PDT 24
Finished Mar 14 01:25:06 PM PDT 24
Peak memory 206364 kb
Host smart-485566cc-a2ec-42c8-941a-673666c8c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039736486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3039736486
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3985030296
Short name T846
Test name
Test status
Simulation time 7572669871 ps
CPU time 48.05 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:26:08 PM PDT 24
Peak memory 240544 kb
Host smart-e5d33300-c099-464e-a88b-898b401b4ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985030296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3985030296
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.743176377
Short name T438
Test name
Test status
Simulation time 2142806207 ps
CPU time 23.53 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:25:43 PM PDT 24
Peak memory 232400 kb
Host smart-16bce028-16e4-4a73-946e-33c2c4865a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743176377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.743176377
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.156442942
Short name T735
Test name
Test status
Simulation time 11953365798 ps
CPU time 55.42 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:26:18 PM PDT 24
Peak memory 248720 kb
Host smart-394a0e50-7cd6-42ea-9120-579cf718d46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156442942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
156442942
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3188282295
Short name T111
Test name
Test status
Simulation time 8629870827 ps
CPU time 18.02 seconds
Started Mar 14 01:25:26 PM PDT 24
Finished Mar 14 01:25:44 PM PDT 24
Peak memory 233448 kb
Host smart-96518de7-67dd-449e-9512-42f01a4aae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188282295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3188282295
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1285720507
Short name T936
Test name
Test status
Simulation time 6635147092 ps
CPU time 4.2 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:25 PM PDT 24
Peak memory 236556 kb
Host smart-c930cb8e-bcf9-4472-8196-0de6b0b83c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285720507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1285720507
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2649318561
Short name T317
Test name
Test status
Simulation time 50250149960 ps
CPU time 57.61 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:26:17 PM PDT 24
Peak memory 240476 kb
Host smart-d5d8a8cd-42fa-4988-82f9-bf77912578aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649318561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2649318561
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3921402333
Short name T402
Test name
Test status
Simulation time 23660951 ps
CPU time 1.02 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:01 PM PDT 24
Peak memory 217664 kb
Host smart-791ccaae-2d85-4019-a7a9-a45fdf267746
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921402333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3921402333
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2359288693
Short name T202
Test name
Test status
Simulation time 1212904939 ps
CPU time 5.81 seconds
Started Mar 14 01:25:22 PM PDT 24
Finished Mar 14 01:25:28 PM PDT 24
Peak memory 233420 kb
Host smart-c475a648-db14-4063-8466-b593ad62f9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359288693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2359288693
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2579672897
Short name T604
Test name
Test status
Simulation time 1380978953 ps
CPU time 9.38 seconds
Started Mar 14 01:25:20 PM PDT 24
Finished Mar 14 01:25:29 PM PDT 24
Peak memory 234604 kb
Host smart-989e05c2-5f3e-4d9d-8119-361a705f8fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579672897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2579672897
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.1026855770
Short name T303
Test name
Test status
Simulation time 21554213 ps
CPU time 0.77 seconds
Started Mar 14 01:25:00 PM PDT 24
Finished Mar 14 01:25:01 PM PDT 24
Peak memory 215892 kb
Host smart-b76e810e-7421-4522-b710-1672c4bd1637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026855770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.1026855770
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1882354420
Short name T426
Test name
Test status
Simulation time 1632633206 ps
CPU time 5.17 seconds
Started Mar 14 01:25:22 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 218176 kb
Host smart-cbf0bc72-6cbb-4ed0-8a86-6a71ecb452a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1882354420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1882354420
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.583151750
Short name T801
Test name
Test status
Simulation time 18041443320 ps
CPU time 91.53 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:26:51 PM PDT 24
Peak memory 254532 kb
Host smart-08f5f709-76e6-4e94-abad-17f52d33ce98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583151750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.583151750
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2167725229
Short name T623
Test name
Test status
Simulation time 3190940863 ps
CPU time 19.57 seconds
Started Mar 14 01:25:03 PM PDT 24
Finished Mar 14 01:25:23 PM PDT 24
Peak memory 215792 kb
Host smart-e3e36eb4-0421-4912-b1d4-d2be661bf314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167725229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2167725229
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3032149499
Short name T660
Test name
Test status
Simulation time 2836897110 ps
CPU time 6.06 seconds
Started Mar 14 01:25:03 PM PDT 24
Finished Mar 14 01:25:09 PM PDT 24
Peak memory 215784 kb
Host smart-f36214f0-54a0-46f0-a4a8-844e7f63e8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032149499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3032149499
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1811713749
Short name T519
Test name
Test status
Simulation time 988978391 ps
CPU time 3.48 seconds
Started Mar 14 01:25:22 PM PDT 24
Finished Mar 14 01:25:26 PM PDT 24
Peak memory 216088 kb
Host smart-51bda23a-5c33-4842-81b1-4ddf58559958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811713749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1811713749
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.653241249
Short name T792
Test name
Test status
Simulation time 338829632 ps
CPU time 1 seconds
Started Mar 14 01:25:04 PM PDT 24
Finished Mar 14 01:25:05 PM PDT 24
Peak memory 206256 kb
Host smart-76ab8b67-8db0-4638-b7f7-111a6110b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653241249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.653241249
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.870855770
Short name T789
Test name
Test status
Simulation time 11666209516 ps
CPU time 12.52 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:37 PM PDT 24
Peak memory 224072 kb
Host smart-782374ad-730e-40ee-b059-f090cf34cf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870855770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.870855770
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3419978398
Short name T347
Test name
Test status
Simulation time 22118082 ps
CPU time 0.69 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:24 PM PDT 24
Peak memory 204376 kb
Host smart-213d6103-3879-4dad-bba9-3efc6642456d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419978398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
419978398
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2392195861
Short name T750
Test name
Test status
Simulation time 11149163461 ps
CPU time 9.51 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:25:34 PM PDT 24
Peak memory 224180 kb
Host smart-72755681-7fb6-4807-bf55-f4c019e55886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392195861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2392195861
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.17601832
Short name T316
Test name
Test status
Simulation time 16036562 ps
CPU time 0.8 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:24 PM PDT 24
Peak memory 206048 kb
Host smart-bb1628df-fd6d-451d-8fbd-d8b89cad7927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17601832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.17601832
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.292355849
Short name T733
Test name
Test status
Simulation time 22452300249 ps
CPU time 113.86 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:27:15 PM PDT 24
Peak memory 253396 kb
Host smart-74ee1fb8-88c7-457b-8af8-72cb1941e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292355849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.292355849
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2937784045
Short name T473
Test name
Test status
Simulation time 14216778109 ps
CPU time 53.41 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 250864 kb
Host smart-f52c3672-0d23-46ed-8fc5-76d2a8b2d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937784045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2937784045
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3152817208
Short name T653
Test name
Test status
Simulation time 82495256292 ps
CPU time 119.42 seconds
Started Mar 14 01:25:26 PM PDT 24
Finished Mar 14 01:27:25 PM PDT 24
Peak memory 232612 kb
Host smart-650fdf8a-83fa-4952-84f6-30a18c270e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152817208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3152817208
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4194525424
Short name T323
Test name
Test status
Simulation time 5381318849 ps
CPU time 15.76 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:37 PM PDT 24
Peak memory 224192 kb
Host smart-c51b8635-e33d-46a3-9469-de9cb76f7227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194525424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4194525424
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2834331989
Short name T145
Test name
Test status
Simulation time 2730434702 ps
CPU time 4.88 seconds
Started Mar 14 01:25:22 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 217844 kb
Host smart-b34c1246-b2eb-4017-9410-b2794e17b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834331989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2834331989
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2498034174
Short name T599
Test name
Test status
Simulation time 11035232087 ps
CPU time 23.27 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:25:42 PM PDT 24
Peak memory 247872 kb
Host smart-2211ee8c-9777-4542-9811-5a2e13add145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498034174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2498034174
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1191024872
Short name T313
Test name
Test status
Simulation time 90413700 ps
CPU time 1.09 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:26 PM PDT 24
Peak memory 217668 kb
Host smart-e0a6c1a2-2798-4daf-9f46-4cb9b1cc26cb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191024872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1191024872
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3612426177
Short name T494
Test name
Test status
Simulation time 22620183787 ps
CPU time 7.23 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:25:31 PM PDT 24
Peak memory 233008 kb
Host smart-3b6d596a-9294-4fea-959d-31fd230e88a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612426177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3612426177
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.268873603
Short name T32
Test name
Test status
Simulation time 4723194315 ps
CPU time 5.77 seconds
Started Mar 14 01:25:20 PM PDT 24
Finished Mar 14 01:25:26 PM PDT 24
Peak memory 217432 kb
Host smart-790328df-95d8-487d-a632-4fc93f199103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268873603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.268873603
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2167480388
Short name T739
Test name
Test status
Simulation time 23385348 ps
CPU time 0.77 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:24 PM PDT 24
Peak memory 215908 kb
Host smart-1dd6ec5e-716f-4a74-b18c-5a9e1938897c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167480388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2167480388
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1267309647
Short name T406
Test name
Test status
Simulation time 672167046 ps
CPU time 4.27 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:25:23 PM PDT 24
Peak memory 221728 kb
Host smart-bd57bdea-e0df-40f5-b24f-d7441aef5a3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1267309647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1267309647
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4178875827
Short name T104
Test name
Test status
Simulation time 7152695850 ps
CPU time 93.86 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:26:57 PM PDT 24
Peak memory 250032 kb
Host smart-5b99d433-17ff-48cb-bea6-6d8ed407ae31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178875827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4178875827
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.274880437
Short name T526
Test name
Test status
Simulation time 5797243883 ps
CPU time 4.79 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:30 PM PDT 24
Peak memory 216000 kb
Host smart-9423dc9f-a311-4553-a4c9-b6a6eaffed6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274880437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.274880437
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1893456790
Short name T755
Test name
Test status
Simulation time 5792132706 ps
CPU time 9.61 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:31 PM PDT 24
Peak memory 215996 kb
Host smart-6350eae0-2b2f-4d98-9be6-499d129e4839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893456790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1893456790
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3324088541
Short name T587
Test name
Test status
Simulation time 74836795 ps
CPU time 1.11 seconds
Started Mar 14 01:25:20 PM PDT 24
Finished Mar 14 01:25:21 PM PDT 24
Peak memory 206320 kb
Host smart-c0e9acf2-7ae6-478c-b49e-54f31da83a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324088541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3324088541
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.849463244
Short name T708
Test name
Test status
Simulation time 211742085 ps
CPU time 0.87 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:26 PM PDT 24
Peak memory 205216 kb
Host smart-66cf1ff2-86b7-44a9-829c-a1be70f5e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849463244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.849463244
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1471835613
Short name T345
Test name
Test status
Simulation time 651739816 ps
CPU time 4 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:27 PM PDT 24
Peak memory 218528 kb
Host smart-1b7d2270-8f6c-43f4-977f-1ca628f54b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471835613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1471835613
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2613351795
Short name T370
Test name
Test status
Simulation time 40117067 ps
CPU time 0.74 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:25:20 PM PDT 24
Peak memory 204996 kb
Host smart-1047ba6a-e58a-40b4-98b1-39788cf1fced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613351795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
613351795
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2039343223
Short name T398
Test name
Test status
Simulation time 85663606 ps
CPU time 2.19 seconds
Started Mar 14 01:25:20 PM PDT 24
Finished Mar 14 01:25:22 PM PDT 24
Peak memory 216996 kb
Host smart-d43bfd69-9ac2-4708-bc69-c439c76a6e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039343223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2039343223
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2114433447
Short name T719
Test name
Test status
Simulation time 17361694 ps
CPU time 0.81 seconds
Started Mar 14 01:25:20 PM PDT 24
Finished Mar 14 01:25:21 PM PDT 24
Peak memory 206408 kb
Host smart-6eb7a76f-45d6-4645-8cd6-66446f2ee065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114433447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2114433447
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3431197575
Short name T697
Test name
Test status
Simulation time 38768676102 ps
CPU time 187.06 seconds
Started Mar 14 01:25:19 PM PDT 24
Finished Mar 14 01:28:26 PM PDT 24
Peak memory 249652 kb
Host smart-f966e484-e615-4f08-bba4-e6ddec2c18ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431197575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3431197575
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4012808608
Short name T615
Test name
Test status
Simulation time 31577760972 ps
CPU time 55.73 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:26:19 PM PDT 24
Peak memory 237812 kb
Host smart-07c5b551-ed75-4496-855e-3a16c95766da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012808608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4012808608
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1185185649
Short name T351
Test name
Test status
Simulation time 12766436135 ps
CPU time 23.13 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:25:47 PM PDT 24
Peak memory 232208 kb
Host smart-6d9b5487-e1d7-4172-9873-d5deeee78d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185185649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1185185649
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2725731680
Short name T483
Test name
Test status
Simulation time 2454480052 ps
CPU time 9.09 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:30 PM PDT 24
Peak memory 232832 kb
Host smart-3f2eb556-5058-4cdc-ab12-10ce725c9efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725731680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2725731680
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2990117830
Short name T710
Test name
Test status
Simulation time 12801807635 ps
CPU time 34.85 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:25:59 PM PDT 24
Peak memory 232332 kb
Host smart-34953747-92a2-464d-927c-c540b7e28ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990117830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2990117830
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1548826972
Short name T273
Test name
Test status
Simulation time 27329810 ps
CPU time 1.14 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:24 PM PDT 24
Peak memory 216464 kb
Host smart-7e14c5f8-1e62-4abb-bd40-a791b3cfa817
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548826972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1548826972
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3688222569
Short name T46
Test name
Test status
Simulation time 15788550297 ps
CPU time 9.68 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:33 PM PDT 24
Peak memory 224092 kb
Host smart-48a18f38-048a-4928-ab87-2de3f4f63b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688222569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3688222569
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.73617603
Short name T699
Test name
Test status
Simulation time 4278655905 ps
CPU time 14 seconds
Started Mar 14 01:25:20 PM PDT 24
Finished Mar 14 01:25:34 PM PDT 24
Peak memory 224252 kb
Host smart-df1d6919-cd41-4b4a-8640-251c0770cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73617603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.73617603
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1380197904
Short name T293
Test name
Test status
Simulation time 31066573 ps
CPU time 0.7 seconds
Started Mar 14 01:25:22 PM PDT 24
Finished Mar 14 01:25:23 PM PDT 24
Peak memory 215856 kb
Host smart-57cb114c-0be3-49bf-a45a-637b615332e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380197904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1380197904
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1383226264
Short name T481
Test name
Test status
Simulation time 4661487626 ps
CPU time 5.57 seconds
Started Mar 14 01:25:25 PM PDT 24
Finished Mar 14 01:25:31 PM PDT 24
Peak memory 218400 kb
Host smart-f9198a89-eac5-4b84-a2c7-c65a402d9338
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1383226264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1383226264
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3498936140
Short name T682
Test name
Test status
Simulation time 14602273686 ps
CPU time 30.07 seconds
Started Mar 14 01:25:22 PM PDT 24
Finished Mar 14 01:25:52 PM PDT 24
Peak memory 215932 kb
Host smart-77d7dfb8-8546-41d3-995a-7e8c61f2344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498936140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3498936140
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3569237924
Short name T598
Test name
Test status
Simulation time 87855032 ps
CPU time 1.07 seconds
Started Mar 14 01:25:23 PM PDT 24
Finished Mar 14 01:25:25 PM PDT 24
Peak memory 205384 kb
Host smart-e07a0011-70c7-446d-b756-98643d433e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569237924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3569237924
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.434415621
Short name T625
Test name
Test status
Simulation time 33524692 ps
CPU time 1.08 seconds
Started Mar 14 01:25:24 PM PDT 24
Finished Mar 14 01:25:25 PM PDT 24
Peak memory 207412 kb
Host smart-cd8f3026-bb69-4194-bd26-1880ad32ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434415621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.434415621
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1051181296
Short name T270
Test name
Test status
Simulation time 164500573 ps
CPU time 0.89 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:22 PM PDT 24
Peak memory 206300 kb
Host smart-2a4e4b81-3e4d-49cf-afe1-09b0b2dbb28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051181296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1051181296
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2724380443
Short name T857
Test name
Test status
Simulation time 6903948613 ps
CPU time 7.99 seconds
Started Mar 14 01:25:21 PM PDT 24
Finished Mar 14 01:25:29 PM PDT 24
Peak memory 233048 kb
Host smart-71bf4538-8c47-4f24-adf8-c4016da0d2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724380443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2724380443
Directory /workspace/9.spi_device_upload/latest
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