Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7808960	1			T1	8188		T2	75183		T3	1
all_values[1]	7808960	1			T1	8188		T2	75183		T3	1
all_values[2]	7808960	1			T1	8188		T2	75183		T3	1
all_values[3]	7808960	1			T1	8188		T2	75183		T3	1
all_values[4]	7808960	1			T1	8188		T2	75183		T3	1
all_values[5]	7808960	1			T1	8188		T2	75183		T3	1
all_values[6]	7808960	1			T1	8188		T2	75183		T3	1
all_values[7]	7808960	1			T1	8188		T2	75183		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60799057

1

T1

65504

T2

601464

T3

8

auto[1]

1672623

1

T28

48

T31

46

T69

19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62386836

1

T1

65204

T2

600876

T3

8

auto[1]

84844

1

T1

300

T2

588

T7

113

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7650119	1			T1	8026		T2	74910		T3	1
all_values[0]	auto[0]	auto[1]	47328	1			T1	162		T2	273		T7	56
all_values[0]	auto[1]	auto[0]	109710	1			T28	2		T31	1		T70	1
all_values[0]	auto[1]	auto[1]	1803	1			T28	2		T31	1		T68	4
all_values[1]	auto[0]	auto[0]	7624324	1			T1	8080		T2	74990		T3	1
all_values[1]	auto[0]	auto[1]	23967	1			T1	108		T2	193		T7	33
all_values[1]	auto[1]	auto[0]	159805	1			T28	5		T31	6		T69	3
all_values[1]	auto[1]	auto[1]	864	1			T69	1		T70	1		T154	5
all_values[2]	auto[0]	auto[0]	7681593	1			T1	8158		T2	75061		T3	1
all_values[2]	auto[0]	auto[1]	8259	1			T1	30		T2	122		T7	24
all_values[2]	auto[1]	auto[0]	118547	1			T28	1		T31	4		T68	1
all_values[2]	auto[1]	auto[1]	561	1			T28	2		T31	3		T69	1
all_values[3]	auto[0]	auto[0]	7560445	1			T1	8188		T2	75183		T3	1
all_values[3]	auto[0]	auto[1]	198	1			T28	1		T31	1		T70	1
all_values[3]	auto[1]	auto[0]	248141	1			T28	6		T31	7		T69	2
all_values[3]	auto[1]	auto[1]	176	1			T28	3		T69	2		T68	2
all_values[4]	auto[0]	auto[0]	7644345	1			T1	8188		T2	75183		T3	1
all_values[4]	auto[0]	auto[1]	197	1			T28	1		T70	1		T68	4
all_values[4]	auto[1]	auto[0]	164236	1			T28	11		T31	5		T69	3
all_values[4]	auto[1]	auto[1]	182	1			T31	4		T69	1		T68	1
all_values[5]	auto[0]	auto[0]	7487867	1			T1	8188		T2	75183		T3	1
all_values[5]	auto[0]	auto[1]	340	1			T18	2		T24	1		T244	2
all_values[5]	auto[1]	auto[0]	320574	1			T28	4		T31	1		T69	2
all_values[5]	auto[1]	auto[1]	179	1			T28	2		T31	3		T69	2
all_values[6]	auto[0]	auto[0]	7596652	1			T1	8188		T2	75183		T3	1
all_values[6]	auto[0]	auto[1]	189	1			T28	8		T68	3		T154	7
all_values[6]	auto[1]	auto[0]	211911	1			T28	2		T31	3		T69	1
all_values[6]	auto[1]	auto[1]	208	1			T28	1		T69	1		T70	3
all_values[7]	auto[0]	auto[0]	7473031	1			T1	8188		T2	75183		T3	1
all_values[7]	auto[0]	auto[1]	203	1			T28	1		T31	1		T69	1
all_values[7]	auto[1]	auto[0]	335536	1			T28	2		T31	2		T68	1
all_values[7]	auto[1]	auto[1]	190	1			T28	5		T31	6		T70	1