Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	44116	1			T1	375		T2	72		T5	6
auto[SpiFlashAddrCfg]	9398	1			T1	41		T2	18		T6	2
auto[SpiFlashAddr3b]	11766	1			T1	51		T2	33		T5	2
auto[SpiFlashAddr4b]	9625	1			T1	26		T2	18		T7	29

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42876

1

T1

209

T2

68

T5

8

auto[1]

32029

1

T1

284

T2

73

T7

114

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40373

1

T1

132

T2

65

T5

8

auto[1]

34532

1

T1

361

T2

76

T6

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	49959	1			T1	393		T2	85		T5	6
values[1]	1454	1			T1	4		T2	8		T6	4
values[2]	1763	1			T1	9		T2	2		T7	5
values[3]	1989	1			T1	7		T2	1		T7	8
values[4]	1852	1			T1	3		T2	8		T6	2
values[5]	1820	1			T1	5		T2	6		T7	8
values[6]	1928	1			T1	7		T2	1		T6	2
values[7]	1787	1			T1	3		T2	2		T6	2
values[8]	12353	1			T1	62		T2	28		T5	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34836

1

T1

493

T2

141

T5

8

auto[1]

40069

1

T7

212

T36

22

T140

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

72195

1

T1

482

T2

130

T5

8

write

2710

1

T1

11

T2

11

T7

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

25185

1

T1

86

T2

64

T5

2

valids[0x1]

49720

1

T1

407

T2

77

T5

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1978	1			T1	7		T2	8		T5	2
internal_process_ops[0x5a]	1971	1			T1	7		T2	5		T7	7
internal_process_ops[0x05]	26319	1			T1	324		T2	25		T5	4
internal_process_ops[0x35]	2014	1			T1	5		T2	1		T6	4
internal_process_ops[0x15]	2056	1			T1	10		T2	4		T6	2
internal_process_ops[0x03]	1387	1			T1	7		T2	2		T7	1
internal_process_ops[0x0b]	1326	1			T1	8		T2	1		T7	4
internal_process_ops[0x3b]	1344	1			T1	9		T2	3		T5	2
internal_process_ops[0x6b]	1334	1			T1	3		T2	2		T8	6
internal_process_ops[0xbb]	1393	1			T1	12		T2	9		T7	3
internal_process_ops[0xeb]	1367	1			T1	8		T2	7		T6	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73572

1

T1

483

T2

134

T5

8

auto[1]

1333

1

T1

10

T2

7

T7

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72253

1

T1

480

T2

131

T5

8

auto[1]

2652

1

T1

13

T2

10

T7

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11878

1

T1

149

T2

37

T5

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7073

1

T1

226

T2

29

T8

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2424

1

T1

13

T2

5

T6

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2096

1

T1

25

T2

13

T8

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3066

1

T1

26

T2

16

T5

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2543

1

T1

20

T2

13

T8

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2479

1

T1

15

T2

5

T10

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2158

1

T1

8

T2

12

T8

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

100

1

T23

1

T28

1

T88

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

95

1

T2

2

T23

1

T88

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

57

1

T2

1

T23

1

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

78

1

T2

3

T13

2

T23

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

77

1

T23

1

T162

4

T163

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

70

1

T1

3

T23

1

T28

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

71

1

T28

5

T32

2

T34

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

70

1

T23

5

T28

2

T164

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

82

1

T2

2

T23

1

T165

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

44

1

T1

2

T23

2

T88

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

69

1

T88

1

T31

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

73

1

T1

3

T2

2

T30

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

77

1

T2

1

T10

2

T13

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

45

1

T1

1

T28

3

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

61

1

T1

1

T23

3

T28

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

50

1

T1

1

T31

2

T32

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

14432

1

T7

49

T25

22

T26

60

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

10001

1

T7

61

T25

21

T26

140

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2106

1

T7

10

T36

3

T25

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2094

1

T7

13

T25

3

T26

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2849

1

T7

20

T36

11

T140

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2633

1

T7

25

T25

9

T26

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2234

1

T7

18

T36

8

T140

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2129

1

T7

9

T25

3

T26

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

93

1

T42

1

T43

1

T166

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

89

1

T26

3

T42

2

T43

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

110

1

T7

2

T26

1

T42

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

110

1

T7

1

T25

2

T42

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

96

1

T93

1

T167

1

T56

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T26

1

T44

1

T168

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

104

1

T7

1

T25

2

T42

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

95

1

T25

1

T26

3

T42

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

125

1

T25

1

T42

6

T43

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

104

1

T26

1

T42

1

T44

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

82

1

T7

1

T26

1

T89

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

96

1

T42

1

T60

1

T43

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T7

1

T42

4

T44

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

126

1

T42

4

T43

1

T167

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

83

1

T25

3

T26

1

T44

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

93

1

T7

1

T42

7

T44

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4767	1			T1	29		T2	25		T10	2
auto[0]	values[0]	valids[0x1]	17306	1			T1	364		T2	60		T5	6
auto[0]	values[1]	valids[0x1]	690	1			T1	4		T2	8		T6	4
auto[0]	values[2]	valids[0x0]	617	1			T1	5		T2	1		T8	6
auto[0]	values[2]	valids[0x1]	326	1			T1	4		T2	1		T12	4
auto[0]	values[3]	valids[0x0]	639	1			T1	7		T2	1		T13	1
auto[0]	values[3]	valids[0x1]	389	1			T13	1		T23	6		T28	4
auto[0]	values[4]	valids[0x0]	624	1			T1	3		T2	7		T6	2
auto[0]	values[4]	valids[0x1]	371	1			T2	1		T8	6		T13	1
auto[0]	values[5]	valids[0x0]	606	1			T1	4		T2	5		T8	4
auto[0]	values[5]	valids[0x1]	332	1			T1	1		T2	1		T23	7
auto[0]	values[6]	valids[0x0]	649	1			T1	3		T2	1		T6	2
auto[0]	values[6]	valids[0x1]	364	1			T1	4		T23	2		T162	4
auto[0]	values[7]	valids[0x0]	596	1			T1	1		T2	2		T23	13
auto[0]	values[7]	valids[0x1]	321	1			T1	2		T6	2		T145	4
auto[0]	values[8]	valids[0x0]	3889	1			T1	34		T2	22		T5	2
auto[0]	values[8]	valids[0x1]	2350	1			T1	28		T2	6		T10	2
auto[1]	values[0]	valids[0x0]	5893	1			T7	22		T25	10		T26	32
auto[1]	values[0]	valids[0x1]	21993	1			T7	110		T25	50		T26	200
auto[1]	values[1]	valids[0x1]	764	1			T7	7		T25	4		T26	7
auto[1]	values[2]	valids[0x0]	500	1			T7	1		T25	3		T26	4
auto[1]	values[2]	valids[0x1]	320	1			T7	4		T25	1		T26	1
auto[1]	values[3]	valids[0x0]	586	1			T7	6		T36	11		T25	1
auto[1]	values[3]	valids[0x1]	375	1			T7	2		T25	1		T26	1
auto[1]	values[4]	valids[0x0]	536	1			T7	3		T38	5		T25	3
auto[1]	values[4]	valids[0x1]	321	1			T7	2		T42	4		T60	2
auto[1]	values[5]	valids[0x0]	546	1			T7	3		T26	2		T42	7
auto[1]	values[5]	valids[0x1]	336	1			T7	5		T140	4		T26	2
auto[1]	values[6]	valids[0x0]	574	1			T7	5		T26	2		T42	12
auto[1]	values[6]	valids[0x1]	341	1			T7	1		T25	2		T26	1
auto[1]	values[7]	valids[0x0]	526	1			T7	3		T140	3		T38	3
auto[1]	values[7]	valids[0x1]	344	1			T25	1		T26	5		T42	1
auto[1]	values[8]	valids[0x0]	3637	1			T7	25		T36	3		T25	6
auto[1]	values[8]	valids[0x1]	2477	1			T7	13		T36	8		T140	5