Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20461

1

T1

87

T2

49

T5

10

auto[1]

26651

1

T1

324

T2

30

T7

56

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17119

1

T1

72

T2

49

T5

10

auto[1]

29993

1

T1

339

T2

30

T7

78

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7786	1			T1	78		T2	14		T5	6
auto[524288:1048575]	5457	1			T1	108		T2	9		T7	5
auto[1048576:1572863]	5818	1			T1	30		T2	12		T7	2
auto[1572864:2097151]	5855	1			T1	4		T2	7		T7	36
auto[2097152:2621439]	5414	1			T1	8		T2	18		T7	14
auto[2621440:3145727]	5653	1			T1	4		T7	14		T11	2
auto[3145728:3670015]	5970	1			T1	177		T2	13		T7	40
auto[3670016:4194303]	5159	1			T1	2		T2	6		T5	4

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46112

1

T1

400

T2

77

T5

10

auto[1]

1000

1

T1

11

T2

2

T7

6

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37692

1

T1

405

T2

78

T5

10

auto[1]

9420

1

T1

6

T2

1

T7

90

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	2014	1			T1	8		T2	4		T5	6
auto[0]	auto[0]	auto[0:524287]	auto[1]	859	1			T1	3		T2	2		T7	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1391	1			T1	11		T2	4		T7	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	552	1			T1	4		T2	1		T7	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1378	1			T1	5		T2	7		T7	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	581	1			T1	2		T2	2		T184	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1428	1			T1	1		T2	2		T7	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	589	1			T1	3		T7	4		T184	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1298	1			T1	5		T2	8		T7	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	533	1			T1	3		T2	2		T7	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1364	1			T1	2		T11	1		T13	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	516	1			T1	2		T13	2		T184	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1400	1			T1	23		T2	8		T13	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	518	1			T1	7		T2	2		T7	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1405	1			T1	1		T2	5		T5	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	523	1			T1	1		T2	1		T7	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	393	1			T7	1		T11	2		T13	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	161	1			T13	1		T43	2		T44	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	354	1			T7	2		T11	3		T23	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	149	1			T7	1		T23	2		T26	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	363	1			T1	2		T2	1		T11	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	163	1			T23	1		T26	1		T42	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	350	1			T7	7		T11	4		T23	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	178	1			T7	5		T23	3		T26	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	325	1			T7	1		T23	3		T26	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	171	1			T26	1		T42	1		T44	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	343	1			T7	8		T11	1		T23	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	180	1			T7	6		T26	2		T44	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	342	1			T1	1		T7	8		T43	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	162	1			T1	3		T7	3		T42	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	318	1			T11	1		T23	2		T26	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	160	1			T7	1		T26	1		T43	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	360	1			T1	2		T2	2		T13	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3163	1			T1	65		T2	6		T13	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	281	1			T1	3		T2	1		T13	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2180	1			T1	90		T2	3		T13	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	232	1			T1	1		T2	1		T23	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2122	1			T1	20		T2	1		T23	51
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	261	1			T2	2		T23	1		T25	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2448	1			T2	3		T23	2		T25	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	247	1			T2	3		T7	1		T23	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2173	1			T2	5		T7	8		T23	23
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	267	1			T13	3		T23	1		T26	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2578	1			T13	6		T23	3		T26	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	261	1			T1	7		T2	1		T23	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2754	1			T1	136		T2	2		T23	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	206	1			T23	1		T42	2		T43	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1810	1			T23	16		T42	78		T43	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	85	1			T13	2		T51	2		T70	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	751	1			T13	7		T51	13		T70	7
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	71	1			T26	1		T60	1		T44	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	479	1			T26	3		T60	15		T44	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	85	1			T42	1		T167	2		T28	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	894	1			T42	51		T167	39		T28	35
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	59	1			T7	1		T60	1		T43	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	542	1			T7	18		T60	4		T43	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	62	1			T26	1		T167	1		T87	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	605	1			T26	15		T167	9		T87	45
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	56	1			T93	1		T89	1		T32	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	349	1			T93	3		T89	3		T32	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	59	1			T7	3		T167	1		T87	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	474	1			T7	25		T167	6		T87	8
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	61	1			T23	2		T26	1		T42	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	676	1			T23	100		T26	15		T42	101

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	15934	1			T1	74		T2	48		T5	10
auto[0]	auto[0]	auto[1]	415	1			T1	7		T7	1		T23	5
auto[0]	auto[1]	auto[0]	4002	1			T1	6		T2	1		T7	42
auto[0]	auto[1]	auto[1]	110	1			T7	1		T23	1		T42	3
auto[1]	auto[0]	auto[0]	20960	1			T1	320		T2	28		T7	8
auto[1]	auto[0]	auto[1]	383	1			T1	4		T2	2		T7	1
auto[1]	auto[1]	auto[0]	5216	1			T7	44		T13	9		T23	102
auto[1]	auto[1]	auto[1]	92	1			T7	3		T42	1		T167	1