Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20437

1

T1

209

T2

68

T5

8

auto[1]

14399

1

T1

284

T2

73

T8

30

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3870	1			T1	83		T10	12		T13	20
values[1]	4634	1			T2	28		T13	31		T28	40
values[2]	4441	1			T1	40		T5	8		T11	22
values[3]	4221	1			T1	120		T2	27		T29	26
values[4]	4480	1			T2	41		T23	123		T171	8
values[5]	5393	1			T1	40		T2	45		T8	30
values[6]	4175	1			T1	210		T13	46		T23	125
values[7]	3622	1			T6	18		T23	46		T202	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4480	1			T1	40		T2	55		T10	12
values[1]	4234	1			T1	40		T2	21		T6	18
values[2]	4483	1			T23	20		T172	2		T35	14
values[3]	4309	1			T2	45		T8	30		T11	22
values[4]	4450	1			T1	63		T23	66		T86	14
values[5]	4713	1			T1	86		T13	54		T145	34
values[6]	3612	1			T1	124		T2	20		T5	8
values[7]	4555	1			T1	140		T13	20		T23	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	263	1			T1	6		T10	12		T34	15
auto[0]	values[0]	values[1]	244	1			T32	17		T174	11		T196	11
auto[0]	values[0]	values[2]	417	1			T165	28		T31	10		T20	10
auto[0]	values[0]	values[3]	304	1			T31	12		T196	12		T186	11
auto[0]	values[0]	values[4]	205	1			T1	12		T28	12		T88	10
auto[0]	values[0]	values[5]	206	1			T145	34		T169	4		T88	17
auto[0]	values[0]	values[6]	240	1			T34	12		T139	13		T186	11
auto[0]	values[0]	values[7]	339	1			T13	15		T163	4		T32	52
auto[0]	values[1]	values[0]	328	1			T2	8		T28	11		T88	11
auto[0]	values[1]	values[1]	284	1			T85	12		T174	10		T178	13
auto[0]	values[1]	values[2]	550	1			T136	14		T178	108		T20	12
auto[0]	values[1]	values[3]	309	1			T88	19		T31	14		T174	13
auto[0]	values[1]	values[4]	400	1			T31	14		T34	49		T196	10
auto[0]	values[1]	values[5]	336	1			T13	23		T210	6		T70	14
auto[0]	values[1]	values[6]	247	1			T174	50		T70	30		T228	12
auto[0]	values[1]	values[7]	124	1			T28	14		T88	17		T70	10
auto[0]	values[2]	values[0]	254	1			T1	7		T32	10		T70	24
auto[0]	values[2]	values[1]	285	1			T1	12		T70	12		T209	10
auto[0]	values[2]	values[2]	379	1			T28	12		T206	16		T178	24
auto[0]	values[2]	values[3]	218	1			T11	22		T88	13		T225	15
auto[0]	values[2]	values[4]	442	1			T86	14		T31	11		T70	13
auto[0]	values[2]	values[5]	429	1			T23	46		T208	26		T258	70
auto[0]	values[2]	values[6]	188	1			T5	8		T190	14		T192	26
auto[0]	values[2]	values[7]	214	1			T164	30		T70	12		T20	12
auto[0]	values[3]	values[0]	481	1			T2	20		T184	20		T27	24
auto[0]	values[3]	values[1]	266	1			T29	26		T164	29		T179	18
auto[0]	values[3]	values[2]	267	1			T172	2		T28	11		T32	13
auto[0]	values[3]	values[3]	500	1			T23	42		T177	2		T88	12
auto[0]	values[3]	values[4]	177	1			T23	12		T28	20		T34	12
auto[0]	values[3]	values[5]	238	1			T23	12		T31	11		T53	10
auto[0]	values[3]	values[6]	210	1			T23	54		T178	9		T139	15
auto[0]	values[3]	values[7]	342	1			T1	16		T183	18		T174	11
auto[0]	values[4]	values[0]	343	1			T28	4		T259	20		T20	15
auto[0]	values[4]	values[1]	389	1			T2	7		T23	54		T174	32
auto[0]	values[4]	values[2]	244	1			T35	14		T162	20		T176	10
auto[0]	values[4]	values[3]	427	1			T28	10		T88	12		T32	31
auto[0]	values[4]	values[4]	275	1			T31	13		T174	25		T139	15
auto[0]	values[4]	values[5]	312	1			T170	10		T107	10		T174	11
auto[0]	values[4]	values[6]	364	1			T2	7		T23	55		T188	12
auto[0]	values[4]	values[7]	320	1			T70	16		T138	20		T190	13
auto[0]	values[5]	values[0]	417	1			T23	14		T198	4		T88	14
auto[0]	values[5]	values[1]	543	1			T1	13		T23	163		T83	4
auto[0]	values[5]	values[2]	349	1			T23	11		T31	9		T194	20
auto[0]	values[5]	values[3]	446	1			T2	26		T23	9		T31	13
auto[0]	values[5]	values[4]	500	1			T23	13		T28	55		T178	8
auto[0]	values[5]	values[5]	279	1			T23	15		T260	12		T32	14
auto[0]	values[5]	values[6]	285	1			T23	6		T187	24		T139	14
auto[0]	values[5]	values[7]	548	1			T1	12		T164	46		T31	21
auto[0]	values[6]	values[0]	281	1			T13	15		T31	15		T34	15
auto[0]	values[6]	values[1]	323	1			T32	14		T34	9		T174	11
auto[0]	values[6]	values[2]	457	1			T174	8		T190	23		T228	17
auto[0]	values[6]	values[3]	156	1			T261	10		T262	2		T186	22
auto[0]	values[6]	values[4]	250	1			T23	11		T195	4		T190	11
auto[0]	values[6]	values[5]	403	1			T1	16		T13	18		T23	75
auto[0]	values[6]	values[6]	419	1			T1	115		T23	11		T34	39
auto[0]	values[6]	values[7]	293	1			T70	15		T228	14		T197	6
auto[0]	values[7]	values[0]	261	1			T28	28		T70	11		T178	73
auto[0]	values[7]	values[1]	235	1			T6	18		T202	10		T32	8
auto[0]	values[7]	values[2]	334	1			T84	28		T178	16		T179	64
auto[0]	values[7]	values[3]	436	1			T23	22		T20	16		T176	10
auto[0]	values[7]	values[4]	227	1			T174	14		T136	27		T70	11
auto[0]	values[7]	values[5]	281	1			T213	4		T28	12		T31	15
auto[0]	values[7]	values[6]	204	1			T88	13		T136	23		T70	15
auto[0]	values[7]	values[7]	150	1			T23	9		T31	10		T32	20
auto[1]	values[0]	values[0]	177	1			T1	14		T34	5		T46	3
auto[1]	values[0]	values[1]	169	1			T32	9		T174	9		T196	9
auto[1]	values[0]	values[2]	244	1			T31	10		T20	16		T139	18
auto[1]	values[0]	values[3]	203	1			T31	8		T196	8		T186	9
auto[1]	values[0]	values[4]	229	1			T1	51		T28	8		T88	11
auto[1]	values[0]	values[5]	181	1			T88	10		T32	11		T176	8
auto[1]	values[0]	values[6]	160	1			T34	8		T139	8		T186	17
auto[1]	values[0]	values[7]	289	1			T13	5		T32	11		T192	10
auto[1]	values[1]	values[0]	237	1			T2	20		T28	9		T88	9
auto[1]	values[1]	values[1]	323	1			T174	111		T178	62		T196	8
auto[1]	values[1]	values[2]	137	1			T136	6		T178	5		T20	8
auto[1]	values[1]	values[3]	219	1			T88	7		T31	6		T174	7
auto[1]	values[1]	values[4]	304	1			T31	7		T34	38		T196	10
auto[1]	values[1]	values[5]	458	1			T13	8		T70	11		T178	20
auto[1]	values[1]	values[6]	256	1			T174	6		T70	12		T228	29
auto[1]	values[1]	values[7]	122	1			T28	6		T88	9		T70	10
auto[1]	values[2]	values[0]	311	1			T1	13		T32	12		T70	16
auto[1]	values[2]	values[1]	210	1			T1	8		T70	8		T178	9
auto[1]	values[2]	values[2]	229	1			T28	8		T178	85		T179	18
auto[1]	values[2]	values[3]	167	1			T88	14		T225	5		T185	14
auto[1]	values[2]	values[4]	340	1			T31	9		T70	7		T178	15
auto[1]	values[2]	values[5]	377	1			T23	10		T178	8		T179	9
auto[1]	values[2]	values[6]	161	1			T190	6		T192	8		T180	9
auto[1]	values[2]	values[7]	237	1			T164	9		T70	30		T20	14
auto[1]	values[3]	values[0]	238	1			T2	7		T31	9		T174	11
auto[1]	values[3]	values[1]	154	1			T164	6		T57	2		T179	7
auto[1]	values[3]	values[2]	117	1			T28	9		T32	15		T229	7
auto[1]	values[3]	values[3]	235	1			T23	14		T88	9		T31	6
auto[1]	values[3]	values[4]	227	1			T23	11		T28	73		T34	8
auto[1]	values[3]	values[5]	205	1			T23	8		T31	9		T138	9
auto[1]	values[3]	values[6]	115	1			T23	9		T178	11		T139	8
auto[1]	values[3]	values[7]	449	1			T1	104		T174	9		T178	94
auto[1]	values[4]	values[0]	299	1			T28	90		T20	5		T139	7
auto[1]	values[4]	values[1]	195	1			T2	14		T23	8		T174	6
auto[1]	values[4]	values[2]	201	1			T176	10		T192	10		T240	33
auto[1]	values[4]	values[3]	151	1			T28	10		T88	8		T32	8
auto[1]	values[4]	values[4]	198	1			T31	17		T174	33		T139	5
auto[1]	values[4]	values[5]	255	1			T171	8		T174	9		T70	33
auto[1]	values[4]	values[6]	241	1			T2	13		T23	6		T34	2
auto[1]	values[4]	values[7]	266	1			T70	4		T138	7		T190	9
auto[1]	values[5]	values[0]	225	1			T23	6		T88	28		T228	20
auto[1]	values[5]	values[1]	233	1			T1	7		T12	12		T23	9
auto[1]	values[5]	values[2]	200	1			T23	9		T31	11		T174	7
auto[1]	values[5]	values[3]	298	1			T2	19		T8	30		T23	11
auto[1]	values[5]	values[4]	241	1			T23	7		T30	12		T28	8
auto[1]	values[5]	values[5]	215	1			T23	5		T32	9		T70	10
auto[1]	values[5]	values[6]	236	1			T23	48		T139	8		T189	30
auto[1]	values[5]	values[7]	378	1			T1	8		T164	10		T31	23
auto[1]	values[6]	values[0]	174	1			T13	8		T31	5		T34	8
auto[1]	values[6]	values[1]	156	1			T32	6		T34	12		T174	9
auto[1]	values[6]	values[2]	209	1			T174	12		T190	17		T228	3
auto[1]	values[6]	values[3]	68	1			T186	7		T21	10		T218	9
auto[1]	values[6]	values[4]	148	1			T23	12		T190	9		T192	8
auto[1]	values[6]	values[5]	306	1			T1	70		T13	5		T23	7
auto[1]	values[6]	values[6]	188	1			T1	9		T23	9		T34	11
auto[1]	values[6]	values[7]	344	1			T70	13		T228	6		T197	14
auto[1]	values[7]	values[0]	191	1			T212	36		T28	47		T70	9
auto[1]	values[7]	values[1]	225	1			T32	13		T70	68		T228	9
auto[1]	values[7]	values[2]	149	1			T178	4		T179	9		T185	9
auto[1]	values[7]	values[3]	172	1			T23	4		T20	4		T176	10
auto[1]	values[7]	values[4]	287	1			T33	20		T174	61		T136	20
auto[1]	values[7]	values[5]	232	1			T28	29		T31	5		T34	15
auto[1]	values[7]	values[6]	98	1			T88	8		T136	4		T70	8
auto[1]	values[7]	values[7]	140	1			T23	11		T31	10		T32	25