Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	571	1			T1	2		T2	3		T13	4
auto[ReadAddrCrossIntoMailbox]	406	1			T1	1		T2	5		T13	1
auto[ReadAddrCrossOutOfMailbox]	419	1			T1	4		T2	4		T13	1
auto[ReadAddrCrossAllMailbox]	269	1			T13	1		T145	2		T23	3
auto[ReadAddrOutsideMailbox]	3901	1			T1	40		T2	12		T5	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2771

1

T1

23

T2

12

T5

1

auto[1]

2795

1

T1

24

T2

12

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	974	1			T1	7		T2	2		T8	2
read_ops[0x0b]	869	1			T1	8		T2	1		T8	6
read_ops[0x3b]	907	1			T1	9		T2	3		T5	2
read_ops[0x6b]	923	1			T1	3		T2	2		T8	6
read_ops[0xbb]	992	1			T1	12		T2	9		T13	3
read_ops[0xeb]	901	1			T1	8		T2	7		T6	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T28	1		T259	1		T53	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T23	1		T88	1		T259	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T1	1		T2	1		T23	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T259	1		T31	3		T263	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T23	1		T259	1		T32	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T259	1		T31	2		T34	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T259	1		T32	2		T264	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T164	1		T259	1		T31	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T1	5		T2	1		T8	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	368	1			T1	1		T8	1		T23	7
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T28	1		T31	1		T32	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T31	1		T32	2		T174	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T23	1		T32	1		T34	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T23	1		T178	1		T139	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T23	2		T31	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T1	1		T32	1		T34	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T259	1		T20	1		T138	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T259	1		T31	1		T179	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	326	1			T1	4		T8	3		T10	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T1	3		T2	1		T8	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	49	1			T2	2		T13	1		T145	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T145	1		T23	1		T35	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T164	1		T31	2		T20	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T23	3		T28	2		T31	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T178	1		T228	1		T196	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T23	1		T32	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T28	1		T34	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T13	1		T23	1		T31	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	320	1			T1	5		T5	1		T8	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T1	4		T2	1		T5	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T13	1		T31	1		T34	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	52	1			T13	2		T23	1		T88	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T13	1		T23	1		T28	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T23	1		T178	1		T139	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T23	1		T190	2		T179	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T2	1		T23	1		T28	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T23	1		T88	1		T21	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T32	1		T174	1		T178	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T1	1		T8	3		T12	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T1	2		T2	1		T8	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	60	1			T23	4		T35	2		T31	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T1	1		T23	1		T35	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T2	2		T174	2		T20	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T2	2		T23	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	44	1			T2	1		T23	1		T164	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T1	1		T2	1		T13	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T23	1		T164	2		T31	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T34	1		T20	1		T180	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	358	1			T1	2		T13	2		T145	7
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	338	1			T1	8		T2	3		T145	7
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T2	1		T145	1		T70	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	52	1			T1	1		T145	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T145	1		T23	1		T178	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T145	1		T88	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T1	2		T2	1		T23	3
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T23	1		T31	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	32	1			T145	1		T88	1		T164	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T145	1		T28	1		T259	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T1	3		T2	3		T6	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T1	2		T2	2		T6	1